121 lines
11 KiB
C
121 lines
11 KiB
C
//******************** (C) COPYRIGHT 2020 SmartLogic*******************************
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// FileName : cci550.h
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// Author : lijian, jian.li@smartlogictech.com
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// Date First Issued : 2021-10-30 06:54:48 PM
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// Last Modified : 2022-03-18 09:33:57 PM
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef __CCI550_H__
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#define __CCI550_H__
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#define CCI550_BASE 0X04608000
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#define CCI_CTRL_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X00000)))
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#define CCI_SECR_ACC (*((volatile uint32_t *)(CCI550_BASE + 0X00008)))
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#define CCI_STATUS (*((volatile uint32_t *)(CCI550_BASE + 0X0000C)))
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#define CCI_IMPR_ERR (*((volatile uint32_t *)(CCI550_BASE + 0X00010)))
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#define CCI_QOS_THRESHOLD (*((volatile uint32_t *)(CCI550_BASE + 0X00014)))
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#define CCI_PMU_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X00100)))
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#define CCI_DEBUG_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X00104)))
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#define CCI_PERIPHERAL_ID4 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD0)))
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#define CCI_PERIPHERAL_ID5 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD4)))
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#define CCI_PERIPHERAL_ID6 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD8)))
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#define CCI_PERIPHERAL_ID7 (*((volatile uint32_t *)(CCI550_BASE + 0X00FDC)))
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#define CCI_PERIPHERAL_ID0 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE0)))
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#define CCI_PERIPHERAL_ID1 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE4)))
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#define CCI_PERIPHERAL_ID2 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE8)))
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#define CCI_PERIPHERAL_ID3 (*((volatile uint32_t *)(CCI550_BASE + 0X00FEC)))
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#define CCI_COMPONENT_ID0 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF0)))
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#define CCI_COMPONENT_ID1 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF4)))
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#define CCI_COMPONENT_ID2 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF8)))
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#define CCI_COMPONENT_ID3 (*((volatile uint32_t *)(CCI550_BASE + 0X00FFC)))
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#define SLV0_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X01000)))
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#define SLV0_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01004)))
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#define SLV0_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01100)))
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#define SLV0_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01104)))
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#define SLV0_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X01110)))
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#define SLV1_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X02000)))
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#define SLV1_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02004)))
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#define SLV1_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02100)))
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#define SLV1_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02104)))
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#define SLV1_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X02110)))
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#define SLV2_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X03000)))
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#define SLV2_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03004)))
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#define SLV2_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03100)))
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#define SLV2_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03104)))
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#define SLV2_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X03110)))
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#define SLV3_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X04000)))
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#define SLV3_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04004)))
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#define SLV3_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04100)))
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#define SLV3_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04104)))
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#define SLV3_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X04110)))
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#define SLV4_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X05000)))
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#define SLV4_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05004)))
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#define SLV4_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05100)))
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#define SLV4_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05104)))
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#define SLV4_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X05110)))
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#define SLV5_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X06000)))
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#define SLV5_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06004)))
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#define SLV5_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06100)))
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#define SLV5_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06104)))
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#define SLV5_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X07110)))
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#define SLV6_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X07000)))
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#define SLV6_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07004)))
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#define SLV6_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07100)))
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#define SLV6_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07104)))
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#define SLV6_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X07110)))
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#define PMU0_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X10000)))
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#define PMU0_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X10004)))
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#define PMU0_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X10008)))
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#define PMU0_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X1000C)))
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#define PMU1_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X20000)))
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#define PMU1_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X20004)))
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#define PMU1_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X20008)))
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#define PMU1_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X2000C)))
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#define PMU2_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X30000)))
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#define PMU2_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X30004)))
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#define PMU2_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X30008)))
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#define PMU2_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X3000C)))
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#define PMU3_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X40000)))
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#define PMU3_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X40004)))
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#define PMU3_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X40008)))
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#define PMU3_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X4000C)))
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#define PMU4_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X50000)))
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#define PMU4_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X50004)))
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#define PMU4_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X50008)))
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#define PMU4_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X5000C)))
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#define PMU5_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X60000)))
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#define PMU5_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X60004)))
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#define PMU5_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X60008)))
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#define PMU5_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X6000C)))
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#define PMU6_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X70000)))
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#define PMU6_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X70004)))
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#define PMU6_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X70008)))
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#define PMU6_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X7000C)))
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#define PMU7_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X80000)))
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#define PMU7_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X80004)))
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#define PMU7_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X80008)))
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#define PMU7_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X8000C)))
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#define SLAVE0_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90000)))
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#define SLAVE1_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90004)))
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#define SLAVE2_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90008)))
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#define SLAVE3_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X9000C)))
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#define SLAVE4_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90010)))
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#define SLAVE5_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90014)))
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#define SLAVE6_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90018)))
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#define MASTER0_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90100)))
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#define MASTER1_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90104)))
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#define MASTER2_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90108)))
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#define MASTER3_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X9010C)))
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#define MASTER4_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90110)))
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#define MASTER5_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90114)))
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#define MASTER6_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90118)))
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#endif
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