161 lines
13 KiB
C
161 lines
13 KiB
C
//******************** (C) COPYRIGHT 2020 SmartLogic*******************************
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// FileName : pet_ctrl.h
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// Author : lijian, jian.li@smartlogictech.com
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// Date First Issued : 2020-05-08 07:44:13 AM
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// Last Modified : 2022-04-13 12:31:08 PM
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef __PET_CTRL_C_H__
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#define __PET_CTRL_C_H__
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#define PET_CTRL_BASE 0x091D0000
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#define PET_CRG_BASE 0x091F0000
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#define PET_PLL_CTL_REG0 (*((volatile uint32_t *)(PET_CRG_BASE + 0x00)))
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#define PET_PLL_CTL_REG1 (*((volatile uint32_t *)(PET_CRG_BASE + 0x04)))
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#define PET_PLL_CTL_REG2 (*((volatile uint32_t *)(PET_CRG_BASE + 0x08)))
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#define PET_PLL_CTL_REG3 (*((volatile uint32_t *)(PET_CRG_BASE + 0x0C)))
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#define PET_PLL_CTL_REG4 (*((volatile uint32_t *)(PET_CRG_BASE + 0x10)))
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#define PET_PLLSEL (*((volatile uint32_t *)(PET_CRG_BASE + 4*5)))
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#define PET_ECPRI_PCS_RXCLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*6)))
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#define PET_TMAC_DEVCLK_TX_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*7)))
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#define PET_TMAC_DEVCLK_RX_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*8)))
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#define PET_ECPRI_APBACLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*12)))
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#define PET_ECPRI_SWITCH_SCHCLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*13)))
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#define PET_ECPRI_SWITCH_MAECORECLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*14)))
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#define PET_ECPRI_PCS_TXCLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*15)))
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#define PET_ETH_CLK_EEE_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*16)))
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#define PET_ETHPLL_TEST_CLK_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*17)))
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#define PET_MANTICORE0_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*19)))
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#define PET_MANTICORE1_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*20)))
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#define PET_MANTICORE2_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*21)))
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#define PET_MANTICORE3_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*22)))
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#define PET_MANTICORE4_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*23)))
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#define PET_EQ0_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*24)))
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#define PET_EQ1_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*25)))
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#define PET_EQ2_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*26)))
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#define PET_EQ3_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*27)))
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#define PET_PAMRX0_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*28)))
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#define PET_PAMRX1_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*29)))
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#define PET_PAMRX2_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*30)))
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#define PET_PAMRX3_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*31)))
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#define PET_RX0_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*32)))
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#define PET_RX1_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*33)))
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#define PET_RX2_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*34)))
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#define PET_RX3_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*35)))
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#define PET_TX0_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*36)))
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#define PET_TX1_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*37)))
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#define PET_TX2_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*38)))
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#define PET_TX3_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*39)))
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#define PET_PWR_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*40)))
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#define PET_PCIE_RST_CFG (*((volatile uint32_t *)(PET_CRG_BASE + 4*41)))
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#define PET_CTRL_REG00 (*((volatile uint32_t *)(PET_CTRL_BASE + 4*0)))
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#define PET_RFM_M0_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*1)))
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#define PET_RFM_M0_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*2)))
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#define PET_RFM_M0_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*3)))
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#define PET_RFM_M1_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*4)))
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#define PET_RFM_M1_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*5)))
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#define PET_RFM_M1_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*6)))
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#define PET_TEST_CTRL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*7)))
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#define PET_RFM_ADDR (*((volatile uint32_t *)(PET_CTRL_BASE + 4*8)))
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#define PET_TESTCLK_SEL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*9)))
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#define PET_ADDR0_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*10)))
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#define PET_ADDR0_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*20)))
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#define PET_ADDR0_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*30)))
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#define PET_ADDR0_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*40)))
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#define PET_ADDR1_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*11)))
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#define PET_ADDR1_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*21)))
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#define PET_ADDR1_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*31)))
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#define PET_ADDR1_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*41)))
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#define PET_ADDR2_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*12)))
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#define PET_ADDR2_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*22)))
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#define PET_ADDR2_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*32)))
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#define PET_ADDR2_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*42)))
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#define PET_ADDR3_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*13)))
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#define PET_ADDR3_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*23)))
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#define PET_ADDR3_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*33)))
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#define PET_ADDR3_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*43)))
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#define PET_ADDR4_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*14)))
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#define PET_ADDR4_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*24)))
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#define PET_ADDR4_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*34)))
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#define PET_ADDR4_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*44)))
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#define PET_ADDR5_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*15)))
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#define PET_ADDR5_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*25)))
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#define PET_ADDR5_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*35)))
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#define PET_ADDR5_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*45)))
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#define PET_ADDR6_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*16)))
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#define PET_ADDR6_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*26)))
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#define PET_ADDR6_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*36)))
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#define PET_ADDR6_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*46)))
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#define PET_ADDR7_START_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*17)))
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#define PET_ADDR7_START_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*27)))
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#define PET_ADDR7_END_H (*((volatile uint32_t *)(PET_CTRL_BASE + 4*37)))
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#define PET_ADDR7_END_L (*((volatile uint32_t *)(PET_CTRL_BASE + 4*47)))
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#define PET_PCIE_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*50)))
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#define PET_PCIE_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*51)))
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#define PET_PCIE_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*52)))
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#define PET_SMMU_REGION (*((volatile uint32_t *)(PET_CTRL_BASE + 4*53)))
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#define PET_TMAC_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*54)))
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#define PET_TMAC_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*55)))
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#define PET_TMAC_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*56)))
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#define PET_CCM_CTRL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*57)))
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#define PET_SPACC_ADDR (*((volatile uint32_t *)(PET_CTRL_BASE + 4*58)))
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#define PET_PHY_BS_CTRL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*59)))
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#define PET_DDR_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*60)))
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#define PET_DDR_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*61)))
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#define PET_DDR_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*62)))
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#define PET_DDR_CTRL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*63)))
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#define PET_SM_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*64)))
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#define PET_SM_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*65)))
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#define PET_SM_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*66)))
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#define PET_SM_CTRL (*((volatile uint32_t *)(PET_CTRL_BASE + 4*67)))
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#define PET_PCIE_BUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*68)))
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#define PET_PCIE_RUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 4*69)))
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#define PETRFM_INT_MASK0_PTR ((volatile uint32_t *)(PET_CTRL_BASE + 70*4))
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#define PETRFM_INT_MASK0 (*((volatile uint32_t *)(PET_CTRL_BASE + 70*4)))
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#define PETRFM_INT_MASK1 (*((volatile uint32_t *)(PET_CTRL_BASE + 71*4)))
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#define PETRFM_INT_MASK2 (*((volatile uint32_t *)(PET_CTRL_BASE + 72*4)))
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#define PETRFM_INT_MASK3 (*((volatile uint32_t *)(PET_CTRL_BASE + 73*4)))
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#define PETRFM_INT_MASK4 (*((volatile uint32_t *)(PET_CTRL_BASE + 74*4)))
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#define PETRFM_INT_MASK5 (*((volatile uint32_t *)(PET_CTRL_BASE + 75*4)))
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#define PETRFM_INT_MASK6 (*((volatile uint32_t *)(PET_CTRL_BASE + 76*4)))
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#define PETRFM_INT_MASK7 (*((volatile uint32_t *)(PET_CTRL_BASE + 77*4)))
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#define PETRFM_INT_MASK8 (*((volatile uint32_t *)(PET_CTRL_BASE + 78*4)))
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#define PETRFM_INT_MASK9 (*((volatile uint32_t *)(PET_CTRL_BASE + 79*4)))
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#define PETRFM_INT_MASK10 (*((volatile uint32_t *)(PET_CTRL_BASE + 80*4)))
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#define PETRFM_INT_MASK11 (*((volatile uint32_t *)(PET_CTRL_BASE + 81*4)))
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#define PETRFM_INT_MASK12 (*((volatile uint32_t *)(PET_CTRL_BASE + 82*4)))
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#define PETRFM_INT_MASK13 (*((volatile uint32_t *)(PET_CTRL_BASE + 83*4)))
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#define PETRFM_INT_MASK14 (*((volatile uint32_t *)(PET_CTRL_BASE + 84*4)))
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#define PETRFM_INT_MASK15 (*((volatile uint32_t *)(PET_CTRL_BASE + 85*4)))
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#define PPET_AWUSER_AP_DMA_BM (*((volatile uint32_t *)(PET_CTRL_BASE + 86*4)))
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#define PPET_WUSER_AP_DMA_BM (*((volatile uint32_t *)(PET_CTRL_BASE + 87*4)))
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#define PPET_ARUSER_AP_DMA_BM (*((volatile uint32_t *)(PET_CTRL_BASE + 88*4)))
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#define PPET_REGION_AP_DMA_BM (*((volatile uint32_t *)(PET_CTRL_BASE + 89*4)))
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#define PET_CTC_INTRREG0 (*((volatile uint32_t *)(PET_CTRL_BASE + 90*4)))
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#define PET_CTC_INTRREG1 (*((volatile uint32_t *)(PET_CTRL_BASE + 91*4)))
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#define PET_CTC_INTRREG2 (*((volatile uint32_t *)(PET_CTRL_BASE + 92*4)))
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#define PET_CTC_INTRREG3 (*((volatile uint32_t *)(PET_CTRL_BASE + 93*4)))
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#define PET_CTC_INTRREG4 (*((volatile uint32_t *)(PET_CTRL_BASE + 94*4)))
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#define PET_CTC_INTRREG5 (*((volatile uint32_t *)(PET_CTRL_BASE + 95*4)))
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#define PET_CTC_INTRREG6 (*((volatile uint32_t *)(PET_CTRL_BASE + 96*4)))
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#define EIP2_QOS (*((volatile uint32_t *)(PET_CTRL_BASE + 97*4)))
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#define EIP2_AWUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 116*4)))
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#define EIP2_WUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 117*4)))
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#define EIP2_ARUSER (*((volatile uint32_t *)(PET_CTRL_BASE + 118*4)))
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#endif
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