316 lines
6.5 KiB
C
316 lines
6.5 KiB
C
#include <ucps2-intrin.h>
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#include "spinlock.h"
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#define OSP_APE_SPAIN_LOCK_ADDR (0x931FF00-0x400)
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#define SPINLOCK_BIT_MAP_ADDR (0x931fb40)
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#define DEBUG_NR 16
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unsigned int spin_debug_switch = 0;
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unsigned int g_unspinlock_loop = 0;
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unsigned int g_ddr_spinlock_loop = 0;
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typedef unsigned int uint32_t;
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#define spin_do_write(a,v) __ucps2_store_ext_mem((void *)(a), (uint32_t)v, f_W)
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#define spin_do_read(ptr) __ucps2_load_ext_mem_v((char*)(ptr), f_W)
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unsigned int g_spinlock_count[DEBUG_NR] = {0};
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unsigned int g_unspinlock_count[DEBUG_NR] = {0};
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unsigned int g_spinlock_loop[DEBUG_NR] = {0};
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unsigned int g_spin_count[DEBUG_NR] = {0};
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unsigned char *use_flag = (char*)SPINLOCK_BIT_MAP_ADDR;
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spin_debug_t *spin_debug_info;
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static int test_bit(void *s,unsigned int index)
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{
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unsigned char *f_bit = s;
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f_bit += index >>3;
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return ((*f_bit&(1 <<((index%8)))) != 0);
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}
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static void set_bit(void *s,unsigned int index)
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{
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unsigned char *f_bit = s;
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f_bit += index >> 3;
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*f_bit |= 1<<(index%8);
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}
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static void clear_bit(void *s,unsigned int index)
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{
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unsigned char *f_bit = s;
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f_bit += index >> 3;
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*f_bit &= ~(1 <<(index%8));
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}
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/*
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函数:smart_spin_debug_init
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参数:lock_idx
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参数范围：1--15
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*/
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int smart_spin_debug_init(int lock_idx,unsigned int debug_base_addr, int len_bytes)
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{
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if((lock_idx < 1)||(lock_idx > 15))
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{
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return -1;
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}
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if(debug_base_addr <= 0x10000000)
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{
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return -1;
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}
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if (len_bytes < 16)
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{
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return -2;
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}
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spin_debug_switch = 1;
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spin_debug_info = (spin_debug_t *)debug_base_addr;
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return 0;
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}
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void spin_debug(void * addr , uint32_t v)
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{
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if(spin_debug_switch == 1)
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{
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spin_do_write(addr, v);
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__ucps2_synch(0);
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}
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}
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int smart_spinlock_init(int lock_index)
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{
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int i;
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if((lock_index < 1)||(lock_index > 15))
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{
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return -1;
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}
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if(test_bit(use_flag,lock_index))
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{
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return -2; //
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}
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set_bit(use_flag,lock_index);
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*(volatile unsigned int *)(OSP_APE_SPAIN_LOCK_ADDR+lock_index*4) = 0;
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return 0;
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}
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void smart_spinlock(int lock_index)
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{
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spinlock_t lockval;
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spinlock_t *lock;
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int ret;
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int owner;
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int next;
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if (lock_index > SLOCK_MAX)
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{
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return;
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}
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else
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{
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lock = (spinlock_t*)(OSP_APE_SPAIN_LOCK_ADDR+lock_index*4);
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}
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while (1)
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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next = ((lockval.slock >> 16) & 0x0000ffff);
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owner = next;
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next++;
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lockval.slock &=0x0000ffff;
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lockval.slock |= ((next & 0xffff) << 16);
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ret = __ucps2_atomicst((int *)lock, lockval.slock, f_W);
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if (1 == ret)
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{
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break;
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}
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else
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{
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g_spin_count[lock_index]++;
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spin_debug(&(spin_debug_info->spin_per_ape.g_spin_count) , g_spin_count[lock_index]);
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}
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}
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do
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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g_spinlock_loop[lock_index]++;
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spin_debug(&(spin_debug_info->spin_per_ape.spinlock_loop) , g_spinlock_loop[lock_index]);
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} while (owner != ((lockval.slock & 0x0000ffff)));
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g_spinlock_count[lock_index]++;
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spin_debug(&(spin_debug_info->spin_per_ape.spinlock_count) , g_spinlock_count[lock_index]);
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}
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void smart_spinunlock(int lock_index)
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{
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spinlock_t lockval;
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int ret;
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int atomfail_unlock = 0;
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spinlock_t * lock;
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unsigned int temp_owner = 0;
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if (lock_index > SLOCK_MAX)
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{
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return;
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}
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else
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{
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lock = (spinlock_t*)(OSP_APE_SPAIN_LOCK_ADDR+lock_index*4);
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}
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while (1)
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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temp_owner = (lockval.slock & 0x0000ffff);
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temp_owner ++;
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lockval.slock &= 0xffff0000;
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lockval.slock |= (temp_owner & 0x0000ffff);
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ret = __ucps2_atomicst((int *)lock, lockval.slock, f_W);
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if (1 == ret)
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{
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break;
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}
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else
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{
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// g_unspinlock_loop++;
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// spin_debug(&(spin_debug_info->spin_per_ape.unspinlock_loop) , g_unspinlock_loop);
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}
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}
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g_unspinlock_count[lock_index]++;
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spin_debug(&(spin_debug_info->spin_per_ape.unspinlock_count) , g_unspinlock_count[lock_index]);
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}
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/*
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参数:lock_idx
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参数范围：1--15
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*/
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int smart_get_spin_loop_cnt(int lock_idx)
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{
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return g_spinlock_loop[lock_idx];
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}
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/*
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参数:lock_idx
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参数范围：1--15
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*/
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int smart_get_spin_cnt(int lock_idx)
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{
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return g_spin_count[lock_idx];
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}
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/*
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参数:lock_idx
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参数范围：1--15
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*/
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int smart_get_spinlock_cnt(int lock_idx)
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{
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return g_spinlock_count[lock_idx];
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}
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/*
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参数:lock_idx
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参数范围：1--15
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*/
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int smart_get_unspinlock_cnt(int lock_idx)
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{
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return g_unspinlock_count[lock_idx];
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}
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int smart_ddr_spinlock_init(ddr_spinlock_t *val)
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{
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int i;
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int init_val = 0;
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if(spin_do_read(val->flag_addr) == 0xab3f)
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{
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return -2;
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}
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spin_do_write(val->flag_addr,0xab3f);
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spin_do_write(val->lock_addr,0);
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return 0;
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}
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void smart_ddr_spinlock(ddr_spinlock_t *val)
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{
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spinlock_t lockval;
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volatile unsigned int *lock;
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int ret;
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int owner;
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int next;
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int loop;
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lock = (volatile unsigned int*)(val->lock_addr);
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while (1)
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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next = ((lockval.slock >> 16) & 0x0000ffff);
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owner = next;
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next++;
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lockval.slock &=0x0000ffff;
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lockval.slock |= ((next & 0xffff) << 16);
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ret = __ucps2_atomicst((int *)lock, lockval.slock, f_W);
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if (1 == ret)
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{
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break;
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}
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else
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{
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}
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}
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do
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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g_ddr_spinlock_loop++;
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} while (owner != ((lockval.slock & 0x0000ffff)));
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}
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void smart_ddr_spinunlock(ddr_spinlock_t *val)
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{
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spinlock_t lockval;
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int ret;
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volatile unsigned int * lock;
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unsigned int temp_owner = 0;
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lock =(volatile unsigned int*)val->lock_addr;
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while (1)
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{
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lockval.slock = __ucps2_atomicld((int *)lock, f_W);
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temp_owner = (lockval.slock & 0x0000ffff);
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temp_owner ++;
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lockval.slock &= 0xffff0000;
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lockval.slock |= (temp_owner & 0x0000ffff);
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ret = __ucps2_atomicst((int *)lock, lockval.slock, f_W);
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if (1 == ret)
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{
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break;
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}
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else
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{
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// g_ddr_unspinlock_loop++;
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// spin_do_write(val->unlock_loop_addr,g_ddr_unspinlock_loop);
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}
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}
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}
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