8c59de6c96
2. update New Feature#1347 to dev_ck_v2.1 3. add new interface for ecs rfm1 and ape: spu_get_oam_handle_id for get oam handle_id by inst_id 4. Move Mem_init() from ape to ecs rfm1 5. TEST: 5.1 spu(case0)+arm(case0): pass 5.2 spu(case14)+arm(case20):pass 5.3 spu(case20)+arm(case20):pass 5.4 spu(case21)+arm(case21):pass 5.5 spu(case34)+arm(case5): pass 5.6 spu(case44)+arm(case5): pass
156 lines
3.4 KiB
C
156 lines
3.4 KiB
C
// +FHDR------------------------------------------------------------
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// Copyright (c) 2022 SmartLogic.
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// ALL RIGHTS RESERVED
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// -----------------------------------------------------------------
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// Filename : main.c
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// Author : xianfeng.du
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// Created On : 2022-06-25
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// Last Modified :
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// -----------------------------------------------------------------
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// Description:
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//
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//
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// -FHDR------------------------------------------------------------
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#include "ucp_printf.h"
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#include "rfm1_drv.h"
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#include "ucp_heartbeat.h"
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#include "ecs_rfm_spu1_top.h"
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#include "msg_transfer_queue.h"
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#include "log_server.h"
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#include "ucp_utility.h"
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#include "phy_queue_proc.h"
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#include "cpri_test_mode.h"
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#include "spu_shell.h"
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#include "gtimer_drv.h"
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#include "rfm1_gtimer2.h"
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#include "ecs_rfm_spu1_oam.h"
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#include "phy_para.h"
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#include "hw_cpri.h"
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#include "hwque.h"
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#include "lib_debug_init.h"
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#ifdef TEST_ENABLE
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#include "fh_test.h"
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#endif
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extern void Mem_Init(void);
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#ifdef DDR_MONITOR
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void spu_ddr_monitor()
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{
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if (1 == do_read_volatile(DDR_MONITOR_ENABLE))
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{
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clear_rfm1_gtimer2_1_intcnt();
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gtimer2_int_enable(0);
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do_write(DDR_MONITOR_ENABLE, 0);
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}
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volatile uint32_t nMonitorCnt = do_read_volatile(DDR_MONITOR_CNT);
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__ucps2_synch(0);
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if (nMonitorCnt < get_rfm1_gtimer2_1_intcnt())
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{
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gtimer2_int_disable(0);
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do_write(DDR_MONITOR_CNT, 0);
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}
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}
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#endif
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extern uint32_t gCpriCsuDummyFlag;
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int32_t main(int32_t argc, char* argv[])
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{
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int32_t core_id = 0;
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int32_t ret = 0;
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UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]", get_core_id());
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core_id = get_core_id();
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debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
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ret = spu_lib_debug_init(core_id);
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debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
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#ifdef PALLADIUM_TEST
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int flag = 1;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
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#endif
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spu_log_client_init();
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spu_log_server_init();
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#ifdef PALLADIUM_TEST
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
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#endif
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Mem_Init(); /* call phy function to mem sm */
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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ecs_rfm_spu1_drv_init();
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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ecs_rfm_spu1_msg_transfer_init();
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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spu_shell_init();
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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spu_shell_cpri_cmd();
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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oam_msg_init();
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#ifdef PALLADIUM_TEST
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flag++;
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debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
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#endif
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while (1)
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{
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if (PROTOCOL_CPRI == get_protocol_sel())
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{
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check_cpri();
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check_10ms_offset();
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}
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#ifdef TEST_ENABLE
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do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
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do_write(CSU_RX_TD_SAMPLE, 10000);
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check_test_outcome(0);
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#endif
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phy_queue_polling();
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spu_log_server_proc();
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/* check whether shell commands exist */
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spu_shell_task();
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/* update heartbeat count */
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heart_beat_write();
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#ifdef DDR_MONITOR
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spu_ddr_monitor();
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#endif
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}
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return 0;
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}
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