9cc9b0b094
2. delete tx/rx slot int on ecs_rfm1 for jesd version; 3. modify sfn updating algorithm for jesd version; 4. optimize jesd gpio on/off code; 5. test case: case24/34/44/45/41/42.
91 lines
1.9 KiB
C
91 lines
1.9 KiB
C
#ifndef _GPIO_DRV_H_
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#define _GPIO_DRV_H_
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#include "dw_apb_gpio.h"
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#include "typedef.h"
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#define JESD_RF_CH_NUM 4
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#define JESD_GPIOGROUP_NUM 9
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typedef enum _tagGpioLValid
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{
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LOW_AS_VALID = 0,
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HIGH_AS_VALID
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}gpioLValid;
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typedef enum _tagJesdGpioTRCH
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{
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JESD_TRANS_TX = 0,
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JESD_RF_TX = 1,
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JESD_ANT_TX = 2,
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JESD_TRANS_RX = 3,
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JESD_RF_RX = 4,
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JESD_ANT_RX = 5,
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JESD_TRANS_ORX = 6,
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JESD_RF_ORX = 7,
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JESD_ANT_ORX = 8,
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JESD_TRCH_MAXNUM = 9
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}jesdGpioTRch;
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typedef enum _tagGpioState
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{
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GPIO_OFF = 0,
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GPIO_ON = 1
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}jesdGpioState;
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typedef struct _tagGpioInfo
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{
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uint8_t pinId; // 0~31
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uint8_t vaFlag; // 0: low as valid; 1: high as valid
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}stGpioInfo;
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typedef struct _tagRfGpioInfo
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{
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uint32_t pinInfo; // 1 bit 1 pin
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uint32_t validInfo; // 0: low as valid; 1: high as valid
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}stRfGpioInfo;
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typedef struct _tagGpioJesd
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{
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stRfGpioInfo txRfGpioInfo[JESD_RF_CH_NUM];
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stRfGpioInfo rxRfGpioInfo[JESD_RF_CH_NUM];
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stRfGpioInfo orxRfGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo txTransGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo txGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo txAntGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo rxTransGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo rxGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo rxAntGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo orxTransGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo orxGpioInfo[JESD_RF_CH_NUM];
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stGpioInfo orxAntGpioInfo[JESD_RF_CH_NUM];
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}stGpioJesd;
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typedef struct _tagGpioOnBoard
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{
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stGpioJesd jesdGpioInfo;
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stGpioInfo triggerGpioInfo;
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}stGpioOnBoard;
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int32_t hw_gpio_init();
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int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState);
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int32_t set_jesd_all_rf_state(uint8_t nTRCh, uint8_t nState); // tx, rx, orx
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int32_t set_trigger_state(uint8_t nState);
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#if 0
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int32_t set_tx_on();
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int32_t set_tx_off();
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int32_t set_rx_on();
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int32_t set_rx_off();
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#endif
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#endif
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