// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : spu_sw_queue.h
// Author        : 
// Created On    : 2023-01-11
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#ifndef __SPU_LOG_H__
#define __SPU_LOG_H__

#include "typedef.h"
#include "ucp_port.h"
#include "ucp_utility.h"
#include "ucp_tick.h"
#include "ucp_printf.h"
#include "log_client.h"
#include "spu_hw_queue.h"
#include "spu_sw_queue.h"
#define SPU_LOG_TEST_FLAG
#define __LOG __attribute__((section(".LOG")))
extern uint8_t  gu8osp_print_level;
#define STSW_MSG_INFO_SET(stsw_msg_info, str_len, core_id)\
do{\
    stsw_msg_info.u8Head[0]  = SPU_SW_MSG_INFO_HEAD1;\
    stsw_msg_info.u8Head[1]  = SPU_SW_MSG_INFO_HEAD2;\
    stsw_msg_info.u16DataLen = str_len;\
    stsw_msg_info.u8PktType  = PKT_TYPE_PLATFORM_LOG;\
    stsw_msg_info.u8CoreId   = core_id;\
    stsw_msg_info.u16Tail    = 0;}while(0)
#define SPU_VPRINTF_LOG(level,fmt, args...)  do{__LOG static char tmp[] = fmt; \
    int32_t  i32core_id = get_core_id();\
    int32_t  i32ret     = 0;\
    uint32_t u32str_len = 0;\
    uint16_t u16_index  = 0;\
    uint8_t  u8offset   = SPU_SW_MSG_INFO_SIZE;\
    uint8_t *pu8_addr   = NULL;\
    int8_t   i8str[128] = {0};\
    if (level > gu8osp_print_level)\
    {\
        break;\
    }\
    u32str_len = strlen(fmt);\
    memcpy_ucp((char *)i8str, (char *)tmp, u32str_len);\
    __ucps2_synch(0);\
    pu8_addr = spu_log_client_mem_alloc(&u16_index);\
    memset(((char *)pu8_addr), 0, SPU_LOG_CLIENT_BUF_SIZE);\
    u32str_len = spu_vsprint_log(((char *)(pu8_addr+u8offset)), (char *)i8str, ##args);\
    spu_sw_msg_info_t   stsw_msg_info;\
    STSW_MSG_INFO_SET(stsw_msg_info, u32str_len, i32core_id);\
    memcpy_ucp((char *)pu8_addr, (void *)&stsw_msg_info, u8offset);\
    __ucps2_synch(0);\
    SpuLogMsgInfo_t stlog_msg_info;\
    stlog_msg_info.cell_id = 0;\
    stlog_msg_info.core_id = i32core_id;\
    stlog_msg_info.buf_idx = u16_index;\
    stlog_msg_info.buf_size = (u32str_len + u8offset);\
    i32ret=ecs_hw_que_send(ECS_RFM_SPU1_HW_QUEUE, stlog_msg_info.value);\
    } while(0)

typedef enum SPU_LOG_LEVEL
{
    LOG_OFF = 0,
    LOG_ERROR,
    LOG_WARN,
    LOG_INFO,
    LOG_DEBUG,
    LOG_TICK,
}spu_log_level_e;

typedef enum SPU_SW_MSG_PKT_TYPE
{
    PKT_TYPE_STR_LOG      = 0x60,
    PKT_TYPE_BIN_LOG      = 0x61,
    PKT_TYPE_PLATFORM_LOG = 0x62,
}spu_sw_msg_pkt_type_e;

/* 对外接口 */
void osp_sendLog(int level, char* pbuf, int size, int cell_id);
void osp_sendLog_print(int level, char* pbuf, int size, int cell_id);

/* 对内接口 */
void spu_log_init(uint8_t level);
void spu_log_output(uint8_t level, const char *fmt, ...);
uint8_t spu_log_level_set(spu_log_level_e emlog_level);
uint8_t spu_log_level_get(void);
uint32_t spu_vsprint_log(char *dst, const char *fmt, ...);

#ifdef PCIE_BACKHAUL
void com_debug_log(const char *fmt, ...);
#endif

#endif  /*__SPU_LOG_H__*/

