	.section .text.m0, "ax"
	.file	"LLRDemodulationAsm.m0.asm"
	// DO NOT MODIFY THE CONTENT ABOVE
	.global LLRDemodulationAsm
	LLRDemodulationAsm:

	R1:M[0]->BIU1.T0;
	NOP;
	NOP;
	NOP;
	BIU1:Load(T0)(A++) -> M[0](W1);
	BIU1:Load(T0)(A++) -> M[1](W1);
	BIU1:Load(T0)(A++) -> M[2](W1);
	BIU1:Load(T0)(A++) -> M[3](W1);
	BIU1:Load(T0)(A++) -> M[4](W1);
	BIU1:Load(T0)(A++) -> M[5](W1);
	BIU1:Load(T0)(A++) -> M[6](W1);
	BIU1:Load(T0)(A++) -> M[7](W1);
	BIU1:Load(T0)(A++) -> M[8](W1);
	BIU1:Load(T0)(A++) -> M[9](W1);
	BIU1:Load(T0)(A++) -> M[10](W1);
	BIU1:Load(T0)(A++) -> M[11](W1);
	BIU1:Load(T0)(A++) -> M[12](W1);
	BIU1:Load(T0)(A++) -> M[13](W1);
	BIU1:Load(T0)(A++) -> M[14](W1);
	BIU1:Load(T0)(A++) -> M[15](W1);
	BIU1:Load(T0)(A++) -> M[16](W1);
	BIU1:Load(T0)(A++) -> M[17](W1);
	BIU1:Load(T0)(A++) -> M[18](W1);
	BIU1:Load(T0)(A++) -> M[19](W1);
	BIU1:Load(T0)(A++) -> M[230](W1);
	BIU1:Load(T0)(A++) -> M[231](W1);
	BIU1:Load(T0)(A++) -> M[232](W1);
	BIU1:Load(T0)(A++) -> M[233](W1);
	BIU1:Load(T0)(A++) -> M[24](W1);
	BIU1:Load(T0)(A++) -> M[25](W1);
	BIU1:Load(T0)(A++) -> M[26](W1);
	BIU1:Load(T0)(A++) -> M[27](W1);
	BIU1:Load(T0)(A++) -> M[28](W1);


	R5:PreConfig(M[0]);
	R5:WriteConf(Mfetch)->KI[0-15];
	R0:M[1]->BIU0.T0;//gainMMSE input
	R2:M[2]->BIU2.T1;//Q output
	R0:M[3]->IMA0.T5;//32768
	R2:M[4]->SHU2.T5;
	R1:M[5]->SHU1.T5;
	R0:M[6]->SHU0.T4;
	R0:M[7]->SHU0.T5;
	R3:M[8]->BIU3.T1;//reciprocalNoiseVar_fixed

	IMA1:V(1)->IMA1.T3;
	IMA1:V(511)->IMA1.T2;
	IMA2:V(6)->IMA2.T0;
	IMA2:V(15)->IMA2.T1;
	IMA2:Vhigh(T0,0)->IMA2.T0;
	IMA2:Vhigh(T1,0)->IMA2.T1;
	IMA2:SetShiftmode(T0)->ShiftMode0;
	IMA2:SetShiftmode(T1)->ShiftMode1;
	IMA2:V(1)->IMA2.T5;

	//BIU0:wait 0 || IMA0:wait 9 || SHU2:wait 12 || BIU2:wait 15 || IMA1:wait 14 || SHU1:wait 17 || R0:wait 20 || SHU0:wait 22 || IMA2:wait 25 || IMA3:wait 30 || BIU3:wait 34;
	BIU0:wait 0 || IMA0:wait 10 || SHU2:wait 13 || BIU2:wait 16 || IMA1:wait 14 || SHU1:wait 17 || R0:wait 20 || SHU0:wait 23 || IMA2:wait 26 || IMA3:wait 31 || BIU3:wait 34;

	Mfetch: LpTo %LLRDeMoCyc0 @(KI0);

	BIU0:load(T0)(A++)(Mask)->IMA0.T0 || IMA0:T5-T0(S)(U)->IMA0.T2 || SHU2:Index(T0,T5)(T7=T5+V(32))->BIU2.T0 || BIU2:Store(T0,T1)(A++)(Mask) || IMA1:CompSel(0,T0,T3,T0)(S)(U)->IMA1.T1 || SHU1:Index(T0,T5)->M[63](W1) || R0:M[63]->SHU0.T2 || shu0:Index(T5,T5,T2)->IMA2.T0 || IMA2:0+T0*T2(Shiftmode0)(S)(SSS)->IMA3.T0 || IMA3:T0+T1(S)->BIU3.T0 || BIU3:Store(T0,T1)(A++)(Mask);
	IMA0:First(Ttmp)(S)->SHU2.T0 || SHU2:Index(T0,T7)->BIU2.T0 || BIU2:Store(T0,T1)(A++)(Mask) || IMA1:Ttmp>>9(S)(U)->SHU1.T0 || SHU1:T1+V(0)->M[62](W1) || R0:M[62]->SHU0.T3 || SHU0:T3+V(0)->IMA2.T2 || IMA2:0+T1*T5(Shiftmode1)(S)(SSS)->IMA3.T1;
	IMA0:T2<<Ttmp(S)(U)(T)->IMA1.T0 || IMA1:T1&T2->SHU1.T1 || shu0:Index(T4,T4,T2)->IMA2.T1;

	LLRDeMoCyc0:
	BIU0:Wait 0 ||BIU1:Wait 0 ||BIU2:Wait 0 ||BIU3:Wait 0 ||SHU1:Wait 0 ||SHU0:Wait 0 ||SHU2:Wait 0 ||SHU3:Wait 0 ||IMA0: Wait 0 ||IMA1: Wait 0 ||IMA2: Wait 0 ||IMA3: Wait 0 ||R0:Wait 0 ||R1:Wait 0 ||R2:Wait 0 ||R3:Wait 0   ;
	Mfetch:repeat @(40);


	Mfetch:IF(KI10==0) JUMP %QPSKASM;
	Mfetch:IF(KI11==0) JUMP %QAM16ASM;
	Mfetch:IF(KI12==0) JUMP %QAM64ASM;
	Mfetch:IF(KI13==0) JUMP %QAM256ASM;


	QPSKASM:


	IMA0:V(0)->IMA0.T0||IMA1:V(0)->IMA1.T0||IMA2:V(0)->IMA2.T0||IMA3:V(0)->IMA3.T0;
	NOP;
	IMA0:Vhigh(T0,0)->IMA0.T0||IMA1:Vhigh(T0,0)->IMA1.T0||IMA2:Vhigh(T0,0)->IMA2.T0||IMA3:Vhigh(T0,0)->IMA3.T0;
	NOP;
	IMA0:SetShiftmode(T0)->ShiftMode0||IMA1:SetShiftmode(T0)->ShiftMode0||IMA2:SetShiftmode(T0)->ShiftMode0||IMA3:SetShiftmode(T0)->ShiftMode0;

	IMA0:V(23170)->IMA0.T5||IMA1:V(1)->IMA1.T0;
	nop;
	IMA1:Vhigh(T0,0)->SHU3.T1;

	R0:M[8]->BIU0.T0;//reciprocalNoiseVar_fixed
	R2:M[2]->BIU2.T0;//Q output
	R1:M[9]->BIU1.T1;//INPUT
	R3:M[10]->BIU3.T1;//OUTPUT
	R0:M[11]->SHU0.T5;//
	R1:M[12]->SHU1.T5;//output shu

	//BIU0:wait 0 || SHU0:wait 9 || IMA0:wait 11 || BIU2:wait 1 || SHU3:wait 10 || R1:wait 12 || BIU1:wait 6 || IMA1:wait 15 || shu1:wait 19 || BIU3:wait 22;

	BIU0:wait 0 || SHU0:wait 10 || IMA0:wait 13 || BIU2:wait 0 || SHU3:wait 10 || R1:wait 13 || BIU1:wait 6 || IMA1:wait 16 || shu1:wait 20 || BIU3:wait 23;

	Mfetch: LpTo %DeQPSKCyc @(KI0);
	//QPSK
	BIU0:load(T0)(A++)->SHU0.T0 || SHU0:Index(T0,T0,T5)(T7=T5+V(16))->IMA0.T0 || IMA0:0+T0*T5(Shiftmode0)(S)(SSS)(P)->IMA1.T1 || BIU2:load(T0)(A++)->SHU3.T0 || SHU3:T1+T0->M[230](W3) || R1:M[230]->IMA1.shiftmode0 || BIU1:load(T1)(A++)->IMA1.T0 || IMA1:0+T0*T1(shiftmode0)(s)(sss)(P)->shu1.T0 || shu1:Index(T0,T5)->BIU3.T0 || BIU3:Store(T0,T1)(A++)(Mask);
	SHU0:Index(T0,T0,T7)->IMA0.T0 || IMA0:0+T0*T5(Shiftmode0)(S)(SSS)(P)->IMA1.T1 || BIU2:load(T0)(A++)->SHU3.T0 || SHU3:T1+T0->M[231](W3) || R1:M[231]->IMA1.shiftmode1 || BIU1:load(T1)(A++)->IMA1.T0 || IMA1:0+T0*T1(shiftmode1)(s)(sss)(P)->shu1.T0 || shu1:Index(T0,T5)->BIU3.T0 || BIU3:Store(T0,T1)(A++)(Mask);

	DeQPSKCyc:
	BIU0:Wait 0 ||BIU1:Wait 0 ||BIU2:Wait 0 ||BIU3:Wait 0 ||SHU1:Wait 0 ||SHU0:Wait 0 ||SHU2:Wait 0 ||SHU3:Wait 0 ||IMA0: Wait 0 ||IMA1: Wait 0 ||IMA2: Wait 0 ||IMA3: Wait 0 ||R0:Wait 0 ||R1:Wait 0 ||R2:Wait 0 ||R3:Wait 0   ;
	Mfetch:repeat @(40);
	Mfetch: MPU.STOP;
	//QAM16

	QAM16ASM:


	IMA0:V(0x3e)->IMA0.T0||IMA1:V(0)->IMA1.T0||IMA2:V(15)->IMA2.T0||IMA3:V(0)->IMA3.T0;
	IMA0:V(0)->IMA0.T1||IMA1:V(0)->IMA1.T1||IMA2:V(15)->IMA2.T1||IMA3:V(0)->IMA3.T1;
	IMA0:Vhigh(T0,0)->IMA0.T0||IMA1:Vhigh(T0,0)->IMA1.T0||IMA2:Vhigh(T0,0)->IMA2.T0||IMA3:Vhigh(T0,0)->IMA3.T0;
	IMA0:Vhigh(T1,0)->IMA0.T1||IMA1:Vhigh(T1,0)->IMA1.T1||IMA2:Vhigh(T1,0)->IMA2.T1||IMA3:Vhigh(T1,0)->IMA3.T1;
	IMA0:SetShiftmode(T0)->ShiftMode0||IMA1:SetShiftmode(T0)->ShiftMode0||IMA2:SetShiftmode(T0)->ShiftMode0||IMA3:SetShiftmode(T0)->ShiftMode0;
	IMA0:SetShiftmode(T1)->ShiftMode1||IMA1:SetShiftmode(T1)->ShiftMode1||IMA2:SetShiftmode(T1)->ShiftMode1||IMA3:SetShiftmode(T1)->ShiftMode1;

	IMA1:V(0)->IMA1.T0;
	IMA1:V(0)->IMA1.T0;
	IMA1:Vhigh(T0,0)->SHU3.T1;
	IMA1:Vhigh(T0,0)->SHU3.T2;

	R0:M[8]->BIU0.T0;//reciprocalNoiseVar_fixed
	R2:M[2]->BIU2.T0||R0:M[1]->BIU0.T1;//Q output and gainmmse
	R1:M[9]->BIU1.T1;//INPUT
	R3:M[10]->BIU3.T1;//OUTPUT
	R0:M[11]->SHU0.T5;//
	R1:M[16]->SHU1.T5;//output shu

	R0:PreConfig(M[13]);
	R0:WriteConf(Wlatch0);
	R2:PreConfig(M[14]);
	R2:WriteConf(Rlatch2);
	R2:PreConfig(M[15]);
	R2:WriteConf(Rlatch3);
	IMA0:V(20724)->IMA0.T3;
//BIU0:wait 0 || SHU0:wait 9 || IMA0:wait 11 || BIU1:wait 6 || IMA1:wait 15 || R2:wait 15 || IMA2:wait 17 || BIU2:wait 7 || SHU3:wait 16 || R6:wait 18 || R3:wait 19 || IMA3:wait 21 || SHU1:wait 25 || BIU3:wait 29;
BIU0:wait 0 || SHU0:wait 10 || IMA0:wait 12 || BIU1:wait 6 || IMA1:wait 16 || R2:wait 16 || IMA2:wait 18 || BIU2:wait 7 || SHU3:wait 17 || R6:wait 19 || R3:wait 19 || IMA3:wait 22 || SHU1:wait 26 || BIU3:wait 30;

	Mfetch: LpTo %QAM16ASMCyc @(KI0);
	BIU0:load(T1)(A++)->SHU0.T0 || SHU0:index(T0,T0,T5)(T7=T5+V(16))->IMA0.T0 || IMA0:0+T0*T3(Shiftmode0)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || BIU1:load(T1)(A++)->IMA1.T0  || IMA1:T0->IMA2.T0 ||R2:M[dis(shift)](latch2)->IMA2.T2  || IMA2:0+T0*T5(ShiftMode1)(S)(SSS)->IMA3.T0 || BIU2:load(T0)(A++)->SHU3.T0 || SHU3:T1+T0->M[230](W3) || R6:M[230]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T3 || IMA3:0+T0*T3(shiftmode0)(S)(SSS)(P)->shu1.T0 || shu1:Index(T0,T5) || BIU3:Store(T0,T1)(A++)(Mask);
	BIU0:load(T0)(A++)->SHU0.T1 || SHU0:Index(T1,T1,T5)->IMA0.T1 || IMA0:0+T1*T3(Shiftmode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:ABS(T0)(S)->IMA2.T1 || IMA2:T2-T1*T5(ShiftMode0)(S)(SSS)->IMA3.T1 || SHU3:T2+T0->M[231](W3) || R6:M[231]->IMA3.shiftmode1 || IMA3:0+T1*T3(shiftmode1)(S)(SSS)(P)->shu1.T1 || shu1:Index(T1,T5)->BIU3.T0;
	SHU0:index(T0,T0,T7)->IMA0.T0 || IMA0:0+T0*T3(Shiftmode0)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || BIU1:load(T1)(A++)->IMA1.T0  || IMA1:T0->IMA2.T0 ||R2:M[dis(shift)](latch2)->IMA2.T2  || IMA2:0+T0*T5(ShiftMode1)(S)(SSS)->IMA3.T0 || BIU2:load(T0)(A++)->SHU3.T0 || SHU3:T1+T0->M[230](W3)  || R6:M[230]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T3 || IMA3:0+T0*T3(shiftmode0)(S)(SSS)(P)->shu1.T0 || shu1:Index(T0,T5) || BIU3:Store(T0,T1)(A++)(Mask);
	SHU0:Index(T1,T1,T7)->IMA0.T1 || IMA0:0+T1*T3(Shiftmode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:ABS(T0)(S)->IMA2.T1 || IMA2:T2-T1*T5(ShiftMode0)(S)(SSS)->IMA3.T1 || SHU3:T2+T0->M[231](W3)  || R6:M[231]->IMA3.shiftmode1 || IMA3:0+T1*T3(shiftmode1)(S)(SSS)(P)->shu1.T1 || shu1:Index(T1,T5)->BIU3.T0;

	QAM16ASMCyc:
	BIU0:Wait 0 ||BIU1:Wait 0 ||BIU2:Wait 0 ||BIU3:Wait 0 ||SHU1:Wait 0 ||SHU0:Wait 0 ||SHU2:Wait 0 ||SHU3:Wait 0 ||IMA0: Wait 0 ||IMA1: Wait 0 ||IMA2: Wait 0 ||IMA3: Wait 0 ||R0:Wait 0 ||R1:Wait 0 ||R2:Wait 0 ||R3:Wait 0   ;
	Mfetch:repeat @(40);
	Mfetch: MPU.STOP;


	//QAM64

	QAM64ASM:

	IMA0:V(0x3e)->IMA0.T0||IMA1:V(15)->IMA1.T0||IMA2:V(15)->IMA2.T0||IMA3:V(1)->IMA3.T0;
	IMA0:V(0x3d)->IMA0.T1||IMA1:V(15)->IMA1.T1||IMA2:V(15)->IMA2.T1||IMA3:V(0x3f)->IMA3.T1;
	IMA0:V(0x00)->IMA0.T2||IMA1:V(0)->IMA1.T2||IMA2:V(0)->IMA2.T2||IMA3:V(0x0)->IMA3.T2;
	IMA0:Vhigh(T0,0)->IMA0.T0||IMA1:Vhigh(T0,0)->IMA1.T0||IMA2:Vhigh(T0,0)->IMA2.T0||IMA3:Vhigh(T0,0)->IMA3.T0;
	IMA0:Vhigh(T1,0)->IMA0.T1||IMA1:Vhigh(T1,0)->IMA1.T1||IMA2:Vhigh(T1,0)->IMA2.T1||IMA3:Vhigh(T1,0)->IMA3.T1;
	IMA0:Vhigh(T2,0)->IMA0.T2||IMA1:Vhigh(T2,0)->IMA1.T2||IMA2:Vhigh(T2,0)->IMA2.T2||IMA3:Vhigh(T2,0)->IMA3.T2;
	IMA0:SetShiftmode(T0)->ShiftMode0||IMA1:SetShiftmode(T0)->ShiftMode0||IMA2:SetShiftmode(T0)->ShiftMode0||IMA3:SetShiftmode(T0)->ShiftMode0;
	IMA0:SetShiftmode(T1)->ShiftMode1||IMA1:SetShiftmode(T1)->ShiftMode1||IMA2:SetShiftmode(T1)->ShiftMode1||IMA3:SetShiftmode(T1)->ShiftMode1;
	IMA0:SetShiftmode(T2)->ShiftMode2||IMA1:SetShiftmode(T2)->ShiftMode2||IMA2:SetShiftmode(T2)->ShiftMode2||IMA3:SetShiftmode(T2)->ShiftMode2;

	IMA1:V(0)->IMA1.T0;
	IMA1:V(0x1)->IMA1.T0;
	IMA1:Vhigh(T0,0)->SHU3.T1;
	IMA1:Vhigh(T0,0)->SHU3.T2;

	R0:M[8]->BIU0.T0;//reciprocalNoiseVar_fixed
	R2:M[2]->BIU2.T0||R0:M[1]->BIU0.T1;//Q output and gainmmse
	R1:M[9]->BIU1.T1;//INPUT
	R3:M[10]->BIU3.T1;//OUTPUT
	R0:M[11]->SHU0.T5;//
	R1:M[16]->SHU1.T5;//output shu
	R1:M[16]->SHU1.T4||R2:M[16]->SHU2.T4;
	R1:M[232]->SHU1.T5||R2:M[232]->SHU2.T5;




	R0:PreConfig(M[17]);
	R0:WriteConf(Wlatch0);
	R0:PreConfig(M[18]);
	R0:WriteConf(Rlatch1);
	R0:PreConfig(M[19]);
	R0:WriteConf(Wlatch1);
	R2:PreConfig(M[230]);
	R2:WriteConf(Rlatch2);
	R2:PreConfig(M[231]);
	R2:WriteConf(Rlatch3);
	IMA0:V(20225)->IMA0.T5;
	IMA1:V(1)->IMA1.T5;

	IMA1:V(0xff)->IMA1.T0;
	IMA1:V(0xff)->IMA1.T1;
	IMA1:V(0xff)->IMA1.T2;
	IMA1:Vhigh(T0,0)->SHU3.T1;
	IMA1:Vhigh(T1,0)->SHU3.T2;
	IMA1:Vhigh(T2,0)->SHU3.T3;
//BIU0:wait 0 || SHU0:wait 9 || IMA0:wait 11 || BIU1:wait 7 || R1:wait 16 || IMA1:wait 16 || R2:wait 23 || IMA2:wait 25 || BIU2:wait 17 || SHU3:wait 26 || R6:wait 29 || R3:wait 30 || IMA3:wait 32 || SHU1:wait 36 || SHU2:wait 39 || BIU3:wait 42;
BIU0:wait 0 || SHU0:wait 10 || IMA0:wait 12 || BIU1:wait 6 || R1:wait 16 || IMA1:wait 17 || R2:wait 23 || IMA2:wait 26 || BIU2:wait 17 || SHU3:wait 27 || R6:wait 30 || R3:wait 30 || IMA3:wait 33 || SHU1:wait 37 || SHU2:wait 40 || BIU3:wait 43;

	Mfetch: LpTo %QAM64ASMCyc @(KI0);

	BIU0:load(T1)(A++)->SHU0.T0  || SHU0:index(T0,T0,T5)(T7=T5+V(16))->IMA0.T0 || IMA0:0+T0*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W0)(latch0) || BIU1:load(T1)(A++)->IMA1.T0  || R1:M[dis(shift)](latch1)->IMA1.T2 || IMA1:ABS(T0)(S)->IMA1.T1 ||R2:M[dis(shift)](latch2)->IMA2.T1 || IMA2:ABS(T1)(S)->IMA2.T4 || BIU2:load(T0)(A++)->SHU3.T0 || SHU3:T1+T0->M[230](W3) || R6:M[230]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T5  || IMA3:0+T2*T5(shiftmode0)(S)(SSS)(P)->SHU1.T0 || SHU1:Index(T0,T4) || shu2:Index(T0,T4) || BIU3:Store(T0,T1)(A++)(MASK);
	BIU0:load(T0)(A++)->SHU0.T1  || SHU0:index(T0,T0,T7)->IMA0.T1 || IMA0:0+T1*T5(ShiftMode0)(S)(SSS)(P)->M[dis(shift)](W0)(latch0)  || BIU1:load(T1)(A++)->IMA1.T3  || R1:M[dis(shift)](latch1)->IMA1.T2 || IMA1:ABS(T3)(S)->IMA1.T1 ||R2:M[dis(shift)](latch2)->IMA2.T1 || IMA2:ABS(T1)(S)->IMA2.T4 || SHU3:T2+T0->M[231](W3) || R6:M[231]->IMA3.shiftmode1 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode1)(S)(SSS)(P)->SHU1.T1 || SHU1:Index(T1,T4)->SHU1.T3 || shu2:Index(T1,T4)->shu2.T3;
	SHU0:Index(T1,T1,T5)->IMA0.T2 || IMA0:0+T0*T5(ShiftMode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0)  || IMA1:T2-T1*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W1)(latch1) ||R2:M[dis(shift)](latch2)->IMA2.T2 || IMA2:T2-T4*T5(ShiftMode1)(S)(SSS)->IMA3.T2  || SHU3:T3+T0->M[232](W3) || R6:M[232]->IMA3.shiftmode2 || R3:M[dis(shift)](latch3)->IMA3.T1  || IMA3:0+T1*T5(shiftmode2)(S)(SSS)(P)->SHU1.T2 || SHU1:Index(T2,T5) || shu2:Index(T2,T5) || BIU3:Store(T0,T1)(A++)(MASK);
	SHU0:Index(T1,T1,T7)->IMA0.T3 || IMA0:0+T1*T5(ShiftMode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0)  || IMA1:T2-T1*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W1)(latch1) ||R2:M[dis(shift)](latch2)->IMA2.T2 || IMA2:T2-T4*T5(ShiftMode1)(S)(SSS)->IMA3.T3  || BIU2:load(T0)(A++)->SHU3.T0  || SHU3:T1+T0->M[233](W3) || R6:M[233]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T5  || IMA3:0+T3*T5(shiftmode0)(S)(SSS)(P)->SHU2.T0 || SHU1:Index(T3,T5)(T7=T5+V(32))->BIU3.T0 || shu2:Index(T3,T5)(T7=T5+V(32))->BIU3.T0 || BIU3:Store(T0,T1)(A++)(MASK);
	IMA0:0+T2*T5(ShiftMode2)(S)(SSS)(P)->M[dis(shift)](W0)(latch0)  || IMA1:0+T0*T5(ShiftMode1)(S)(SSS)->M[dis(shift)](W1)(latch1)  || SHU3:T2+T0->M[234](W3) || R6:M[234]->IMA3.shiftmode1 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode1)(S)(SSS)(P)->SHU2.T1 || SHU1:Index(T2,T7) || shu2:Index(T2,T7);
	IMA0:0+T3*T5(ShiftMode2)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:0+T3*T5(ShiftMode1)(S)(SSS)->M[dis(shift)](W1)(latch1)  || SHU3:T3+T0->M[235](W3) || R6:M[235]->IMA3.shiftmode2 || R3:M[dis(shift)](latch3)->IMA3.T1  || IMA3:0+T1*T5(shiftmode2)(S)(SSS)(P)->SHU2.T2 || SHU1:Index(T3,T7)->BIU3.T0 || shu2:Index(T3,T7)->BIU3.T0 || BIU3:Store(T0,T1)(A++)(MASK);

	QAM64ASMCyc:
	BIU0:Wait 0 ||BIU1:Wait 0 ||BIU2:Wait 0 ||BIU3:Wait 0 ||SHU1:Wait 0 ||SHU0:Wait 0 ||SHU2:Wait 0 ||SHU3:Wait 0 ||IMA0: Wait 0 ||IMA1: Wait 0 ||IMA2: Wait 0 ||IMA3: Wait 0 ||R0:Wait 0 ||R1:Wait 0 ||R2:Wait 0 ||R3:Wait 0   ;
	Mfetch:repeat @(50);
	Mfetch: MPU.STOP;
	//QAM256
	QAM256ASM:
	IMA0:V(0xFE)->IMA0.T0||IMA1:V(15)->IMA1.T0||IMA2:V(15)->IMA2.T0||IMA3:V(1)->IMA3.T0;
	IMA0:V(0xFD)->IMA0.T1||IMA1:V(15)->IMA1.T1||IMA2:V(15)->IMA2.T1||IMA3:V(0x3f)->IMA3.T1;
	IMA0:V(0xFC)->IMA0.T2||IMA1:V(15)->IMA1.T2||IMA2:V(0)->IMA2.T2||IMA3:V(0x0)->IMA3.T2;
	IMA0:V(0x00)->IMA0.T3||IMA1:V(15)->IMA1.T3||IMA2:V(0)->IMA2.T3||IMA3:V(0x0)->IMA3.T3;
	IMA0:Vhigh(T0,0)->IMA0.T0||IMA1:Vhigh(T0,0)->IMA1.T0||IMA2:Vhigh(T0,0)->IMA2.T0||IMA3:Vhigh(T0,0)->IMA3.T0;
	IMA0:Vhigh(T1,0)->IMA0.T1||IMA1:Vhigh(T1,0)->IMA1.T1||IMA2:Vhigh(T1,0)->IMA2.T1||IMA3:Vhigh(T1,0)->IMA3.T1;
	IMA0:Vhigh(T2,0)->IMA0.T2||IMA1:Vhigh(T2,0)->IMA1.T2||IMA2:Vhigh(T2,0)->IMA2.T2||IMA3:Vhigh(T2,0)->IMA3.T2;
	IMA0:Vhigh(T3,0)->IMA0.T3||IMA1:Vhigh(T3,0)->IMA1.T3||IMA2:Vhigh(T3,0)->IMA2.T3||IMA3:Vhigh(T3,0)->IMA3.T3;
	IMA0:SetShiftmode(T0)->ShiftMode0||IMA1:SetShiftmode(T0)->ShiftMode0||IMA2:SetShiftmode(T0)->ShiftMode0||IMA3:SetShiftmode(T0)->ShiftMode0;
	IMA0:SetShiftmode(T1)->ShiftMode1||IMA1:SetShiftmode(T1)->ShiftMode1||IMA2:SetShiftmode(T1)->ShiftMode1||IMA3:SetShiftmode(T1)->ShiftMode1;
	IMA0:SetShiftmode(T2)->ShiftMode2||IMA1:SetShiftmode(T2)->ShiftMode2||IMA2:SetShiftmode(T2)->ShiftMode2||IMA3:SetShiftmode(T2)->ShiftMode2;
	IMA0:SetShiftmode(T3)->ShiftMode3||IMA1:SetShiftmode(T3)->ShiftMode3||IMA2:SetShiftmode(T3)->ShiftMode3||IMA3:SetShiftmode(T3)->ShiftMode3;

	IMA1:V(0)->IMA1.T0;
	IMA1:V(0x1)->IMA1.T0;
	IMA1:Vhigh(T0,0)->SHU3.T1;
	IMA1:Vhigh(T0,0)->SHU3.T2;

	R0:M[8]->BIU0.T0;//reciprocalNoiseVar_fixed
	R2:M[2]->BIU2.T0||R0:M[1]->BIU0.T1;//Q output and gainmmse
	R1:M[9]->BIU1.T1;//INPUT
	R3:M[10]->BIU3.T1;//OUTPUT
	R0:M[11]->SHU0.T5;//
	R1:M[16]->SHU1.T5;//output shu
	R1:M[16]->SHU1.T4||R2:M[16]->SHU2.T4;
	R1:M[232]->SHU1.T5||R2:M[232]->SHU2.T5;




	R0:PreConfig(M[17]);
	R0:WriteConf(Wlatch0);
	R0:PreConfig(M[19]);
	R0:WriteConf(Wlatch1);
	R2:PreConfig(M[233]);
	R2:WriteConf(Wlatch2);

	R2:PreConfig(M[25]);
	R2:WriteConf(Rlatch2);
	R2:PreConfig(M[24]);
	R2:WriteConf(Rlatch3);


	IMA0:V(20105)->IMA0.T5;
	IMA1:V(1)->IMA1.T5;

	IMA1:V(0xff)->IMA1.T0;
	IMA1:V(0xff)->IMA1.T1;
	IMA1:V(0xff)->IMA1.T2;
	IMA1:Vhigh(T0,00)->SHU3.T1;
	IMA1:Vhigh(T1,0)->SHU3.T2;
	IMA1:Vhigh(T2,0)->SHU3.T3;

	R1:M[16]->SHU1.T4||R2:M[16]->SHU2.T4;
	R1:M[16]->SHU1.T5||R2:M[16]->SHU2.T5;
	R1:M[26]->SHU1.T6||R2:M[26]->SHU2.T6;


//BIU0:wait 0 || SHU0:wait 9 || IMA0:wait 11 || BIU1:wait 7 || R1:wait 16 || IMA1:wait 16 || R2:wait 22 || IMA2:wait 24 || BIU2:wait 20 || SHU3:wait 29 || R6:wait 31 || R3:wait 32 || IMA3:wait 34 || SHU1:wait 38 || SHU2:wait 42 || BIU3:wait 46;
BIU0:wait 0 || SHU0:wait 10 || IMA0:wait 12 || BIU1:wait 6 || R1:wait 16 || IMA1:wait 17 || R2:wait 22 || IMA2:wait 25 || BIU2:wait 20 || SHU3:wait 30 || R6:wait 32 || R3:wait 32 || IMA3:wait 35 || SHU1:wait 39 || SHU2:wait 43 || BIU3:wait 47;

	Mfetch: LpTo %QAM256ASMCyc @(KI0);
	BIU0:load(T1)(A++)->SHU0.T0  || SHU0:index(T0,T0,T5)(T7=T5+V(16))->IMA0.T0 || IMA0:0+T0*T5(ShiftMode0)(S)(SSS)(P)->M[63](W0) || BIU1:load(T1)(A++)->IMA1.T0  || R1:M[63]->IMA1.T2 || IMA1:ABS(T0)(S)->IMA1.T4 ||R2:M[dis(shift)](latch2)->IMA2.T3 || IMA2:T3-T1*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W2)(latch2)&IMA2.T4  || BIU2:load(T0)(A++)->SHU3.T0  || SHU3:T3+T0->M[230](W3) || R6:M[230]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T5  || IMA3:0+T2*T5(shiftmode0)(S)(SSS)(P)->SHU1.T0  || SHU1:Index(T0,T4) || SHU2:Index(T0,T4) || BIU3:Store(T0,T1)(A++);
	BIU0:load(T0)(A++)->SHU0.T1  || SHU0:index(T0,T0,T7)->IMA0.T1 || IMA0:0+T1*T5(ShiftMode0)(S)(SSS)(P)->M[62](W0) || BIU1:load(T1)(A++)->IMA1.T3  || R1:M[62]->IMA1.T2 || IMA1:ABS(T3)(S)->IMA1.T4 ||R2:M[dis(shift)](latch2)->IMA2.T3 || IMA2:T3-T2*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W2)(latch2)&IMA2.T4  || SHU3:T1+T0->M[231](W3) || R6:M[231]->IMA3.shiftmode1 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode1)(S)(SSS)(P)->SHU1.T1  || SHU1:Index(T1,T4)->SHU1.T2 || SHU2:Index(T1,T4)->SHU2.T2;
	SHU0:Index(T1,T1,T5)->IMA0.T2 || IMA0:0+T0*T5(ShiftMode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:T2-T4*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W1)(latch1)&IMA1.T4  || SHU3:T2+T0->M[232](W3)  || R6:M[232]->IMA3.shiftmode2 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode2)(S)(SSS)(P)->SHU1.T0  || SHU1:Index(T0,T4) || SHU2:Index(T0,T4) || BIU3:Store(T0,T1)(A++);
	SHU0:Index(T1,T1,T7)->IMA0.T3 || IMA0:0+T1*T5(ShiftMode1)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:T2-T4*T5(ShiftMode0)(S)(SSS)->M[dis(shift)](W1)(latch1)&IMA1.T4  || SHU3:T3+T0->M[233](W3)  || R6:M[233]->IMA3.shiftmode3 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode3)(S)(SSS)(P)->SHU1.T1  || SHU1:Index(T1,T4)->SHU1.T3 || SHU2:Index(T1,T4)->SHU2.T3;
	IMA0:0+T0*T5(ShiftMode2)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:0+T0*T5(ShiftMode1)(S)(SSS)->M[dis(shift)](W1)(latch1) || IMA2:Abs(T4)(S)->IMA2.T4 || BIU2:load(T0)(A++)->SHU3.T0  || SHU3:T3+T0->M[230](W3) || R6:M[230]->IMA3.shiftmode0 || R3:M[dis(shift)](latch3)->IMA3.T5  || IMA3:0+T3*T5(shiftmode0)(S)(SSS)(P)->SHU2.T0  || BIU3:Store(T0,T1)(A++);
	IMA0:0+T1*T5(ShiftMode2)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:0+T3*T5(ShiftMode1)(S)(SSS)->M[dis(shift)](W1)(latch1) || IMA2:Abs(T4)(S)->IMA2.T4 || SHU3:T1+T0->M[231](W3) || R6:M[231]->IMA3.shiftmode1 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode1)(S)(SSS)(P)->SHU2.T1  || SHU1:Index(T3,T2,T6)(T7=T6+V(16))->BIU3.T0 || SHU2:Index(T3,T2,T6)(T7=T6+V(16))->BIU3.T0;
	IMA0:0+T2*T5(ShiftMode3)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:Abs(T4)(S)->IMA2.T1 ||R2:M[dis(shift)](latch2)->IMA2.T3 || IMA2:T3-T4*T5(ShiftMode1)(S)(SSS)->IMA3.T2  || SHU3:T2+T0->M[232](W3)  || R6:M[232]->IMA3.shiftmode2 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode2)(S)(SSS)(P)->SHU2.T0 || BIU3:Store(T0,T1)(A++);
	IMA0:0+T3*T5(ShiftMode3)(S)(SSS)(P)->M[dis(shift)](W0)(latch0) || IMA1:Abs(T4)(S)->IMA2.T2 ||R2:M[dis(shift)](latch2)->IMA2.T3 || IMA2:T3-T4*T5(ShiftMode1)(S)(SSS)->IMA3.T3  || SHU3:T3+T0->M[233](W3)  || R6:M[233]->IMA3.shiftmode3 || R3:M[dis(shift)](latch3)->IMA3.T0  || IMA3:0+T0*T5(shiftmode3)(S)(SSS)(P)->SHU2.T1  || SHU1:Index(T3,T2,T7)->BIU3.T0 || SHU2:Index(T3,T2,T7)->BIU3.T0;

	QAM256ASMCyc:
	BIU0:Wait 0 ||BIU1:Wait 0 ||BIU2:Wait 0 ||BIU3:Wait 0 ||SHU1:Wait 0 ||SHU0:Wait 0 ||SHU2:Wait 0 ||SHU3:Wait 0 ||IMA0: Wait 0 ||IMA1: Wait 0 ||IMA2: Wait 0 ||IMA3: Wait 0 ||R0:Wait 0 ||R1:Wait 0 ||R2:Wait 0 ||R3:Wait 0   ;
	Mfetch:repeat @(50);
	Mfetch: MPU.STOP;



