#ifndef _JESD_CSU_NR_FDD_H_
#define _JESD_CSU_NR_FDD_H_

#include "typedef.h"

//#define JESD_SAMP_FREQ_245760K

// 4 ant, NR
#define JESD_NRFDD_ANT_NUM							    4 // 2 // 
#define JESD_NRFDD_MARGIN							    5
#define JESD_NRFDD_SLOT_NUM						        10

#define JESD_NRFDD_TX_NODENUM						    10
#define JESD_NRFDD_RX_NODENUM						    10

#ifdef JESD_SAMP_FREQ_245760K /* Sample Freq: 245.76MHz */
#define JESD_NRFDD_SLOT_SAM_CNT						    122880
#else /* Sample Freq: 122.88MHz */
#define JESD_NRFDD_SLOT_SAM_CNT						    61440
#endif

#define JESD_NRFDD_TX_LIST_ADDR							0x8A000000 // 0x0a4f4000// 
#define JESD_NRFDD_RX_LIST_ADDR							0x8A008000 // 0x0a4f4800// 


#if 0
#define JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x9F00000	// SM2
#define JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x9FF0400	// SM2
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0xA380000	// SM5
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0xA290400	// SM4
#else
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR			0x60F00000	// 0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR			0x610E0000	// 0x1E0000
#endif

#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR			0x6BC00000	// 0x9F00000	// 0x1E0000
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR			0x6BDE0000	// 0xA380000	// 0x1E0000

int32_t jesd_csu_init_nr_fdd();

int32_t jesd_csu_init_nr_fdd_slot0();

int32_t jesd_csu_init_nr_fdd_rx_slot2();


#if 0
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();

int32_t jesd_csu_start_nr_7ds2u();
int32_t jesd_csu_start_nr_7ds2u_8t8r();
#endif

#endif

