	.section .text.m0, "ax"
	.file	"IFFT4096Asm.m0.asm"
	// DO NOT MODIFY THE CONTENT ABOVE

.global IFFT4096Asm

IFFT4096Asm:

	    R2:M[0]->BIU2.T3;
	    NOP;
	    NOP;
		NOP;
		BIU2:Load(T3)(A++) -> M[0](Mode0);	//ConfigMFetch
		BIU2:Load(T3)(A++) -> M[1](Mode0);	//BIU0.T0 reset biu0.t2
		BIU2:Load(T3)(A++) -> M[2](Mode0);	//BIU1.T0 reset biu1.t2
		BIU2:Load(T3)(A++) -> M[3](Mode0);	//BIU0.T2_input_1@00000
		BIU2:Load(T3)(A++) -> M[4](Mode0);	//BIU1.T2_input_2@40000
		BIU2:Load(T3)(A++) -> M[5](Mode0);	//BIU3.T1_output@80000
		BIU2:Load(T3)(A++) -> M[6](Mode0);	//BIU2.T1_output@82000
		BIU2:Load(T3)(A++) -> M[7](Mode0);	//BIU3.T2_output@c0000
		BIU2:Load(T3)(A++) -> M[8](Mode0);	//BIU2.T2_output@c2000
		BIU2:Load(T3)(A++) -> M[9](Mode0);	//biu1.T1 move_factor_addr0
		BIU2:Load(T3)(A++) -> M[10](Mode0);	//biu1.T3 move_factor_addr1
		BIU2:Load(T3)(A++) -> M[1](Mode0);	//index_factor1
		BIU2:Load(T3)(A++) -> M[133](Mode0);	//index_factor2
		BIU2:Load(T3)(A++) -> M[134](Mode0); //index_factor3
		BIU2:Load(T3)(A++) -> M[135](Mode0)|| 	R0:M[1] -> BIU0.T0(Mode0)|| 	R1:M[2] -> BIU1.T0(Mode0);	//index_factor4_1
		BIU2:Load(T3)(A++) -> M[136](Mode0)|| 	R0:M[3] -> BIU0.T2(Mode0)|| 	R1:M[4] -> BIU1.T2(Mode0)|| 	R3:M[5] -> BIU3.T1(Mode0);	//index_factor4_2
		R5:PreConfig(M[0])(Mode0);
		BIU2:Load(T3)(A++) -> M[137](Mode0)|| 	R5:WriteConf(Mfetch)->KI[0-3](Mode0);	//index_factor5_1
		BIU2:Load(T3)(A++) -> M[138](Mode0)|| 	R2:M[6] -> BIU2.T1(Mode0)|| 	R3:M[7] -> BIU3.T2(Mode0);	//index_factor5_2
		BIU2:Load(T3)(A++) -> M[51](Mode0)|| 	R2:M[8] -> BIU2.T2(Mode0)|| 	R1:M[9] -> BIU1.T1(Mode0);
		BIU2:Load(T3)(A++) -> M[41](Mode0)|| 	R1:M[10] -> BIU1.T3(Mode0);
		R5:PreConfig(M[0])(Mode0);
		BIU2:Load(T3)(A++) -> M[60](Mode0)|| 	R5:WriteConf(Mfetch)->KI[4-7](Mode0);
		BIU2:Load(T3)(A++) -> M[61](Mode0);
		BIU2:Load(T3)(A++) -> M[32](Mode0);
		BIU2:Load(T3)(A++) -> M[33](Mode0);
		BIU2:Load(T3)(A++) -> M[142](Mode0);
		BIU2:Load(T3)(A++) -> M[143](Mode0);
		MFetch:REPEAT @(8);
		R0:M[1] -> SHU0.T2(Mode0);
		R0:M[32] -> SHU0.T0(Mode0);
	    R0:M[133] -> SHU0.T2(Mode0);
		R0:M[134] -> SHU0.T2(Mode0);
		SHU0:Index(T0,T2) -> M[132](W4) (Mode0)|| R0:M[135] -> SHU0.T2(Mode0);
		SHU0:Index(T0,T2) -> M[133](W4) (Mode0)|| R0:M[136] -> SHU0.T2(Mode0)|| R1:M[33] -> SHU1.T1(Mode0);
		SHU0:Index(T0,T2) -> M[134](W4) (Mode0)|| R1:M[137] -> SHU1.T2(Mode0);
		SHU0:Index(T0,T2) -> M[135](W4) (Mode0)|| R1:M[138] -> SHU1.T2(Mode0);
		SHU0:Index(T0,T2) -> M[136](W4) (Mode0);
		SHU1:Index(T1,T2) -> M[137] (Mode0);
		SHU1:Index(T1,T2) -> M[138] (Mode0);
		R0:M[51] -> SHU0.T6(Mode0)||	R1:M[51] -> SHU1.T6(Mode0)|| 	R2:M[51] -> SHU2.T6(Mode0)|| 	R3:M[51] -> SHU3.T6(Mode0);
		R0:M[41] -> SHU0.T7(Mode0)|| 	R1:M[41] -> SHU1.T7(Mode0)|| 	R2:M[41] -> SHU2.T7(Mode0)|| 	R3:M[41] -> SHU3.T7(Mode0);
		R0:M[60] -> SHU0.T4(Mode0)|| 	R1:M[60] -> SHU1.T4(Mode0)|| 	R2:M[60] -> SHU2.T4(Mode0)|| 	R3:M[60] -> SHU3.T4(Mode0);
		R0:M[61] -> SHU0.T5(Mode0)|| 	R1:M[61] -> SHU1.T5(Mode0)|| 	R2:M[61] -> SHU2.T5(Mode0)|| 	R3:M[61] -> SHU3.T5(Mode0);
        NOP;
		MFetch:LPTO %FFT4096AsmCyc0 @(KI2 - 0);	//cycle all 64FFT code
		BIU1:Load( T1)(A++) -> SHU0.T0(Mode0);
		BIU1:Load(T3)(A++) -> SHU1.T0(Mode0);
		R0:M[1] -> SHU0.T7||R1:M[1] -> SHU1.T7;
		MFetch:REPEAT @(9);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[10](Mode0);
        SHU1: T2 -V(1)->M[20](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2-V(1)->M[11](Mode0);
		SHU1: T2-V(1)->M[21](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2-V(1)->M[12](Mode0);
		SHU1: T2-V(1)->M[22](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2-V(1)->M[13](Mode0);
		SHU1: T2-V(1)->M[23](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2-V(1)->M[14](Mode0);
		SHU1: T2-V(1)->M[24](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2-V(1)->M[15](Mode0);
		SHU1: T2-V(1)->M[25](Mode0);

		R0:M[10] -> IMA0.T0(Mode0)|| 	R2:M[20] -> IMA2.T0(Mode0)|| 	R1:M[10] -> IMA1.T0(Mode0)|| 	R3:M[20] -> IMA3.T0(Mode0);
		R0:M[11] -> IMA0.T1(Mode0)|| 	R2:M[21] -> IMA2.T1(Mode0)|| 	R1:M[11] -> IMA1.T1(Mode0)|| 	R3:M[21] -> IMA3.T1(Mode0);
		R0:M[12] -> IMA0.T2(Mode0)|| 	R2:M[22] -> IMA2.T2(Mode0)|| 	R1:M[12] -> IMA1.T2(Mode0)|| 	R3:M[22] -> IMA3.T2(Mode0);
		R0:M[13] -> IMA0.T3(Mode0)|| 	R2:M[23] -> IMA2.T3(Mode0)|| 	R1:M[13] -> IMA1.T3(Mode0)|| 	R3:M[23] -> IMA3.T3(Mode0);
		IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
		IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
		IMA0: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA1: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA2: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA3: SetShiftMode (T2) -> SHIFTMODE2 (Mode0);
		IMA0: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA1: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA2: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA3: SetShiftMode (T3) -> SHIFTMODE3 (Mode0);
		R0:M[41] -> SHU0.T7(Mode0)|| 	R1:M[41] -> SHU1.T7||R3:M[132] -> IMA2.T2(Mode0);

		//shiftmode
		BIU0:Wait 0 || BIU2:Wait 50  || R0:Wait 29 || R4:Wait 14 || R1:Wait 12 || R5:Wait 20 || SHU0:Wait 15 || SHU1:Wait 14 || IMA0:Wait 15 || IMA1:Wait 23 || BIU1:Wait 4 || BIU3:Wait 54 || R2:Wait 33 || R6:Wait 19 || R3:Wait 34 || R7:Wait 24 || SHU2:Wait 18 || SHU3:Wait 19 || IMA2:Wait 21 || IMA3:Wait 27 ;

		MFetch:LPTO %FFT4096AsmCyc1 @(KI0 - 0);
			//
BIU0:Load(T2)(A++)(BR) -> SHU1.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[32] -> SHU1.T0(Mode0) || R4:M[132] -> IMA0.T2(Mode0) || R1:M[10] -> IMA0.T0(Mode0) || R5:M[10] -> IMA1.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA0.T0(Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[42] -> SHU3.T0(Mode0) || R6:M[133] -> IMA2.T4(Mode0) || R3:M[14] -> IMA2.T0(Mode0) || R7:M[10] -> IMA3.T0(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[33] -> SHU1.T1(Mode0) || R4:M[133] -> IMA0.T4(Mode0) || R1:M[11] -> IMA0.T1(Mode0) || R5:M[11] -> IMA1.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA0.T1 (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[43] -> SHU3.T1(Mode0) || R6:M[134] -> IMA2.T5(Mode0) || R3:M[15] -> IMA2.T1(Mode0) || R7:M[11] -> IMA3.T1(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1(Mode0) || SHU3:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[34] -> SHU1.T2(Mode0) || R4:M[134] -> IMA0.T5(Mode0) || R5:M[132] -> IMA1.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[44] -> SHU3.T2(Mode0) || R7:M[132] -> IMA3.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[35] -> SHU1.T3(Mode0) || R5:M[133] -> IMA1.T4(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[45] -> SHU3.T3(Mode0) || R7:M[133] -> IMA3.T4(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || SHU3:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[134] -> IMA1.T5(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R7:M[134] -> IMA3.T5(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[36] -> SHU0.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA1.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[46] -> SHU2.T0(Mode0) || SHU2:Index(T0, T1, T6) -> IMA3.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[42] (W2) & SHU2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[37] -> SHU0.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[47] -> SHU2.T1(Mode0) || SHU2:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[43] (W2) & SHU2.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[38] -> SHU0.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA1.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[32] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[36] (W1) & SHU1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[48] -> SHU2.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[44] (W2) & SHU2.T2(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[46] (W3) & SHU3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[39] -> SHU0.T3(Mode0) || SHU0:Index(T2, T3, T7) -> IMA1.T1(Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[33] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[37] (W1) & SHU1.T1(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[49] -> SHU2.T3(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[45] (W2) & SHU2.T3(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[47] (W3) & SHU3.T1(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[34] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[38] (W1) & SHU1.T2(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[48] (W3) & SHU3.T2(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[35] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[39] (W1) & SHU1.T3(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[32] -> BIU2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[49] (W3) & SHU3.T3(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[14] -> IMA1.T2(Mode0) || IMA1: SetShiftMode (T2) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[33] -> BIU2.T0(Mode0) || R3:M[10] -> IMA2.T5(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[15] -> IMA1.T3(Mode0) || IMA1: SetShiftMode (T3) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[34] -> BIU2.T0(Mode0) || R3:M[11] -> IMA2.T4(Mode0);
R2:M[35] -> BIU2.T0(Mode0) || IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
R1:M[14] -> IMA0.T0(Mode0) || SHU0:Index(T1, T0, T4) -> IMA0.T3(Mode0) || R2:M[42] -> BIU2.T0(Mode0) || R6:M[135] -> IMA2.T4(Mode0) || R7:M[14] -> IMA3.T0(Mode0) || IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
R4:M[135] -> IMA0.T2(Mode0) || R1:M[15] -> IMA0.T1(Mode0) || SHU0:Index(T1, T0, T5) -> IMA0.T1(Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || R2:M[43] -> BIU2.T0(Mode0) || R6:M[136] -> IMA2.T2(Mode0) || R7:M[15] -> IMA3.T1(Mode0) || SHU2:Index(T1, T0, T4) -> IMA2.T0(Mode0) || SHU3:Index(T1, T0, T4) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
R4:M[136] -> IMA0.T4(Mode0) || SHU0:Index(T3, T2, T4) -> IMA0.T3(Mode0) || SHU1:Index(T1, T0, T4) -> IMA0.T0(Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || R2:M[44] -> BIU2.T0(Mode0) || SHU2:Index(T1, T0, T5) -> IMA2.T1(Mode0) || SHU3:Index(T1, T0, T5) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
R5:M[135] -> IMA1.T2(Mode0) || SHU0:Index(T3, T2, T5) -> IMA0.T1(Mode0) || SHU1:Index(T1, T0, T5) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[45] -> BIU2.T0(Mode0) || R7:M[135] -> IMA3.T4(Mode0) || SHU2:Index(T3, T2, T4) -> IMA2.T0(Mode0) || SHU3:Index(T3, T2, T4) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R5:M[136] -> IMA1.T4(Mode0) || SHU1:Index(T3, T2, T4) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[36] -> BIU2.T0(Mode0) || R6:M[137] -> IMA2.T5(Mode0) || R7:M[136] -> IMA3.T2(Mode0) || SHU2:Index(T3, T2, T5) -> IMA2.T1(Mode0) || SHU3:Index(T3, T2, T5) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R4:M[137] -> IMA0.T5(Mode0) || SHU1:Index(T3, T2, T5) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[37] -> BIU2.T0(Mode0) || R6:M[138] -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R4:M[138] -> IMA0.T3(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[38] -> BIU2.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R5:M[137] -> IMA1.T5(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[39] -> BIU2.T0(Mode0) || R7:M[137] -> IMA3.T5(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R5:M[138] -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[46] -> BIU2.T0(Mode0) || R6:M[142] -> IMA2.T4(Mode0) || R7:M[138] -> IMA3.T3(Mode0) || SHU3:Index(T1, T0, T4) -> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R4:M[142] -> IMA0.T2(Mode0) || SHU0:Index(T1, T0, T4) -> IMA1.T0(Mode0) || SHU1:Index(T1, T0, T4) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[47] -> BIU2.T0(Mode0) || R6:M[143] -> IMA2.T2(Mode0) || SHU3:Index(T1, T0, T5) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[42] (W2) & SHU2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R4:M[143] -> IMA0.T4(Mode0) || SHU0:Index(T1, T0, T5) -> IMA1.T1(Mode0) || SHU1:Index(T1, T0, T5) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[48] -> BIU2.T0(Mode0) || SHU2:Index(T1, T0, T4) -> IMA3.T3(Mode0) || SHU3:Index(T3, T2, T4) -> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[43] (W2) & SHU2.T1(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R5:M[142] -> IMA1.T2(Mode0) || SHU0:Index(T3, T2, T4) -> IMA1.T0(Mode0) || SHU1:Index(T3, T2, T4) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[32] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[36] (W1) & SHU1.T0(Mode0) || R2:M[49] -> BIU2.T0(Mode0) || R7:M[142] -> IMA3.T4(Mode0) || SHU2:Index(T1, T0, T5) -> IMA3.T1(Mode0) || SHU3:Index(T3, T2, T5) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[44] (W2) & SHU2.T2(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[46] (W3) & SHU3.T0(Mode0);
R5:M[143] -> IMA1.T5(Mode0) || SHU0:Index(T3, T2, T5) -> IMA1.T1(Mode0) || SHU1:Index(T3, T2, T5) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[33] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[37] (W1) & SHU1.T1(Mode0) || R7:M[143] -> IMA3.T2(Mode0) || SHU2:Index(T3, T2, T4) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[45] (W2) & SHU2.T3(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[47] (W3) & SHU3.T1(Mode0);
IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[34] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[38] (W1) & SHU1.T2(Mode0) || SHU2:Index(T3, T2, T5) -> IMA3.T1(Mode0) || IMA2: SetShiftMode (T5) -> SHIFTMODE0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[48] (W3) & SHU3.T2(Mode0);
IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[35] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[39] (W1) & SHU1.T3(Mode0) || IMA2: SetShiftMode (T4) -> SHIFTMODE1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[49] (W3) & SHU3.T3(Mode0);
NOP;
R6:M[132] -> IMA2.T2(Mode0);
NOP;
NOP;
SHU0:T0 + V(0)->  BIU3.T0(Mode0);
SHU0:T1 + V(0) -> BIU3.T0(Mode0) || SHU2:T0 + V(0)->  BIU3.T0(Mode0);
SHU0:T2 + V(0) -> BIU3.T0(Mode0) || SHU2:T1 + V(0) -> BIU3.T0(Mode0);
SHU0:T3 + V(0) -> BIU3.T0(Mode0) || SHU2:T2 + V(0) -> BIU3.T0(Mode0);
SHU2:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
NOP;
NOP;
SHU3:T0 + V(0)->  BIU3.T0(Mode0);
SHU1:T0 + V(0)->  BIU3.T0(Mode0) || SHU3:T1 + V(0) -> BIU3.T0(Mode0);
SHU1:T1 + V(0) -> BIU3.T0(Mode0) || SHU3:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:T2 + V(0) -> BIU3.T0(Mode0) || SHU3:T3 + V(0) -> BIU3.T0(Mode0);
SHU1:T3 + V(0) -> BIU3.T0(Mode0);
NOP;

		FFT4096AsmCyc1:
	BIU2:Wait 0  || 	BIU3:Wait 0 || 	BIU0:Wait 0  || 	BIU1:Wait 0  || 	IMA0: Wait 0 || 	IMA1: Wait 0 || 	IMA2: Wait 0 || 	IMA3: Wait 0 || 	R0:Wait 0 || 	R1:Wait 0 || 	R2:Wait 0 || 	R3:Wait 0 || 	R4:Wait 0 || 	R5:Wait 0 || 	R6:Wait 0 || 	R7:Wait 0  || 	SHU0:Wait 0 || 	SHU1:Wait 0 || 	SHU2:Wait 0 || 	SHU3:Wait 0  ;
	MFetch:REPEAT @(60);
		BIU0:T0[0]+T0[1]-> T2[0](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[0](Mode0);
		BIU0:T0[0]+T0[1]-> T2[1](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[1](Mode0);
		BIU0:T0[0]+T0[1]-> T2[2](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[2](Mode0);
		BIU0:T0[0]+T0[1]-> T0[0](Mode0)|| 	BIU1:T0[0]+T0[1]-> T0[0](Mode0);

		FFT4096AsmCyc0:

	////////////////////////////////////////////////////////////////////
		BIU2:Load(T3)(A++) -> M[0](Mode0);	//BIU2.T1_output
		BIU2:Load(T3)(A++) -> M[1](Mode0);	//BIU2.T2_output
		BIU2:Load(T3)(A++) -> M[2](Mode0);	//BIU3.T1_output
		BIU2:Load(T3)(A++) -> M[3](Mode0);	//BIU3.T2_output
		BIU2:Load(T3)(A++) -> M[4](Mode0);	//BIU0.T2_input
		BIU2:Load(T3)(A++) -> M[5](Mode0);	//BIU1.T2_input
		BIU2:Load(T3)(A++) -> M[6](Mode0);	//BIU0.T0_input
		BIU2:Load(T3)(A++) -> M[7](Mode0);	//BIU1.T0_input
		BIU2:Load(T3)(A++) -> M[8](Mode0);	//BIU0.T3_butterfly
		BIU2:Load(T3)(A++) -> M[9](Mode0);	//BIU0.T1_butterfly
		BIU2:Load(T3)(A++) -> M[10](Mode0);	//biu1.T1 move_factor_addr
		BIU2:Load(T3)(A++) -> M[11](Mode0);	//biu1.T3 move_factor_addr
		BIU2:Load(T3)(A++) -> M[60](Mode0);
		BIU2:Load(T3)(A++) -> M[61](Mode0);
		BIU2:Load(T3)(A++) -> M[62](Mode0);
		BIU2:Load(T3)(A++) -> M[63](Mode0);
		BIU2:Load(T3)(A++) -> M[140](Mode0)|| 	R2:M[0] -> BIU2.T1(Mode0)|| 	R3:M[2] -> BIU3.T1(Mode0);	//index_factor7_1
		BIU2:Load(T3)(A++) -> M[141](Mode0)|| 	R2:M[1] -> BIU2.T2(Mode0)|| 	R3:M[3] -> BIU3.T2(Mode0);	//index_factor7_2
		BIU2:Load(T3)(A++) -> M[142](Mode0)|| 	R0:M[4] -> BIU0.T2(Mode0)|| 	R1:M[5] -> BIU1.T2(Mode0);	//index_factor8_1
		BIU2:Load(T3)(A++) -> M[143](Mode0)|| 	R0:M[6] -> BIU0.T0(Mode0)|| 	R1:M[7] -> BIU1.T0(Mode0);	//index_factor8_2
		BIU2:Load(T3)(A++) -> M[144](Mode0)|| 	R0:M[8] -> BIU0.T3(Mode0);	//index_factor9_1
		BIU2:Load(T3)(A++) -> M[145](Mode0)|| 	R0:M[9] -> BIU0.T1(Mode0);	//index_factor9_2
		BIU2:Load(T3)(A++) -> M[146](Mode0)|| 	R1:M[10] -> BIU1.T1(Mode0);	//index_factor10_1
		BIU2:Load(T3)(A++) -> M[147](Mode0)|| 	R1:M[11] -> BIU1.T3(Mode0);	//index_factor10_2
		BIU2:Load(T3)(A++) -> M[50](Mode0);	//index_factor10_3
		BIU2:Load(T3)(A++) -> M[149](Mode0);	//index_factor10_4
		BIU2:Load(T3)(A++) -> M[152](Mode0);	//index_factor11_1
		BIU2:Load(T3)(A++) -> M[153](Mode0);	//index_factor11_2
		R0:M[60] -> SHU0.T6(Mode0)|| 	R2:M[60] -> SHU2.T6(Mode0)|| 	R3:M[60] -> SHU3.T6(Mode0);
		R0:M[61] -> SHU0.T7(Mode0)|| 	R2:M[61] -> SHU2.T7(Mode0)|| 	R3:M[61] -> SHU3.T7(Mode0);

		MFetch:LPTO %FFT4096AsmCyc4 @(KI4 - 0);	//symbol
		BIU1:Load(T1)(A++) -> SHU0.T0(Mode0);
		BIU1:Load(T3)(A++) -> SHU1.T0(Mode0);
		R0:M[140] -> SHU0.T7(Mode0)||R1:M[140] -> SHU1.T7(Mode0);
		MFetch:REPEAT @(9);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[20](Mode0);
        SHU1: T2 -V(1)->M[8](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[21](Mode0);
        SHU1: T2 -V(1)->M[9](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[12](Mode0);
        SHU1: T2 -V(1)->M[18](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[13](Mode0);
        SHU1: T2 -V(1)->M[19](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[30](Mode0);
        SHU1: T2 -V(1)->M[58](Mode0);
		SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
		SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
		SHU0: T2 -V(1)->M[31](Mode0);
        SHU1: T2 -V(1)->M[59](Mode0);
		R0:M[20] -> IMA0.T0(Mode0)|| 	R2:M[8] -> IMA2.T0(Mode0)|| 	R1:M[20] -> IMA1.T0(Mode0)|| 	R3:M[8] -> IMA3.T0(Mode0);
		R0:M[21] -> IMA0.T1(Mode0)|| 	R2:M[9] -> IMA2.T1(Mode0)|| 	R1:M[21] -> IMA1.T1(Mode0)|| 	R3:M[9] -> IMA3.T1(Mode0);
		R0:M[12] -> IMA0.T2(Mode0)|| 	R2:M[18] -> IMA2.T2(Mode0)|| 	R1:M[12] -> IMA1.T2(Mode0)|| 	R3:M[18] -> IMA3.T2(Mode0);
		R0:M[13] -> IMA0.T3(Mode0)|| 	R2:M[19] -> IMA2.T3(Mode0)|| 	R1:M[13] -> IMA1.T3(Mode0)|| 	R3:M[19] -> IMA3.T3(Mode0);
		IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| 	IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
		IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| 	IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
		IMA0: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA1: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA2: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| 	IMA3: SetShiftMode (T2) -> SHIFTMODE2 (Mode0);
		IMA0: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA1: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA2: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| 	IMA3: SetShiftMode (T3) -> SHIFTMODE3 (Mode0);

		R2:M[8] -> SHU2.T3(Mode0)|| 	R3:M[8] -> SHU3.T4(Mode0);
		R2:M[9] -> SHU2.T5(Mode0)|| 	R3:M[9] -> SHU3.T5(Mode0);
		R0:M[61] -> SHU0.T7;
		MFetch:LPTO %FFT4096AsmCyc2 @(KI3 - 0);	//cyle all 64FFT
		 BIU0:Wait 0 || BIU2:Wait 56  || R0:Wait 23   || R4:Wait 15 || R1:Wait 14 || R5:Wait 26 || SHU0:Wait 21 || SHU1:Wait 18 || IMA0:Wait 21 || IMA1:Wait 29 || BIU1:Wait 6 || BIU3:Wait 56 || R2:Wait 36 || R6:Wait 32 || R3:Wait 34 || R7:Wait 44 || SHU2:Wait 18 || SHU3:Wait 20 || IMA3:Wait 21 || IMA2:Wait 29 ;

		MFetch:LPTO %FFT4096AsmCyc3 @(KI1 - 0);	//64FFT cycle
	//cycle_64fft
	//
BIU0:Load(T3)(A++) -> M[172](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[173] -> SHU0.T4(Mode0) || R4:M[20] -> IMA0.T0(Mode0) || R1:M[172] -> SHU1.T4(Mode0) || R5:M[20] -> IMA1.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T4,T2)-> IMA[0,3].T2  (Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[40] -> SHU2.T2(Mode0) || R7:M[155] -> IMA3.T5(Mode0) || R2:M[62] -> SHU2.T6(Mode0) || R6:M[58] -> SHU3.T4(Mode0) || SHU2:T3 + V(0) ->IMA3.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T0 (Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T3)(A++) -> M[173](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[140] -> SHU0.T2(Mode0) || R4:M[21] -> IMA0.T1(Mode0) || R1:M[140] -> SHU1.T2(Mode0) || R5:M[21] -> IMA1.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T4,T2)-> IMA[0,3].T4  (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[41] -> SHU2.T3(Mode0) || R7:M[156] -> IMA3.T4(Mode0) || R2:M[63] -> SHU2.T7(Mode0) || R6:M[59] -> SHU3.T5(Mode0) || SHU2:T5 + V(0) ->IMA3.T1(Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T3)(A++) -> M[174](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[141] -> SHU0.T2(Mode0) || R4:M[60] -> SHU1.T6(Mode0) || R1:M[141] -> SHU1.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA0.T0 (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[42] -> SHU2.T4(Mode0) || R7:M[190] -> IMA3.T5(Mode0) || R6:M[62] -> SHU3.T6(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T0 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[175](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R4:M[61] -> SHU1.T7(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || SHU1:Index(T0, T1, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[43] -> SHU2.T5(Mode0) || R7:M[91] -> IMA3.T3(Mode0) || R6:M[63] -> SHU3.T7(Mode0) || SHU2:Index(T0, T1, T6) -> IMA3.T3(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[176](W4)(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T2(Mode0) || R7:M[92] -> IMA3.T2(Mode0) || SHU2:Index(T0, T1, T7) -> IMA3.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[177](W4)(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R7:M[93] -> IMA3.T4(Mode0) || R2:M[128] -> IMA3.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T3(Mode0) || IMA3: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || SHU0:Index(T4,T2)-> IMA[1,2].T2  (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T5  (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[30] -> SHU2.T3(Mode0) || R7:M[60] -> SHU2.T6(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || SHU3:T4 + V(0) ->IMA2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[142] -> SHU0.T0(Mode0) || R1:M[142] -> SHU1.T3(Mode0) || R5:M[62] -> SHU0.T6(Mode0) || SHU0:Index(T4,T2)-> IMA[1,2].T4  (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T2 (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[31] -> SHU2.T5(Mode0) || R7:M[61] -> SHU2.T7(Mode0) || R6:M[58] -> IMA2.T3(Mode0) || SHU3:T5 + V(0) ->IMA2.T1(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[143] -> SHU0.T5(Mode0) || R1:M[143] -> SHU1.T3(Mode0) || R5:M[63] -> SHU0.T7(Mode0) || SHU0:Index(T0, T1, T6) -> IMA1.T3(Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T4(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T0(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[44] -> SHU3.T5(Mode0) || R6:M[59] -> IMA2.T4(Mode0) || SHU3:Index(T0, T1, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[144] -> SHU0.T6(Mode0) || R1:M[144] -> SHU1.T3(Mode0) || R5:M[62] -> SHU1.T6(Mode0) || SHU0:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T3 (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[45] -> SHU3.T3(Mode0) || SHU3:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T2(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[145] -> SHU0.T7(Mode0) || R1:M[145] -> SHU1.T3(Mode0) || R5:M[63] -> SHU1.T7(Mode0) || SHU0:Index(T2, T3, T6) -> IMA1.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[0] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[4] (W1) & SHU1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || SHU3:Index(T2, T3, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[40] (W3) & SHU3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[44] (W2) & SHU2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T3(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || SHU0:Index(T2, T3, T7) -> IMA1.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[1] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[5] (W1) & SHU1.T1(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[46] -> SHU3.T4(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T3 (Mode0) || SHU3:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[41] (W3) & SHU3.T1(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[45] (W2) & SHU2.T1(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T2(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[0] -> SHU1.T2(Mode0) || SHU0:Index(T4,T0)-> IMA[1,2].T5  (Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[2] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[6] (W1) & SHU1.T2(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T2(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[47] -> SHU3.T5(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[42] (W3) & SHU3.T2(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[46] (W2) & SHU2.T2(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T3(Mode0) || R0:M[1] -> SHU1.T3(Mode0) || R1:M[174] -> SHU1.T1(Mode0) || SHU0:Index(T4,T5)-> IMA[1,2].T3  (Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[3] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[7] (W1) & SHU1.T3(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T3(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T3 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[43] (W3) & SHU3.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[47] (W2) & SHU2.T3(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[2] -> SHU1.T4(Mode0) || R1:M[146] -> SHU1.T4(Mode0) || SHU0:Index(T4,T6)-> IMA[1,2].T5  (Mode0) || SHU1:Index(T1,T4)-> IMA[0,3].T2  (Mode0) || IMA0: SetShiftMode (T5) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1(Mode0) || IMA2: SetShiftMode (T3) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++) -> SHU1.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[3] -> SHU1.T5(Mode0) || R1:M[147] -> SHU1.T5(Mode0) || SHU0:Index(T4,T7)-> IMA[1,2].T2  (Mode0) || SHU1:Index(T1,T5)-> IMA[0,3].T4 (Mode0) || BIU1:Load(T2)(A++) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: SetShiftMode (T4) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++) -> SHU0.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R1:M[50] -> SHU1.T4(Mode0) || SHU1:Index(T1,T4)-> IMA[0,3].T5 (Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || SHU3:T4 + V(0) ->IMA3.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R4:M[30] -> IMA0.T5(Mode0) || R1:M[149] -> SHU1.T5(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T1,T5) -> M[128] (Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[8] -> SHU3.T4(Mode0) || R6:M[157] -> IMA2.T4(Mode0) || SHU3:T5 + V(0) ->IMA3.T1(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T2(Mode0) || R0:M[128] -> IMA0.T2(Mode0) || R1:M[177] -> SHU1.T3(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T3,T4) -> M[155] (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || R2:M[9] -> SHU3.T5(Mode0) || R6:M[60] -> SHU3.T6(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T3 (Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++) -> SHU1.T3(Mode0) || R1:M[152] -> SHU1.T4(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T3,T5) -> M[156] (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || R6:M[61] -> SHU3.T7(Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++) -> SHU0.T2(Mode0) || R0:M[4] -> SHU0.T5(Mode0) || R1:M[153] -> SHU1.T5(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1(Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T3 (Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T3(Mode0) || R0:M[5] -> SHU0.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[0] -> BIU2.T0(Mode0) || R6:M[194] -> IMA2.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T0(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[178](W6)(Mode0) || R0:M[6] -> SHU0.T4(Mode0) || SHU0:Index(T0,T2)-> IMA[1,2].T4  (Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[1] -> BIU2.T0(Mode0) || R6:M[195] -> IMA2.T5(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1(Mode0) || IMA3: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[179](W6)(Mode0) || R0:M[7] -> SHU0.T5(Mode0) || R4:M[175] -> SHU0.T0(Mode0) || R1:M[31] -> IMA0.T1(Mode0) || SHU0:Index(T0,T3)-> IMA[1,2].T2  (Mode0) || SHU1:Index(T4, T5, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R3:M[40] -> BIU3.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0) || R6:M[196] -> IMA2.T4(Mode0) || SHU2:Index(T4, T5, T6) -> IMA3.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[190](W6)(Mode0) || R0:M[178] -> SHU1.T0(Mode0) || R4:M[146] -> SHU0.T2(Mode0) || SHU0:Index(T0,T2)-> IMA[1,2].T5  (Mode0) || SHU1:Index(T4, T5, T7) -> IMA0.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[41] -> BIU3.T0(Mode0) || R2:M[3] -> BIU2.T0(Mode0) || R6:M[197] -> IMA2.T3(Mode0) || SHU2:Index(T4, T5, T7) -> IMA3.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[91](W6)(Mode0) || R0:M[152] -> SHU1.T2(Mode0) || R4:M[147] -> SHU0.T3(Mode0) || R1:M[176] -> SHU1.T3(Mode0) || R5:M[60] -> SHU0.T6(Mode0) || SHU0:Index(T0,T3) -> M[157] (Mode0) || SHU1:Index(T3,T4)-> IMA[0,3].T4  (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[42] -> BIU3.T0(Mode0) || SHU2:T3 + V(0) ->IMA1.T0(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[92](W6)(Mode0) || R0:M[153] -> SHU1.T3(Mode0) || R4:M[50] -> SHU0.T2(Mode0) || R1:M[152] -> SHU1.T4(Mode0) || R5:M[61] -> SHU0.T7(Mode0) || SHU0:Index(T5, T3, T6) -> IMA1.T0(Mode0) || SHU1:Index(T3,T5)-> IMA[0,3].T3  (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[43] -> BIU3.T0(Mode0) || SHU2:T5 + V(0) ->IMA1.T1(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[93](W6)(Mode0) || R0:M[179] -> SHU1.T4(Mode0) || R4:M[149] -> SHU0.T3(Mode0) || R1:M[153] -> SHU1.T5(Mode0) || SHU0:Index(T5, T3, T7) -> IMA1.T1(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || SHU3:Index(T5, T3, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[194](W6)(Mode0) || R5:M[194] -> IMA1.T2(Mode0) || SHU0:Index(T4, T5, T6) -> IMA1.T0(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[0] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[4] (W1) & SHU1.T0(Mode0) || R2:M[8] -> SHU2.T3(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T3(Mode0) || SHU3:Index(T5, T3, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[40] (W3) & SHU3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[44] (W2) & SHU2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[195](W6)(Mode0) || R4:M[155] -> IMA0.T2(Mode0) || R5:M[195] -> IMA1.T5(Mode0) || SHU0:Index(T4, T5, T7) -> IMA1.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[1] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[5] (W1) & SHU1.T1(Mode0) || R2:M[9] -> SHU2.T5(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1(Mode0) || SHU3:Index(T4, T5, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[41] (W3) & SHU3.T1(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[45] (W2) & SHU2.T1(Mode0);
BIU0:Load(T1)(A++) -> M[196](W6)(Mode0) || R4:M[156] -> IMA0.T4(Mode0) || R5:M[196] -> IMA1.T4(Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[2] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[6] (W1) & SHU1.T2(Mode0) || R2:M[4] -> BIU2.T0(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T3(Mode0) || SHU3:Index(T4, T5, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[42] (W3) & SHU3.T2(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[46] (W2) & SHU2.T2(Mode0);
BIU0:Load(T1)(A++) -> M[197](W6)(Mode0) || R4:M[190] -> IMA0.T5(Mode0) || R5:M[197] -> IMA1.T3(Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[3] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[7] (W1) & SHU1.T3(Mode0) || R2:M[5] -> BIU2.T0(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[43] (W3) & SHU3.T3(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[47] (W2) & SHU2.T3(Mode0);
R4:M[91] -> IMA0.T3(Mode0) || SHU0:T0 + V(0)->  BIU2.T0(Mode0) || R3:M[44] -> BIU3.T0(Mode0) || R2:M[6] -> BIU2.T0(Mode0);
R4:M[92] -> IMA0.T2(Mode0) || SHU0:T1 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T0,T2)-> IMA[1,2].T2  (Mode0) || R3:M[45] -> BIU3.T0(Mode0) || R2:M[7] -> BIU2.T0(Mode0) || SHU3:T0 + V(0) -> BIU3.T0(Mode0);
R4:M[93] -> IMA0.T4(Mode0) || SHU0:T2 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T0,T3)-> IMA[1,2].T5  (Mode0) || R3:M[46] -> BIU3.T0(Mode0) || SHU3:T1 + V(0) -> BIU3.T0(Mode0);
R1:M[157] -> IMA1.T4(Mode0) || SHU0:T3 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T4,T2)-> IMA[1,2].T4  (Mode0) || R3:M[47] -> BIU3.T0(Mode0) || SHU3:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:Index(T4,T3)-> IMA[1,2].T3  (Mode0) || SHU3:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
SHU1:T0 + V(0)->  BIU2.T0(Mode0) || SHU2:T0 + V(0)->  BIU3.T0(Mode0);
SHU1:T1 + V(0) -> BIU2.T0(Mode0) || SHU2:T1 + V(0) -> BIU3.T0(Mode0);
SHU1:T2 + V(0) -> BIU2.T0(Mode0) || SHU2:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:T3 + V(0) -> BIU2.T0(Mode0) || SHU2:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
	//
		FFT4096AsmCyc3:
	BIU2:Wait 0  || 	BIU3:Wait 0 || 	BIU0:Wait 0  || 	BIU1:Wait 0  || 	IMA0: Wait 0 || 	IMA1: Wait 0 || 	IMA2: Wait 0 || 	IMA3: Wait 0 || 	R0:Wait 0 || 	R1:Wait 0 || 	R2:Wait 0 || 	R3:Wait 0 || 	R4:Wait 0 || 	R5:Wait 0 || 	R6:Wait 0 || 	R7:Wait 0  || 	SHU0:Wait 0 || 	SHU1:Wait 0 || 	SHU2:Wait 0 || 	SHU3:Wait 0  ;
		MFetch:REPEAT @(60);

		BIU0:4 -> T2[11](Mode0)|| 	BIU1:4 -> T2[11](Mode0);
		BIU0:T0[0]+T0[1]-> T2[0](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[0](Mode0);
		BIU0:T0[0]+T0[1]-> T2[1](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[1](Mode0);
		BIU0:T0[0]+T0[1]-> T2[2](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[2](Mode0);
		BIU0:T0[0]+T0[1]-> T2[3](Mode0)|| 	BIU1:T0[0]+T0[1]-> T2[3](Mode0);
		BIU0:T2[0](S)(L)-> T0[0](L)(Mode0)|| 	BIU1:T2[0](S)(L)-> T0[0](L)(Mode0);
		BIU0:T2[0](S)(MH)-> T0[0](MH)(Mode0)|| 	BIU1:T2[0](S)(MH)-> T0[0](MH)(Mode0);

	FFT4096AsmCyc2:
	FFT4096AsmCyc4:
		MFetch:REPEAT @(10);

		MFetch:MPU.STOP;
