YB_TX_RX_APE_PRJ/Common/inc/mem_def.h

/******************************************************************
 * @file  ucp_mem_def.h
 * @brief:   两片UCP的内存分布头文件
 * @author: xuekun.zhang
 * @Date 2021年1月5日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
 * Change_date         Owner         Change_content
 * 2021年1月5日        xuekun.zhang       create file

*****************************************************************/

#ifndef     UCP_MEM_DEF_H
#define     UCP_MEM_DEF_H

#include "test_macro.h"


//！命名宏定义时需要注意UCP使用的地址
/*********************************UCP************************************************/
#define SM0_BASE                    	(0x09D00000)//1M
#define SM1_BASE                    	(0x09E00000)//1M
#define SM2_BASE                    	(0x09F00000)//1.5M
#define SM3_BASE                    	(0x0A080000)//1.5M
#define SM4_BASE                    	(0x0A200000)//1.5M
#define SM5_BASE                    	(0x0A380000)//1.5M

//空间规划：
/*
    SM0:（）
    SM1：(1M)用于recv_symb双核任务处理的数据临时存放空间
    SM5:（1201/1024KB）用于存放RECV_SYNC后给RECV_SYMB的数据
    SM2:（/1536KB）用于存放Transmitter的输出结果
*/

//len define 
//SM0

//SM1
#define TIME_DATA_SLOT_LEN              (0x0003c000)  //61440*4byte = 240k
//SM2
#define TRANSMITTER_OUT_LEN              (0x0003c000)   //TODO:确定实际长度
//SM3
#define SM3_NR_PUCCH_LUT_LEN		    (0x00040000)  //256K
#define SM3_PHY_MSG_BUFFER_LEN          (0x00000400)  //1K
//SM5
#define SM5_SYMB2_BIT_LEN               (0x00038000)
//DDR
#define TRACE_GRP_LEN                   (0x00000200)  //128Word    

/************************************SM0--1M*************************************************/
#define RECEIVER_BIT_CFG_BASE              (SM0_BASE) 
/************************************SM1---1M ***********************************************/ 
#define RECEIVER_SYMB_OUT               (SM1_BASE)
#define RECEIVER_SYMB_OUT_ODD           (RECEIVER_SYMB_OUT + 0x80000) //512KB each

#ifdef CORE_ODD
// CORE_ODD 的地址
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000 + 0x8000)
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
#else
// 非CORE_ODD 的地址
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000)
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#endif
/************************************SM2--1.5M***********************************************/
#define TRANSMITTER_OUT                    (SM2_BASE)         //4k对齐
/************************************SM3--1.5M***********************************************/
#define SM3_PHY_MSG_BUFFER_ADDR            (SM3_BASE)
#define SM3_PHY_TASKS_MGR_ADDR             (SM3_PHY_MSG_BUFFER_ADDR + SM3_PHY_MSG_BUFFER_LEN)
#define RECEIVER_OUT3                      (SM3_BASE + 0x4000)
/************************************SM4--1.5M***********************************************/
#define RECEIVER_BASE                 (SM4_BASE) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR    (RECEIVER_BASE)
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR    (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR    (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR    (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR    (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR    (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR    (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR  (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)

/************************************SM5--1.5M***********************************************/
//SM5前面区域被占用
#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR  (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t)
#ifdef CORE_ODD
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR  (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN) 
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR  (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN)
#else
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR  (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 2*SM5_SYMB2_BIT_LEN) 
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR  (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 3*SM5_SYMB2_BIT_LEN)
#endif
/**************************************DDR***************************************************/
//1.93GB可用0x14400000-0x8FFFFFFF
#define DDR_PHY_BASE                           (0x14400000) 
#define DDR_ERROR_RECORD_CNT_ADDR              (0x79FF8000)
#define DDR_STATE_RECORD_CNT_ADDR              (0x79FFc000)

//接收端数据来源选择
//---------------TX RX JESD地址接口---------------------------------------------------------
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR	   (0x60F00000)	//0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR	   (0x610E0000)	//0x1E0000


#ifdef TX_RX_LOOP
    #define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR      (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR)  
    #define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR       (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR)
#elif !defined(TX_RX_LOOP) && !defined(RECV_DBG_DATA_TEST)
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR      (0x6BC00000)  //!!!DDR_PHY_BASE 0x1E0000 
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR       (0x6BDE0000)  // 0x1E0000
#else
//---------------RECV测试用DDR空间--------------------------------------
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR	   (0x88800000)	//61440*4
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR	   (0x8883c000)	//
#endif
#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR      (0x6BFC0000)  // 61440*4 用于暂存数据供first_sync处理
#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR      (0x6BFFC000)  // 2048*4 用于暂存数据供first_sync处理
//---------------APE4 RECV START FIRSTSYNC FLAG---------------------------------------------
#define RECV_FIRST_SYNC_START_FLAG             (0x82000000)     //通过手动输入来开始接收端第一次同步   devmem 0x82000000 0xa5a55a5a 32
//---------------APE7 PCIE TO APE4 sync_proc
#define TRANSFORM_REF_PARA_PCIE2SYNC_ADDR      (0x83000000)

//---------------ARM Transmitter比特存放地址，大小SOURCE_DATA_BYTE_LENGTH*SOURCE_DATA_BUFFER_NUM = 313KB
#define SOURCE_DATA_FLAG_DDR_ADDR               (0x84000000)    // SPU READ FLAG
#define SOURCE_DATA_DDR_ADDR                    (0x84C00000)
#define SOURCE_DATA_BUFFER_NUM                  (20)
#define SOURCE_DATA_BYTE_LENGTH                 (16016)
#define SOURCE_DATA_DDR_ADDR_END                (SOURCE_DATA_DDR_ADDR + SOURCE_DATA_BUFFER_NUM*SOURCE_DATA_BYTE_LENGTH + 0x100)
//--------------ARM RECV data存放地址，大小
#define RECV_BIT_OUT_DATA_FLAG_DDR_ADDR               (0x85000000)    // SPU READ FLAG
#define RECV_BIT_OUT_DATA_DDR_ADDR                    (0x85001000)
#define RECV_BIT_OUT_DATA_BUFFER_NUM                  (8)
#define RECV_BIT_OUT_DATA_BYTE_LENGTH                 (16016)
#define RECV_BIT_OUT_DATA_DDR_ADDR_END                (RECV_BIT_OUT_DATA_DDR_ADDR + RECV_BIT_OUT_DATA_BUFFER_NUM*RECV_BIT_OUT_DATA_BYTE_LENGTH + 0x100)
//-----------------------------TRACE打点相关空间-----------------------------------------------------------------
#define TRACE_RECEIVER_ADDR                             (0x88700000)
#define TRACE_RECV_INIT_ADDR                            (TRACE_RECEIVER_ADDR) //0x88700000
#define TRACE_SLOTIND_ADDR                              (TRACE_RECV_INIT_ADDR + TRACE_GRP_LEN) //0x88700200
#define TRACE_RECEIVER_SYNC_ADDR                        (TRACE_SLOTIND_ADDR + TRACE_GRP_LEN) // 0x88700400

#ifdef CORE_ODD
#define TRACE_RECEIVER_SYMB_ADDR                        (TRACE_RECEIVER_SYNC_ADDR + TRACE_GRP_LEN)// 0x88700600
#else
#define TRACE_RECEIVER_SYMB_ADDR                        (TRACE_RECEIVER_SYNC_ADDR + 2*TRACE_GRP_LEN)// 0x88700800
#endif

#define TRACE_RECEIVER_BIT_ADDR                         (TRACE_RECEIVER_SYNC_ADDR + 3*TRACE_GRP_LEN)// 0x88700a00
#define TRACE_TESTTASK_ADDR                             (TRACE_RECEIVER_BIT_ADDR + TRACE_GRP_LEN) // 0x88700c00
#define TRACE_RECEIVER_SYNC_FIRST_ADDR                  (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700e00   
#define TRACE_RECEIVER_SYNC_FINE_ADDR                   (TRACE_RECEIVER_SYNC_FIRST_ADDR + TRACE_GRP_LEN) // 0x88701000
#define TRACE_PCIE_ADDR                                 (TRACE_RECEIVER_SYNC_FINE_ADDR + TRACE_GRP_LEN) //0x88701200

#define TRACE_TRANSMITTER_ADDR                          (TRACE_PCIE_ADDR + TRACE_GRP_LEN)  // 0x88701400
#define TRACE_TRANS_INIT_ADDR                           (TRACE_TRANSMITTER_ADDR + TRACE_GRP_LEN)  // 0x88701600
#define TRACE_RECEIVER_SYNC_INIT_ADDR                   (TRACE_TRANS_INIT_ADDR + TRACE_GRP_LEN) // 0x88701800

#endif