1297 lines
106 KiB
C
1297 lines
106 KiB
C
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//******************** (C) COPYRIGHT 2020 SmartLogic*******************************
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// FileName : cpri.h
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// Author : lijian, jian.li@smartlogictech.com
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// Date First Issued : 2022-05-11 04:47:13 PM
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// Last Modified : 2022-05-25 08:19:15 AM
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// Author : xiakang, kang.xia@smartlogictech.com
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// Date First Issued : 2022-05-24 08:34:07 PM
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// Last Modified : 2022-05-25 08:19:15 AM
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef __UCP_CPRI_H__
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#define __UCP_CPRI_H__
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#define CPRI_GMAC_BASE 0x08524000
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#define CPRI_AUX_BASE 0x08544000
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//#define CPRI_TIME_BASE CPRI_AUX_BASE + 0x0C000
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#define CPRI_CPU_BASE 0x08564000
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#define CPRI_STC_BASE 0x08568000
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#define PCS_STATUS_1 0x4
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#define PCS_DEV_ID1 0x8
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#define PCS_DEV_ID2 0xC
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#define PCS_SPEED_ABLT 0x10
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#define PCS_DEV_PKG1 0x14
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#define PCS_DEV_PKG2 0x18
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#define PCS_CONTROL_2 0x1C
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#define PCS_STATUS_2 0x20
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#define PCS_STATUS_3 0x24
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#define PCS_PKG_ID1 0x38
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#define PCS_PKG_ID2 0x3C
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#define PCS_EEE_CC1 0x50
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#define PCS_EEE_CC2 0x54
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#define PCS_EEE_WEC 0x58
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#define PCS_MLTBASER_STATUS1 0x80
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#define PCS_MLTBASER_STATUS4 0x84
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#define PCS_SEED_A0 0x88
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#define PCS_SEED_A1 0x8C
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#define PCS_SEED_A2 0x90
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#define PCS_SEED_A3 0x94
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#define PCS_SEED_B0 0x98
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#define PCS_SEED_B1 0x9C
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#define PCS_SEED_B2 0xA0
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#define PCS_SEED_B3 0xA4
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#define PCS_TEST_CTRL 0xA8
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#define PCS_ERROR_CNT 0xAC
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#define GENERAL_TX 0xB8
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#define GENERAL_RX 0xBC
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#define CFG_TX 0xC0
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#define CFG_RX 0xC4
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#define BUF_STAT_TX 0xC8
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#define BUF_STAT_RX 0xCC
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#define DELAY_RX 0xD0
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#define DISP_ERRORS 0xD4
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#define CODE_ERRORS 0xD8
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#define CPCS_SHCV 0xDC
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#define ANEG_CTRL 0xE8
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#define ANEG_ADV 0xEC
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#define ANEG_NP 0xF0
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#define ANEG_LP_ADV 0xF4
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#define ANEG_LP_NP 0xF8
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#define BER_TIMER_END 0xFC
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#define SH_DELAY_TX 0x100
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#define SH_DELAY_RX 0x104
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#define SH_GB_POS_TX 0x108
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#define SH_GB_POS_RX 0x10C
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#define SCCFEC_ABILITY 0x2A8
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#define SCCFEC_CTRL 0x2AC
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#define SCCFEC_COR_BLKS1 0x2B0
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#define SCCFEC_COR_BLKS2 0x2B4
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#define SCCFEC_UNCOR_BLKS1 0x2B8
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#define SCCFEC_UNCOR_BLKS2 0x2BC
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#define SCCFEC_ERR_CNT1 0x2C0
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#define SCCFEC_ERR_CNT2 0x2C4
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#define RSFEC_CTRL 0x320
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#define RSFEC_STATUS 0x324
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#define RSFEC_COR_CW1 0x328
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#define RSFEC_COR_CW2 0x32C
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#define RSFEC_UNCOR_CW11 0x330
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#define RSFEC_UNCOR_CW22 0x334
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#define RSFEC_SYM_ERR1 0x348
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#define RSFEC_SYM_ERR2 0x34C
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#define CPRI_IP_VERSION (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x0)))
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#define CPRI_IP_DELAY_RX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4)))
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#define CPRI_IP_DELAY_TX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8)))
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#define CPRI_PCS_64B66B_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x40)))
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#define CPRI_PCS_CTRL_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x44)))
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#define CPRI_PCS_ADDR_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x48)))
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#define CPRI_PCS_DATA_TX_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4C)))
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#define CPRI_PCS_DATA_RX_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x50)))
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#define CPRI_ADJ_OFFSET_RX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x60)))
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#define CPRI_ADJ_OFFSET_TX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x64)))
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#define CPRI_FRAME_RX_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x70)))
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#define CPRI_FRAME_RX_STATE_SYNC_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x74)))
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#define CPRI_FRAMES_RX_FRAME_FILTER_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x78)))
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#define CPRI_FRAME_RX_CM_FILTER_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7C)))
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#define CPRI_FRAME_RX_LCV_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x80)))
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#define CPRI_FRAME_RX_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x90)))
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#define CPRI_FRAME_RX_HFN (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x94)))
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#define CPRI_FRAME_RX_BFN (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x98)))
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#define CPRI_FRAME_RX_SCRAMBLER (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9C)))
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#define CPRI_FRAME_RX_PROT_VER (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA0)))
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#define CPRI_FRAME_RX_RESET_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA4)))
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#define CPRI_FRAME_RX_CM_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA8)))
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#define CPRI_FRAME_RX_LCV_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAC)))
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#define CPRI_FRAME_RX_L1_STAT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB0)))
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#define CPRI_FRAME_RX_HDR_ADDR (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC0)))
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#define CPRI_FRAME_RX_HDR_DATA (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC4)))
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#define CPRI_FRAME_TX_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD0)))
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#define CPRI_FRAME_TX_L1_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD8)))
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#define CPRI_FRAME_TX_OFFSET (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDC)))
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#define CPRI_FRAME_TX_CM_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE0)))
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#define CPRI_FRAME_TX_SCRAMBLER (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE4)))
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#define CPRI_FRAME_TX_PROT_VER (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE8)))
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#define CPRI_FRAME_TX_BFN_INIT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF0)))
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#define CPRI_FRAME_TX_BFN (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF4)))
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#define CPRI_FRAME_TX_HFN (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF8)))
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#define CPRI_FRAME_TX_ETH_STATUS (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFC)))
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#define CPRI_FRAME_TX_RNDTRIP_DEL (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x100)))
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#define CPRI_FRAME_TX_HDR_ADDR (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x110)))
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#define CPRI_FRAME_TX_HDR_DATA (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x114)))
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#define CPRI_GMII_RX_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x120)))
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#define CPRI_GMII_TX_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x124)))
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#define CPRI_GMII_RX_CNT_RX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x128)))
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#define CPRI_GMII_RX_CNT_TX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12C)))
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#define CPRI_GMII_RX_CNT_OVFL (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x130)))
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#define CPRI_GMII_RX_CNT_ABORT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x134)))
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#define CPRI_GMII_TX_CNT_RX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x138)))
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#define CPRI_GMII_TX_CNT_TX (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13C)))
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#define CPRI_GMII_TX_CNT_OVFL (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x140)))
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#define CPRI_GMII_TX_CNT_ABORT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x144)))
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#define CPRI_MAP_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x180)))
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#define CPRI_MAP_TOGGLE (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x184)))
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#define CPRI_MAP_TX_AXC_ALARMS_H (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x190)))
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#define CPRI_MAP_TX_AXC_ALARMS_L (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x194)))
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#define CPRI_MAP_AXC_GEN_CHK_CFG (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1A0)))
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#define CPRI_MAP_AXC_CHK_MATCHED_CNT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1A4)))
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#define CPRI_MAP_AXC_CHK_UNMATCHED_CNT (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1A8)))
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//CPRI_MAP_RX_CFG
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#define CPRI_MAP_RX_CFG_0 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x400)))
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#define CPRI_MAP_RX_CFG_1 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x404)))
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#define CPRI_MAP_RX_CFG_2 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x408)))
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#define CPRI_MAP_RX_CFG_3 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x40C)))
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#define CPRI_MAP_RX_CFG_4 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x410)))
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#define CPRI_MAP_RX_CFG_5 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x414)))
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#define CPRI_MAP_RX_CFG_6 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x418)))
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#define CPRI_MAP_RX_CFG_7 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x41C)))
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#define CPRI_MAP_RX_CFG_8 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x420)))
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#define CPRI_MAP_RX_CFG_9 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x424)))
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#define CPRI_MAP_RX_CFG_10 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x428)))
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#define CPRI_MAP_RX_CFG_11 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x42C)))
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#define CPRI_MAP_RX_CFG_12 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x430)))
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#define CPRI_MAP_RX_CFG_13 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x434)))
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#define CPRI_MAP_RX_CFG_14 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x438)))
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#define CPRI_MAP_RX_CFG_15 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x43C)))
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#define CPRI_MAP_RX_CFG_16 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x440)))
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#define CPRI_MAP_RX_CFG_17 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x444)))
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#define CPRI_MAP_RX_CFG_18 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x448)))
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#define CPRI_MAP_RX_CFG_19 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x44C)))
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#define CPRI_MAP_RX_CFG_20 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x450)))
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#define CPRI_MAP_RX_CFG_21 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x454)))
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#define CPRI_MAP_RX_CFG_22 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x458)))
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#define CPRI_MAP_RX_CFG_23 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x45C)))
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#define CPRI_MAP_RX_CFG_24 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x460)))
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#define CPRI_MAP_RX_CFG_25 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x464)))
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#define CPRI_MAP_RX_CFG_26 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x468)))
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#define CPRI_MAP_RX_CFG_27 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x46C)))
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#define CPRI_MAP_RX_CFG_28 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x470)))
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#define CPRI_MAP_RX_CFG_29 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x474)))
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#define CPRI_MAP_RX_CFG_30 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x478)))
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#define CPRI_MAP_RX_CFG_31 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x47C)))
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#define CPRI_MAP_RX_CFG_32 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x480)))
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#define CPRI_MAP_RX_CFG_33 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x484)))
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#define CPRI_MAP_RX_CFG_34 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x488)))
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#define CPRI_MAP_RX_CFG_35 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x48C)))
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#define CPRI_MAP_RX_CFG_36 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x490)))
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#define CPRI_MAP_RX_CFG_37 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x494)))
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#define CPRI_MAP_RX_CFG_38 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x498)))
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#define CPRI_MAP_RX_CFG_39 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x49C)))
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#define CPRI_MAP_RX_CFG_40 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4A0)))
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#define CPRI_MAP_RX_CFG_41 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4A4)))
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#define CPRI_MAP_RX_CFG_42 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4A8)))
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#define CPRI_MAP_RX_CFG_43 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4AC)))
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#define CPRI_MAP_RX_CFG_44 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4B0)))
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#define CPRI_MAP_RX_CFG_45 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4B4)))
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#define CPRI_MAP_RX_CFG_46 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4B8)))
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#define CPRI_MAP_RX_CFG_47 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4BC)))
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#define CPRI_MAP_RX_CFG_48 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4C0)))
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#define CPRI_MAP_RX_CFG_49 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4C4)))
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#define CPRI_MAP_RX_CFG_50 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4C8)))
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#define CPRI_MAP_RX_CFG_51 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4CC)))
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#define CPRI_MAP_RX_CFG_52 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4D0)))
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#define CPRI_MAP_RX_CFG_53 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4D4)))
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#define CPRI_MAP_RX_CFG_54 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4D8)))
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#define CPRI_MAP_RX_CFG_55 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4DC)))
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#define CPRI_MAP_RX_CFG_56 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4E0)))
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#define CPRI_MAP_RX_CFG_57 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4E4)))
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#define CPRI_MAP_RX_CFG_58 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4E8)))
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#define CPRI_MAP_RX_CFG_59 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4EC)))
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#define CPRI_MAP_RX_CFG_60 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4F0)))
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#define CPRI_MAP_RX_CFG_61 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4F4)))
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#define CPRI_MAP_RX_CFG_62 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4F8)))
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#define CPRI_MAP_RX_CFG_63 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x4FC)))
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#define CPRI_MAP_RX_CFG_64 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x500)))
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#define CPRI_MAP_RX_CFG_65 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x504)))
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#define CPRI_MAP_RX_CFG_66 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x508)))
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#define CPRI_MAP_RX_CFG_67 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x50C)))
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|
|
#define CPRI_MAP_RX_CFG_68 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x510)))
|
||
|
|
#define CPRI_MAP_RX_CFG_69 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x514)))
|
||
|
|
#define CPRI_MAP_RX_CFG_70 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x518)))
|
||
|
|
#define CPRI_MAP_RX_CFG_71 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x51C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_72 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x520)))
|
||
|
|
#define CPRI_MAP_RX_CFG_73 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x524)))
|
||
|
|
#define CPRI_MAP_RX_CFG_74 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x528)))
|
||
|
|
#define CPRI_MAP_RX_CFG_75 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x52C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_76 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x530)))
|
||
|
|
#define CPRI_MAP_RX_CFG_77 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x534)))
|
||
|
|
#define CPRI_MAP_RX_CFG_78 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x538)))
|
||
|
|
#define CPRI_MAP_RX_CFG_79 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x53C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_80 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x540)))
|
||
|
|
#define CPRI_MAP_RX_CFG_81 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x544)))
|
||
|
|
#define CPRI_MAP_RX_CFG_82 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x548)))
|
||
|
|
#define CPRI_MAP_RX_CFG_83 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x54C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_84 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x550)))
|
||
|
|
#define CPRI_MAP_RX_CFG_85 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x554)))
|
||
|
|
#define CPRI_MAP_RX_CFG_86 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x558)))
|
||
|
|
#define CPRI_MAP_RX_CFG_87 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x55C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_88 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x560)))
|
||
|
|
#define CPRI_MAP_RX_CFG_89 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x564)))
|
||
|
|
#define CPRI_MAP_RX_CFG_90 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x568)))
|
||
|
|
#define CPRI_MAP_RX_CFG_91 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x56C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_92 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x570)))
|
||
|
|
#define CPRI_MAP_RX_CFG_93 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x574)))
|
||
|
|
#define CPRI_MAP_RX_CFG_94 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x578)))
|
||
|
|
#define CPRI_MAP_RX_CFG_95 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x57C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_96 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x580)))
|
||
|
|
#define CPRI_MAP_RX_CFG_97 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x584)))
|
||
|
|
#define CPRI_MAP_RX_CFG_98 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x588)))
|
||
|
|
#define CPRI_MAP_RX_CFG_99 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x58C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_100 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x590)))
|
||
|
|
#define CPRI_MAP_RX_CFG_101 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x594)))
|
||
|
|
#define CPRI_MAP_RX_CFG_102 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x598)))
|
||
|
|
#define CPRI_MAP_RX_CFG_103 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x59C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_104 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5A0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_105 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5A4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_106 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5A8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_107 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5AC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_108 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5B0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_109 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5B4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_110 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5B8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_111 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5BC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_112 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5C0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_113 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5C4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_114 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5C8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_115 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5CC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_116 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5D0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_117 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5D4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_118 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5D8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_119 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5DC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_120 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5E0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_121 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5E4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_122 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5E8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_123 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5EC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_124 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5F0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_125 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5F4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_126 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5F8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_127 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x5FC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_128 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x600)))
|
||
|
|
#define CPRI_MAP_RX_CFG_129 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x604)))
|
||
|
|
#define CPRI_MAP_RX_CFG_130 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x608)))
|
||
|
|
#define CPRI_MAP_RX_CFG_131 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x60C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_132 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x610)))
|
||
|
|
#define CPRI_MAP_RX_CFG_133 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x614)))
|
||
|
|
#define CPRI_MAP_RX_CFG_134 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x618)))
|
||
|
|
#define CPRI_MAP_RX_CFG_135 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x61C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_136 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x620)))
|
||
|
|
#define CPRI_MAP_RX_CFG_137 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x624)))
|
||
|
|
#define CPRI_MAP_RX_CFG_138 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x628)))
|
||
|
|
#define CPRI_MAP_RX_CFG_139 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x62C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_140 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x630)))
|
||
|
|
#define CPRI_MAP_RX_CFG_141 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x634)))
|
||
|
|
#define CPRI_MAP_RX_CFG_142 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x638)))
|
||
|
|
#define CPRI_MAP_RX_CFG_143 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x63C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_144 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x640)))
|
||
|
|
#define CPRI_MAP_RX_CFG_145 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x644)))
|
||
|
|
#define CPRI_MAP_RX_CFG_146 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x648)))
|
||
|
|
#define CPRI_MAP_RX_CFG_147 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x64C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_148 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x650)))
|
||
|
|
#define CPRI_MAP_RX_CFG_149 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x654)))
|
||
|
|
#define CPRI_MAP_RX_CFG_150 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x658)))
|
||
|
|
#define CPRI_MAP_RX_CFG_151 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x65C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_152 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x660)))
|
||
|
|
#define CPRI_MAP_RX_CFG_153 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x664)))
|
||
|
|
#define CPRI_MAP_RX_CFG_154 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x668)))
|
||
|
|
#define CPRI_MAP_RX_CFG_155 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x66C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_156 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x670)))
|
||
|
|
#define CPRI_MAP_RX_CFG_157 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x674)))
|
||
|
|
#define CPRI_MAP_RX_CFG_158 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x678)))
|
||
|
|
#define CPRI_MAP_RX_CFG_159 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x67C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_160 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x680)))
|
||
|
|
#define CPRI_MAP_RX_CFG_161 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x684)))
|
||
|
|
#define CPRI_MAP_RX_CFG_162 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x688)))
|
||
|
|
#define CPRI_MAP_RX_CFG_163 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x68C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_164 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x690)))
|
||
|
|
#define CPRI_MAP_RX_CFG_165 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x694)))
|
||
|
|
#define CPRI_MAP_RX_CFG_166 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x698)))
|
||
|
|
#define CPRI_MAP_RX_CFG_167 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x69C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_168 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6A0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_169 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6A4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_170 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6A8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_171 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6AC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_172 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6B0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_173 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6B4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_174 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6B8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_175 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6BC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_176 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6C0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_177 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6C4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_178 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6C8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_179 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6CC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_180 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6D0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_181 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6D4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_182 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6D8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_183 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6DC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_184 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6E0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_185 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6E4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_186 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6E8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_187 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6EC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_188 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6F0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_189 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6F4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_190 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6F8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_191 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x6FC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_192 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x700)))
|
||
|
|
#define CPRI_MAP_RX_CFG_193 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x704)))
|
||
|
|
#define CPRI_MAP_RX_CFG_194 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x708)))
|
||
|
|
#define CPRI_MAP_RX_CFG_195 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x70C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_196 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x710)))
|
||
|
|
#define CPRI_MAP_RX_CFG_197 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x714)))
|
||
|
|
#define CPRI_MAP_RX_CFG_198 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x718)))
|
||
|
|
#define CPRI_MAP_RX_CFG_199 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x71C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_200 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x720)))
|
||
|
|
#define CPRI_MAP_RX_CFG_201 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x724)))
|
||
|
|
#define CPRI_MAP_RX_CFG_202 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x728)))
|
||
|
|
#define CPRI_MAP_RX_CFG_203 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x72C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_204 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x730)))
|
||
|
|
#define CPRI_MAP_RX_CFG_205 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x734)))
|
||
|
|
#define CPRI_MAP_RX_CFG_206 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x738)))
|
||
|
|
#define CPRI_MAP_RX_CFG_207 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x73C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_208 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x740)))
|
||
|
|
#define CPRI_MAP_RX_CFG_209 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x744)))
|
||
|
|
#define CPRI_MAP_RX_CFG_210 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x748)))
|
||
|
|
#define CPRI_MAP_RX_CFG_211 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x74C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_212 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x750)))
|
||
|
|
#define CPRI_MAP_RX_CFG_213 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x754)))
|
||
|
|
#define CPRI_MAP_RX_CFG_214 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x758)))
|
||
|
|
#define CPRI_MAP_RX_CFG_215 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x75C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_216 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x760)))
|
||
|
|
#define CPRI_MAP_RX_CFG_217 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x764)))
|
||
|
|
#define CPRI_MAP_RX_CFG_218 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x768)))
|
||
|
|
#define CPRI_MAP_RX_CFG_219 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x76C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_220 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x770)))
|
||
|
|
#define CPRI_MAP_RX_CFG_221 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x774)))
|
||
|
|
#define CPRI_MAP_RX_CFG_222 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x778)))
|
||
|
|
#define CPRI_MAP_RX_CFG_223 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x77C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_224 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x780)))
|
||
|
|
#define CPRI_MAP_RX_CFG_225 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x784)))
|
||
|
|
#define CPRI_MAP_RX_CFG_226 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x788)))
|
||
|
|
#define CPRI_MAP_RX_CFG_227 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x78C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_228 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x790)))
|
||
|
|
#define CPRI_MAP_RX_CFG_229 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x794)))
|
||
|
|
#define CPRI_MAP_RX_CFG_230 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x798)))
|
||
|
|
#define CPRI_MAP_RX_CFG_231 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x79C)))
|
||
|
|
#define CPRI_MAP_RX_CFG_232 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7A0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_233 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7A4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_234 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7A8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_235 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7AC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_236 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7B0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_237 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7B4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_238 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7B8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_239 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7BC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_240 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7C0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_241 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7C4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_242 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7C8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_243 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7CC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_244 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7D0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_245 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7D4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_246 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7D8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_247 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7DC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_248 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7E0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_249 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7E4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_250 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7E8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_251 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7EC)))
|
||
|
|
#define CPRI_MAP_RX_CFG_252 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7F0)))
|
||
|
|
#define CPRI_MAP_RX_CFG_253 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7F4)))
|
||
|
|
#define CPRI_MAP_RX_CFG_254 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7F8)))
|
||
|
|
#define CPRI_MAP_RX_CFG_255 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x7FC)))
|
||
|
|
|
||
|
|
//CPRI_MAP_TX_CFG
|
||
|
|
#define CPRI_MAP_TX_CFG_0 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x800)))
|
||
|
|
#define CPRI_MAP_TX_CFG_1 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x804)))
|
||
|
|
#define CPRI_MAP_TX_CFG_2 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x808)))
|
||
|
|
#define CPRI_MAP_TX_CFG_3 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x80C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_4 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x810)))
|
||
|
|
#define CPRI_MAP_TX_CFG_5 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x814)))
|
||
|
|
#define CPRI_MAP_TX_CFG_6 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x818)))
|
||
|
|
#define CPRI_MAP_TX_CFG_7 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x81C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_8 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x820)))
|
||
|
|
#define CPRI_MAP_TX_CFG_9 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x824)))
|
||
|
|
#define CPRI_MAP_TX_CFG_10 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x828)))
|
||
|
|
#define CPRI_MAP_TX_CFG_11 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x82C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_12 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x830)))
|
||
|
|
#define CPRI_MAP_TX_CFG_13 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x834)))
|
||
|
|
#define CPRI_MAP_TX_CFG_14 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x838)))
|
||
|
|
#define CPRI_MAP_TX_CFG_15 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x83C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_16 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x840)))
|
||
|
|
#define CPRI_MAP_TX_CFG_17 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x844)))
|
||
|
|
#define CPRI_MAP_TX_CFG_18 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x848)))
|
||
|
|
#define CPRI_MAP_TX_CFG_19 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x84C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_20 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x850)))
|
||
|
|
#define CPRI_MAP_TX_CFG_21 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x854)))
|
||
|
|
#define CPRI_MAP_TX_CFG_22 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x858)))
|
||
|
|
#define CPRI_MAP_TX_CFG_23 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x85C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_24 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x860)))
|
||
|
|
#define CPRI_MAP_TX_CFG_25 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x864)))
|
||
|
|
#define CPRI_MAP_TX_CFG_26 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x868)))
|
||
|
|
#define CPRI_MAP_TX_CFG_27 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x86C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_28 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x870)))
|
||
|
|
#define CPRI_MAP_TX_CFG_29 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x874)))
|
||
|
|
#define CPRI_MAP_TX_CFG_30 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x878)))
|
||
|
|
#define CPRI_MAP_TX_CFG_31 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x87C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_32 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x880)))
|
||
|
|
#define CPRI_MAP_TX_CFG_33 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x884)))
|
||
|
|
#define CPRI_MAP_TX_CFG_34 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x888)))
|
||
|
|
#define CPRI_MAP_TX_CFG_35 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x88C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_36 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x890)))
|
||
|
|
#define CPRI_MAP_TX_CFG_37 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x894)))
|
||
|
|
#define CPRI_MAP_TX_CFG_38 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x898)))
|
||
|
|
#define CPRI_MAP_TX_CFG_39 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x89C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_40 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8A0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_41 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8A4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_42 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8A8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_43 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8AC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_44 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8B0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_45 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8B4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_46 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8B8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_47 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8BC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_48 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8C0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_49 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8C4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_50 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8C8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_51 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8CC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_52 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8D0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_53 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8D4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_54 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8D8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_55 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8DC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_56 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8E0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_57 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8E4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_58 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8E8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_59 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8EC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_60 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8F0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_61 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8F4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_62 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8F8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_63 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x8FC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_64 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x900)))
|
||
|
|
#define CPRI_MAP_TX_CFG_65 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x904)))
|
||
|
|
#define CPRI_MAP_TX_CFG_66 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x908)))
|
||
|
|
#define CPRI_MAP_TX_CFG_67 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x90C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_68 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x910)))
|
||
|
|
#define CPRI_MAP_TX_CFG_69 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x914)))
|
||
|
|
#define CPRI_MAP_TX_CFG_70 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x918)))
|
||
|
|
#define CPRI_MAP_TX_CFG_71 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x91C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_72 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x920)))
|
||
|
|
#define CPRI_MAP_TX_CFG_73 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x924)))
|
||
|
|
#define CPRI_MAP_TX_CFG_74 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x928)))
|
||
|
|
#define CPRI_MAP_TX_CFG_75 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x92C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_76 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x930)))
|
||
|
|
#define CPRI_MAP_TX_CFG_77 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x934)))
|
||
|
|
#define CPRI_MAP_TX_CFG_78 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x938)))
|
||
|
|
#define CPRI_MAP_TX_CFG_79 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x93C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_80 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x940)))
|
||
|
|
#define CPRI_MAP_TX_CFG_81 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x944)))
|
||
|
|
#define CPRI_MAP_TX_CFG_82 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x948)))
|
||
|
|
#define CPRI_MAP_TX_CFG_83 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x94C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_84 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x950)))
|
||
|
|
#define CPRI_MAP_TX_CFG_85 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x954)))
|
||
|
|
#define CPRI_MAP_TX_CFG_86 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x958)))
|
||
|
|
#define CPRI_MAP_TX_CFG_87 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x95C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_88 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x960)))
|
||
|
|
#define CPRI_MAP_TX_CFG_89 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x964)))
|
||
|
|
#define CPRI_MAP_TX_CFG_90 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x968)))
|
||
|
|
#define CPRI_MAP_TX_CFG_91 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x96C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_92 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x970)))
|
||
|
|
#define CPRI_MAP_TX_CFG_93 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x974)))
|
||
|
|
#define CPRI_MAP_TX_CFG_94 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x978)))
|
||
|
|
#define CPRI_MAP_TX_CFG_95 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x97C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_96 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x980)))
|
||
|
|
#define CPRI_MAP_TX_CFG_97 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x984)))
|
||
|
|
#define CPRI_MAP_TX_CFG_98 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x988)))
|
||
|
|
#define CPRI_MAP_TX_CFG_99 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x98C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_100 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x990)))
|
||
|
|
#define CPRI_MAP_TX_CFG_101 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x994)))
|
||
|
|
#define CPRI_MAP_TX_CFG_102 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x998)))
|
||
|
|
#define CPRI_MAP_TX_CFG_103 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x99C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_104 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9A0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_105 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9A4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_106 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9A8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_107 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9AC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_108 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9B0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_109 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9B4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_110 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9B8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_111 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9BC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_112 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9C0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_113 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9C4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_114 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9C8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_115 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9CC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_116 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9D0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_117 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9D4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_118 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9D8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_119 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9DC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_120 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9E0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_121 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9E4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_122 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9E8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_123 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9EC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_124 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9F0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_125 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9F4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_126 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9F8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_127 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x9FC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_128 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA00)))
|
||
|
|
#define CPRI_MAP_TX_CFG_129 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA04)))
|
||
|
|
#define CPRI_MAP_TX_CFG_130 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA08)))
|
||
|
|
#define CPRI_MAP_TX_CFG_131 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA0C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_132 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA10)))
|
||
|
|
#define CPRI_MAP_TX_CFG_133 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA14)))
|
||
|
|
#define CPRI_MAP_TX_CFG_134 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA18)))
|
||
|
|
#define CPRI_MAP_TX_CFG_135 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA1C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_136 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA20)))
|
||
|
|
#define CPRI_MAP_TX_CFG_137 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA24)))
|
||
|
|
#define CPRI_MAP_TX_CFG_138 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA28)))
|
||
|
|
#define CPRI_MAP_TX_CFG_139 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA2C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_140 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA30)))
|
||
|
|
#define CPRI_MAP_TX_CFG_141 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA34)))
|
||
|
|
#define CPRI_MAP_TX_CFG_142 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA38)))
|
||
|
|
#define CPRI_MAP_TX_CFG_143 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA3C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_144 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA40)))
|
||
|
|
#define CPRI_MAP_TX_CFG_145 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA44)))
|
||
|
|
#define CPRI_MAP_TX_CFG_146 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA48)))
|
||
|
|
#define CPRI_MAP_TX_CFG_147 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA4C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_148 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA50)))
|
||
|
|
#define CPRI_MAP_TX_CFG_149 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA54)))
|
||
|
|
#define CPRI_MAP_TX_CFG_150 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA58)))
|
||
|
|
#define CPRI_MAP_TX_CFG_151 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA5C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_152 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA60)))
|
||
|
|
#define CPRI_MAP_TX_CFG_153 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA64)))
|
||
|
|
#define CPRI_MAP_TX_CFG_154 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA68)))
|
||
|
|
#define CPRI_MAP_TX_CFG_155 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA6C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_156 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA70)))
|
||
|
|
#define CPRI_MAP_TX_CFG_157 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA74)))
|
||
|
|
#define CPRI_MAP_TX_CFG_158 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA78)))
|
||
|
|
#define CPRI_MAP_TX_CFG_159 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA7C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_160 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA80)))
|
||
|
|
#define CPRI_MAP_TX_CFG_161 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA84)))
|
||
|
|
#define CPRI_MAP_TX_CFG_162 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA88)))
|
||
|
|
#define CPRI_MAP_TX_CFG_163 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA8C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_164 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA90)))
|
||
|
|
#define CPRI_MAP_TX_CFG_165 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA94)))
|
||
|
|
#define CPRI_MAP_TX_CFG_166 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA98)))
|
||
|
|
#define CPRI_MAP_TX_CFG_167 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xA9C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_168 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAA0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_169 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAA4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_170 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAA8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_171 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAAC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_172 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAB0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_173 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAB4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_174 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAB8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_175 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xABC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_176 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAC0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_177 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAC4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_178 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAC8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_179 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xACC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_180 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAD0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_181 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAD4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_182 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAD8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_183 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xADC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_184 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAE0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_185 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAE4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_186 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAE8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_187 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAEC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_188 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAF0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_189 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAF4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_190 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAF8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_191 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xAFC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_192 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB00)))
|
||
|
|
#define CPRI_MAP_TX_CFG_193 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB04)))
|
||
|
|
#define CPRI_MAP_TX_CFG_194 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB08)))
|
||
|
|
#define CPRI_MAP_TX_CFG_195 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB0C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_196 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB10)))
|
||
|
|
#define CPRI_MAP_TX_CFG_197 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB14)))
|
||
|
|
#define CPRI_MAP_TX_CFG_198 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB18)))
|
||
|
|
#define CPRI_MAP_TX_CFG_199 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB1C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_200 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB20)))
|
||
|
|
#define CPRI_MAP_TX_CFG_201 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB24)))
|
||
|
|
#define CPRI_MAP_TX_CFG_202 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB28)))
|
||
|
|
#define CPRI_MAP_TX_CFG_203 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB2C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_204 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB30)))
|
||
|
|
#define CPRI_MAP_TX_CFG_205 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB34)))
|
||
|
|
#define CPRI_MAP_TX_CFG_206 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB38)))
|
||
|
|
#define CPRI_MAP_TX_CFG_207 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB3C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_208 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB40)))
|
||
|
|
#define CPRI_MAP_TX_CFG_209 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB44)))
|
||
|
|
#define CPRI_MAP_TX_CFG_210 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB48)))
|
||
|
|
#define CPRI_MAP_TX_CFG_211 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB4C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_212 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB50)))
|
||
|
|
#define CPRI_MAP_TX_CFG_213 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB54)))
|
||
|
|
#define CPRI_MAP_TX_CFG_214 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB58)))
|
||
|
|
#define CPRI_MAP_TX_CFG_215 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB5C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_216 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB60)))
|
||
|
|
#define CPRI_MAP_TX_CFG_217 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB64)))
|
||
|
|
#define CPRI_MAP_TX_CFG_218 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB68)))
|
||
|
|
#define CPRI_MAP_TX_CFG_219 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB6C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_220 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB70)))
|
||
|
|
#define CPRI_MAP_TX_CFG_221 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB74)))
|
||
|
|
#define CPRI_MAP_TX_CFG_222 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB78)))
|
||
|
|
#define CPRI_MAP_TX_CFG_223 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB7C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_224 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB80)))
|
||
|
|
#define CPRI_MAP_TX_CFG_225 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB84)))
|
||
|
|
#define CPRI_MAP_TX_CFG_226 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB88)))
|
||
|
|
#define CPRI_MAP_TX_CFG_227 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB8C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_228 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB90)))
|
||
|
|
#define CPRI_MAP_TX_CFG_229 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB94)))
|
||
|
|
#define CPRI_MAP_TX_CFG_230 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB98)))
|
||
|
|
#define CPRI_MAP_TX_CFG_231 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xB9C)))
|
||
|
|
#define CPRI_MAP_TX_CFG_232 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBA0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_233 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBA4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_234 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBA8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_235 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBAC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_236 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBB0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_237 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBB4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_238 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBB8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_239 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBBC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_240 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBC0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_241 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBC4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_242 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBC8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_243 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBCC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_244 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBD0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_245 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBD4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_246 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBD8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_247 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBDC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_248 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBE0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_249 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBE4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_250 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBE8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_251 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBEC)))
|
||
|
|
#define CPRI_MAP_TX_CFG_252 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBF0)))
|
||
|
|
#define CPRI_MAP_TX_CFG_253 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBF4)))
|
||
|
|
#define CPRI_MAP_TX_CFG_254 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBF8)))
|
||
|
|
#define CPRI_MAP_TX_CFG_255 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xBFC)))
|
||
|
|
|
||
|
|
//CPRI_ACX_RX_CFG
|
||
|
|
#define CPRI_AXC_RX_CFG_0 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC00)))
|
||
|
|
#define CPRI_AXC_RX_CFG_1 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC04)))
|
||
|
|
#define CPRI_AXC_RX_CFG_2 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC08)))
|
||
|
|
#define CPRI_AXC_RX_CFG_3 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC0C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_4 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC10)))
|
||
|
|
#define CPRI_AXC_RX_CFG_5 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC14)))
|
||
|
|
#define CPRI_AXC_RX_CFG_6 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC18)))
|
||
|
|
#define CPRI_AXC_RX_CFG_7 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC1C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_8 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC20)))
|
||
|
|
#define CPRI_AXC_RX_CFG_9 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC24)))
|
||
|
|
#define CPRI_AXC_RX_CFG_10 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC28)))
|
||
|
|
#define CPRI_AXC_RX_CFG_11 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC2C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_12 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC30)))
|
||
|
|
#define CPRI_AXC_RX_CFG_13 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC34)))
|
||
|
|
#define CPRI_AXC_RX_CFG_14 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC38)))
|
||
|
|
#define CPRI_AXC_RX_CFG_15 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC3C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_16 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC40)))
|
||
|
|
#define CPRI_AXC_RX_CFG_17 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC44)))
|
||
|
|
#define CPRI_AXC_RX_CFG_18 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC48)))
|
||
|
|
#define CPRI_AXC_RX_CFG_19 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC4C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_20 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC50)))
|
||
|
|
#define CPRI_AXC_RX_CFG_21 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC54)))
|
||
|
|
#define CPRI_AXC_RX_CFG_22 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC58)))
|
||
|
|
#define CPRI_AXC_RX_CFG_23 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC5C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_24 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC60)))
|
||
|
|
#define CPRI_AXC_RX_CFG_25 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC64)))
|
||
|
|
#define CPRI_AXC_RX_CFG_26 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC68)))
|
||
|
|
#define CPRI_AXC_RX_CFG_27 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC6C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_28 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC70)))
|
||
|
|
#define CPRI_AXC_RX_CFG_29 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC74)))
|
||
|
|
#define CPRI_AXC_RX_CFG_30 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC78)))
|
||
|
|
#define CPRI_AXC_RX_CFG_31 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC7C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_32 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC80)))
|
||
|
|
#define CPRI_AXC_RX_CFG_33 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC84)))
|
||
|
|
#define CPRI_AXC_RX_CFG_34 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC88)))
|
||
|
|
#define CPRI_AXC_RX_CFG_35 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC8C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_36 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC90)))
|
||
|
|
#define CPRI_AXC_RX_CFG_37 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC94)))
|
||
|
|
#define CPRI_AXC_RX_CFG_38 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC98)))
|
||
|
|
#define CPRI_AXC_RX_CFG_39 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xC9C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_40 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCA0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_41 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCA4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_42 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCA8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_43 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCAC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_44 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCB0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_45 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCB4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_46 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCB8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_47 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCBC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_48 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCC0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_49 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCC4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_50 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCC8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_51 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCCC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_52 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCD0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_53 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCD4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_54 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCD8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_55 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCDC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_56 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCE0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_57 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCE4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_58 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCE8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_59 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCEC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_60 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCF0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_61 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCF4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_62 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCF8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_63 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xCFC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_64 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD00)))
|
||
|
|
#define CPRI_AXC_RX_CFG_65 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD04)))
|
||
|
|
#define CPRI_AXC_RX_CFG_66 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD08)))
|
||
|
|
#define CPRI_AXC_RX_CFG_67 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD0C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_68 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD10)))
|
||
|
|
#define CPRI_AXC_RX_CFG_69 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD14)))
|
||
|
|
#define CPRI_AXC_RX_CFG_70 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD18)))
|
||
|
|
#define CPRI_AXC_RX_CFG_71 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD1C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_72 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD20)))
|
||
|
|
#define CPRI_AXC_RX_CFG_73 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD24)))
|
||
|
|
#define CPRI_AXC_RX_CFG_74 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD28)))
|
||
|
|
#define CPRI_AXC_RX_CFG_75 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD2C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_76 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD30)))
|
||
|
|
#define CPRI_AXC_RX_CFG_77 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD34)))
|
||
|
|
#define CPRI_AXC_RX_CFG_78 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD38)))
|
||
|
|
#define CPRI_AXC_RX_CFG_79 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD3C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_80 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD40)))
|
||
|
|
#define CPRI_AXC_RX_CFG_81 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD44)))
|
||
|
|
#define CPRI_AXC_RX_CFG_82 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD48)))
|
||
|
|
#define CPRI_AXC_RX_CFG_83 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD4C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_84 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD50)))
|
||
|
|
#define CPRI_AXC_RX_CFG_85 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD54)))
|
||
|
|
#define CPRI_AXC_RX_CFG_86 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD58)))
|
||
|
|
#define CPRI_AXC_RX_CFG_87 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD5C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_88 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD60)))
|
||
|
|
#define CPRI_AXC_RX_CFG_89 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD64)))
|
||
|
|
#define CPRI_AXC_RX_CFG_90 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD68)))
|
||
|
|
#define CPRI_AXC_RX_CFG_91 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD6C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_92 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD70)))
|
||
|
|
#define CPRI_AXC_RX_CFG_93 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD74)))
|
||
|
|
#define CPRI_AXC_RX_CFG_94 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD78)))
|
||
|
|
#define CPRI_AXC_RX_CFG_95 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD7C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_96 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD80)))
|
||
|
|
#define CPRI_AXC_RX_CFG_97 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD84)))
|
||
|
|
#define CPRI_AXC_RX_CFG_98 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD88)))
|
||
|
|
#define CPRI_AXC_RX_CFG_99 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD8C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_100 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD90)))
|
||
|
|
#define CPRI_AXC_RX_CFG_101 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD94)))
|
||
|
|
#define CPRI_AXC_RX_CFG_102 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD98)))
|
||
|
|
#define CPRI_AXC_RX_CFG_103 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xD9C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_104 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDA0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_105 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDA4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_106 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDA8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_107 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDAC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_108 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDB0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_109 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDB4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_110 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDB8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_111 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDBC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_112 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDC0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_113 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDC4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_114 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDC8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_115 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDCC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_116 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDD0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_117 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDD4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_118 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDD8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_119 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDDC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_120 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDE0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_121 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDE4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_122 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDE8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_123 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDEC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_124 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDF0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_125 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDF4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_126 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDF8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_127 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xDFC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_128 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE00)))
|
||
|
|
#define CPRI_AXC_RX_CFG_129 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE04)))
|
||
|
|
#define CPRI_AXC_RX_CFG_130 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE08)))
|
||
|
|
#define CPRI_AXC_RX_CFG_131 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE0C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_132 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE10)))
|
||
|
|
#define CPRI_AXC_RX_CFG_133 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE14)))
|
||
|
|
#define CPRI_AXC_RX_CFG_134 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE18)))
|
||
|
|
#define CPRI_AXC_RX_CFG_135 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE1C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_136 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE20)))
|
||
|
|
#define CPRI_AXC_RX_CFG_137 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE24)))
|
||
|
|
#define CPRI_AXC_RX_CFG_138 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE28)))
|
||
|
|
#define CPRI_AXC_RX_CFG_139 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE2C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_140 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE30)))
|
||
|
|
#define CPRI_AXC_RX_CFG_141 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE34)))
|
||
|
|
#define CPRI_AXC_RX_CFG_142 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE38)))
|
||
|
|
#define CPRI_AXC_RX_CFG_143 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE3C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_144 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE40)))
|
||
|
|
#define CPRI_AXC_RX_CFG_145 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE44)))
|
||
|
|
#define CPRI_AXC_RX_CFG_146 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE48)))
|
||
|
|
#define CPRI_AXC_RX_CFG_147 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE4C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_148 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE50)))
|
||
|
|
#define CPRI_AXC_RX_CFG_149 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE54)))
|
||
|
|
#define CPRI_AXC_RX_CFG_150 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE58)))
|
||
|
|
#define CPRI_AXC_RX_CFG_151 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE5C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_152 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE60)))
|
||
|
|
#define CPRI_AXC_RX_CFG_153 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE64)))
|
||
|
|
#define CPRI_AXC_RX_CFG_154 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE68)))
|
||
|
|
#define CPRI_AXC_RX_CFG_155 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE6C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_156 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE70)))
|
||
|
|
#define CPRI_AXC_RX_CFG_157 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE74)))
|
||
|
|
#define CPRI_AXC_RX_CFG_158 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE78)))
|
||
|
|
#define CPRI_AXC_RX_CFG_159 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE7C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_160 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE80)))
|
||
|
|
#define CPRI_AXC_RX_CFG_161 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE84)))
|
||
|
|
#define CPRI_AXC_RX_CFG_162 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE88)))
|
||
|
|
#define CPRI_AXC_RX_CFG_163 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE8C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_164 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE90)))
|
||
|
|
#define CPRI_AXC_RX_CFG_165 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE94)))
|
||
|
|
#define CPRI_AXC_RX_CFG_166 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE98)))
|
||
|
|
#define CPRI_AXC_RX_CFG_167 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xE9C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_168 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEA0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_169 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEA4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_170 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEA8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_171 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEAC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_172 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEB0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_173 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEB4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_174 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEB8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_175 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEBC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_176 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEC0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_177 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEC4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_178 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEC8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_179 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xECC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_180 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xED0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_181 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xED4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_182 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xED8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_183 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEDC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_184 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEE0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_185 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEE4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_186 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEE8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_187 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEEC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_188 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEF0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_189 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEF4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_190 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEF8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_191 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xEFC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_192 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF00)))
|
||
|
|
#define CPRI_AXC_RX_CFG_193 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF04)))
|
||
|
|
#define CPRI_AXC_RX_CFG_194 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF08)))
|
||
|
|
#define CPRI_AXC_RX_CFG_195 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF0C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_196 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF10)))
|
||
|
|
#define CPRI_AXC_RX_CFG_197 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF14)))
|
||
|
|
#define CPRI_AXC_RX_CFG_198 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF18)))
|
||
|
|
#define CPRI_AXC_RX_CFG_199 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF1C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_200 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF20)))
|
||
|
|
#define CPRI_AXC_RX_CFG_201 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF24)))
|
||
|
|
#define CPRI_AXC_RX_CFG_202 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF28)))
|
||
|
|
#define CPRI_AXC_RX_CFG_203 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF2C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_204 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF30)))
|
||
|
|
#define CPRI_AXC_RX_CFG_205 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF34)))
|
||
|
|
#define CPRI_AXC_RX_CFG_206 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF38)))
|
||
|
|
#define CPRI_AXC_RX_CFG_207 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF3C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_208 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF40)))
|
||
|
|
#define CPRI_AXC_RX_CFG_209 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF44)))
|
||
|
|
#define CPRI_AXC_RX_CFG_210 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF48)))
|
||
|
|
#define CPRI_AXC_RX_CFG_211 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF4C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_212 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF50)))
|
||
|
|
#define CPRI_AXC_RX_CFG_213 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF54)))
|
||
|
|
#define CPRI_AXC_RX_CFG_214 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF58)))
|
||
|
|
#define CPRI_AXC_RX_CFG_215 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF5C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_216 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF60)))
|
||
|
|
#define CPRI_AXC_RX_CFG_217 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF64)))
|
||
|
|
#define CPRI_AXC_RX_CFG_218 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF68)))
|
||
|
|
#define CPRI_AXC_RX_CFG_219 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF6C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_220 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF70)))
|
||
|
|
#define CPRI_AXC_RX_CFG_221 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF74)))
|
||
|
|
#define CPRI_AXC_RX_CFG_222 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF78)))
|
||
|
|
#define CPRI_AXC_RX_CFG_223 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF7C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_224 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF80)))
|
||
|
|
#define CPRI_AXC_RX_CFG_225 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF84)))
|
||
|
|
#define CPRI_AXC_RX_CFG_226 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF88)))
|
||
|
|
#define CPRI_AXC_RX_CFG_227 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF8C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_228 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF90)))
|
||
|
|
#define CPRI_AXC_RX_CFG_229 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF94)))
|
||
|
|
#define CPRI_AXC_RX_CFG_230 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF98)))
|
||
|
|
#define CPRI_AXC_RX_CFG_231 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xF9C)))
|
||
|
|
#define CPRI_AXC_RX_CFG_232 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFA0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_233 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFA4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_234 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFA8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_235 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFAC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_236 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFB0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_237 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFB4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_238 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFB8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_239 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFBC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_240 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFC0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_241 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFC4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_242 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFC8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_243 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFCC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_244 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFD0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_245 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFD4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_246 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFD8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_247 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFDC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_248 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFE0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_249 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFE4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_250 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFE8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_251 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFEC)))
|
||
|
|
#define CPRI_AXC_RX_CFG_252 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFF0)))
|
||
|
|
#define CPRI_AXC_RX_CFG_253 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFF4)))
|
||
|
|
#define CPRI_AXC_RX_CFG_254 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFF8)))
|
||
|
|
#define CPRI_AXC_RX_CFG_255 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0xFFC)))
|
||
|
|
|
||
|
|
//CPRI_ACX_TX_CFG
|
||
|
|
#define CPRI_AXC_TX_CFG_0 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1000)))
|
||
|
|
#define CPRI_AXC_TX_CFG_1 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1004)))
|
||
|
|
#define CPRI_AXC_TX_CFG_2 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1008)))
|
||
|
|
#define CPRI_AXC_TX_CFG_3 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x100C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_4 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1010)))
|
||
|
|
#define CPRI_AXC_TX_CFG_5 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1014)))
|
||
|
|
#define CPRI_AXC_TX_CFG_6 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1018)))
|
||
|
|
#define CPRI_AXC_TX_CFG_7 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x101C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_8 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1020)))
|
||
|
|
#define CPRI_AXC_TX_CFG_9 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1024)))
|
||
|
|
#define CPRI_AXC_TX_CFG_10 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1028)))
|
||
|
|
#define CPRI_AXC_TX_CFG_11 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x102C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_12 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1030)))
|
||
|
|
#define CPRI_AXC_TX_CFG_13 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1034)))
|
||
|
|
#define CPRI_AXC_TX_CFG_14 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1038)))
|
||
|
|
#define CPRI_AXC_TX_CFG_15 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x103C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_16 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1040)))
|
||
|
|
#define CPRI_AXC_TX_CFG_17 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1044)))
|
||
|
|
#define CPRI_AXC_TX_CFG_18 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1048)))
|
||
|
|
#define CPRI_AXC_TX_CFG_19 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x104C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_20 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1050)))
|
||
|
|
#define CPRI_AXC_TX_CFG_21 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1054)))
|
||
|
|
#define CPRI_AXC_TX_CFG_22 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1058)))
|
||
|
|
#define CPRI_AXC_TX_CFG_23 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x105C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_24 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1060)))
|
||
|
|
#define CPRI_AXC_TX_CFG_25 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1064)))
|
||
|
|
#define CPRI_AXC_TX_CFG_26 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1068)))
|
||
|
|
#define CPRI_AXC_TX_CFG_27 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x106C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_28 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1070)))
|
||
|
|
#define CPRI_AXC_TX_CFG_29 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1074)))
|
||
|
|
#define CPRI_AXC_TX_CFG_30 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1078)))
|
||
|
|
#define CPRI_AXC_TX_CFG_31 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x107C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_32 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1080)))
|
||
|
|
#define CPRI_AXC_TX_CFG_33 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1084)))
|
||
|
|
#define CPRI_AXC_TX_CFG_34 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1088)))
|
||
|
|
#define CPRI_AXC_TX_CFG_35 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x108C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_36 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1090)))
|
||
|
|
#define CPRI_AXC_TX_CFG_37 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1094)))
|
||
|
|
#define CPRI_AXC_TX_CFG_38 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1098)))
|
||
|
|
#define CPRI_AXC_TX_CFG_39 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x109C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_40 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10A0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_41 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10A4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_42 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10A8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_43 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10AC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_44 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10B0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_45 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10B4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_46 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10B8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_47 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10BC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_48 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10C0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_49 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10C4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_50 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10C8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_51 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10CC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_52 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10D0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_53 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10D4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_54 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10D8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_55 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10DC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_56 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10E0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_57 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10E4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_58 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10E8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_59 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10EC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_60 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10F0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_61 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10F4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_62 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10F8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_63 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x10FC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_64 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1100)))
|
||
|
|
#define CPRI_AXC_TX_CFG_65 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1104)))
|
||
|
|
#define CPRI_AXC_TX_CFG_66 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1108)))
|
||
|
|
#define CPRI_AXC_TX_CFG_67 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x110C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_68 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1110)))
|
||
|
|
#define CPRI_AXC_TX_CFG_69 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1114)))
|
||
|
|
#define CPRI_AXC_TX_CFG_70 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1118)))
|
||
|
|
#define CPRI_AXC_TX_CFG_71 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x111C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_72 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1120)))
|
||
|
|
#define CPRI_AXC_TX_CFG_73 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1124)))
|
||
|
|
#define CPRI_AXC_TX_CFG_74 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1128)))
|
||
|
|
#define CPRI_AXC_TX_CFG_75 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x112C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_76 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1130)))
|
||
|
|
#define CPRI_AXC_TX_CFG_77 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1134)))
|
||
|
|
#define CPRI_AXC_TX_CFG_78 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1138)))
|
||
|
|
#define CPRI_AXC_TX_CFG_79 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x113C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_80 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1140)))
|
||
|
|
#define CPRI_AXC_TX_CFG_81 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1144)))
|
||
|
|
#define CPRI_AXC_TX_CFG_82 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1148)))
|
||
|
|
#define CPRI_AXC_TX_CFG_83 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x114C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_84 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1150)))
|
||
|
|
#define CPRI_AXC_TX_CFG_85 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1154)))
|
||
|
|
#define CPRI_AXC_TX_CFG_86 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1158)))
|
||
|
|
#define CPRI_AXC_TX_CFG_87 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x115C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_88 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1160)))
|
||
|
|
#define CPRI_AXC_TX_CFG_89 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1164)))
|
||
|
|
#define CPRI_AXC_TX_CFG_90 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1168)))
|
||
|
|
#define CPRI_AXC_TX_CFG_91 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x116C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_92 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1170)))
|
||
|
|
#define CPRI_AXC_TX_CFG_93 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1174)))
|
||
|
|
#define CPRI_AXC_TX_CFG_94 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1178)))
|
||
|
|
#define CPRI_AXC_TX_CFG_95 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x117C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_96 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1180)))
|
||
|
|
#define CPRI_AXC_TX_CFG_97 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1184)))
|
||
|
|
#define CPRI_AXC_TX_CFG_98 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1188)))
|
||
|
|
#define CPRI_AXC_TX_CFG_99 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x118C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_100 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1190)))
|
||
|
|
#define CPRI_AXC_TX_CFG_101 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1194)))
|
||
|
|
#define CPRI_AXC_TX_CFG_102 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1198)))
|
||
|
|
#define CPRI_AXC_TX_CFG_103 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x119C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_104 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11A0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_105 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11A4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_106 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11A8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_107 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11AC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_108 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11B0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_109 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11B4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_110 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11B8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_111 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11BC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_112 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11C0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_113 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11C4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_114 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11C8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_115 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11CC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_116 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11D0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_117 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11D4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_118 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11D8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_119 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11DC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_120 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11E0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_121 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11E4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_122 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11E8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_123 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11EC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_124 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11F0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_125 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11F4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_126 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11F8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_127 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x11FC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_128 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1200)))
|
||
|
|
#define CPRI_AXC_TX_CFG_129 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1204)))
|
||
|
|
#define CPRI_AXC_TX_CFG_130 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1208)))
|
||
|
|
#define CPRI_AXC_TX_CFG_131 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x120C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_132 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1210)))
|
||
|
|
#define CPRI_AXC_TX_CFG_133 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1214)))
|
||
|
|
#define CPRI_AXC_TX_CFG_134 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1218)))
|
||
|
|
#define CPRI_AXC_TX_CFG_135 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x121C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_136 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1220)))
|
||
|
|
#define CPRI_AXC_TX_CFG_137 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1224)))
|
||
|
|
#define CPRI_AXC_TX_CFG_138 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1228)))
|
||
|
|
#define CPRI_AXC_TX_CFG_139 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x122C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_140 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1230)))
|
||
|
|
#define CPRI_AXC_TX_CFG_141 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1234)))
|
||
|
|
#define CPRI_AXC_TX_CFG_142 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1238)))
|
||
|
|
#define CPRI_AXC_TX_CFG_143 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x123C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_144 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1240)))
|
||
|
|
#define CPRI_AXC_TX_CFG_145 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1244)))
|
||
|
|
#define CPRI_AXC_TX_CFG_146 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1248)))
|
||
|
|
#define CPRI_AXC_TX_CFG_147 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x124C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_148 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1250)))
|
||
|
|
#define CPRI_AXC_TX_CFG_149 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1254)))
|
||
|
|
#define CPRI_AXC_TX_CFG_150 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1258)))
|
||
|
|
#define CPRI_AXC_TX_CFG_151 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x125C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_152 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1260)))
|
||
|
|
#define CPRI_AXC_TX_CFG_153 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1264)))
|
||
|
|
#define CPRI_AXC_TX_CFG_154 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1268)))
|
||
|
|
#define CPRI_AXC_TX_CFG_155 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x126C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_156 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1270)))
|
||
|
|
#define CPRI_AXC_TX_CFG_157 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1274)))
|
||
|
|
#define CPRI_AXC_TX_CFG_158 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1278)))
|
||
|
|
#define CPRI_AXC_TX_CFG_159 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x127C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_160 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1280)))
|
||
|
|
#define CPRI_AXC_TX_CFG_161 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1284)))
|
||
|
|
#define CPRI_AXC_TX_CFG_162 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1288)))
|
||
|
|
#define CPRI_AXC_TX_CFG_163 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x128C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_164 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1290)))
|
||
|
|
#define CPRI_AXC_TX_CFG_165 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1294)))
|
||
|
|
#define CPRI_AXC_TX_CFG_166 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1298)))
|
||
|
|
#define CPRI_AXC_TX_CFG_167 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x129C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_168 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12A0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_169 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12A4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_170 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12A8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_171 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12AC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_172 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12B0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_173 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12B4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_174 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12B8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_175 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12BC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_176 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12C0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_177 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12C4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_178 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12C8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_179 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12CC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_180 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12D0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_181 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12D4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_182 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12D8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_183 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12DC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_184 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12E0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_185 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12E4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_186 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12E8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_187 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12EC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_188 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12F0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_189 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12F4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_190 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12F8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_191 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x12FC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_192 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1300)))
|
||
|
|
#define CPRI_AXC_TX_CFG_193 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1304)))
|
||
|
|
#define CPRI_AXC_TX_CFG_194 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1308)))
|
||
|
|
#define CPRI_AXC_TX_CFG_195 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x130C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_196 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1310)))
|
||
|
|
#define CPRI_AXC_TX_CFG_197 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1314)))
|
||
|
|
#define CPRI_AXC_TX_CFG_198 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1318)))
|
||
|
|
#define CPRI_AXC_TX_CFG_199 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x131C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_200 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1320)))
|
||
|
|
#define CPRI_AXC_TX_CFG_201 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1324)))
|
||
|
|
#define CPRI_AXC_TX_CFG_202 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1328)))
|
||
|
|
#define CPRI_AXC_TX_CFG_203 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x132C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_204 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1330)))
|
||
|
|
#define CPRI_AXC_TX_CFG_205 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1334)))
|
||
|
|
#define CPRI_AXC_TX_CFG_206 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1338)))
|
||
|
|
#define CPRI_AXC_TX_CFG_207 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x133C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_208 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1340)))
|
||
|
|
#define CPRI_AXC_TX_CFG_209 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1344)))
|
||
|
|
#define CPRI_AXC_TX_CFG_210 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1348)))
|
||
|
|
#define CPRI_AXC_TX_CFG_211 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x134C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_212 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1350)))
|
||
|
|
#define CPRI_AXC_TX_CFG_213 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1354)))
|
||
|
|
#define CPRI_AXC_TX_CFG_214 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1358)))
|
||
|
|
#define CPRI_AXC_TX_CFG_215 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x135C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_216 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1360)))
|
||
|
|
#define CPRI_AXC_TX_CFG_217 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1364)))
|
||
|
|
#define CPRI_AXC_TX_CFG_218 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1368)))
|
||
|
|
#define CPRI_AXC_TX_CFG_219 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x136C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_220 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1370)))
|
||
|
|
#define CPRI_AXC_TX_CFG_221 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1374)))
|
||
|
|
#define CPRI_AXC_TX_CFG_222 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1378)))
|
||
|
|
#define CPRI_AXC_TX_CFG_223 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x137C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_224 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1380)))
|
||
|
|
#define CPRI_AXC_TX_CFG_225 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1384)))
|
||
|
|
#define CPRI_AXC_TX_CFG_226 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1388)))
|
||
|
|
#define CPRI_AXC_TX_CFG_227 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x138C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_228 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1390)))
|
||
|
|
#define CPRI_AXC_TX_CFG_229 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1394)))
|
||
|
|
#define CPRI_AXC_TX_CFG_230 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x1398)))
|
||
|
|
#define CPRI_AXC_TX_CFG_231 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x139C)))
|
||
|
|
#define CPRI_AXC_TX_CFG_232 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13A0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_233 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13A4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_234 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13A8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_235 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13AC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_236 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13B0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_237 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13B4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_238 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13B8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_239 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13BC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_240 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13C0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_241 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13C4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_242 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13C8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_243 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13CC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_244 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13D0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_245 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13D4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_246 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13D8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_247 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13DC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_248 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13E0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_249 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13E4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_250 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13E8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_251 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13EC)))
|
||
|
|
#define CPRI_AXC_TX_CFG_252 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13F0)))
|
||
|
|
#define CPRI_AXC_TX_CFG_253 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13F4)))
|
||
|
|
#define CPRI_AXC_TX_CFG_254 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13F8)))
|
||
|
|
#define CPRI_AXC_TX_CFG_255 (*((volatile uint32_t *)(CPRI_CPU_BASE + 0x13FC)))
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define AUX_CTRL_REG (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x00)))
|
||
|
|
#define AUX_INS_NUM (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x04)))
|
||
|
|
#define DATA_CNT_POS0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x08)))
|
||
|
|
#define DATA_CNT_POS1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x0C)))
|
||
|
|
#define DATA_CNT_POS2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x10)))
|
||
|
|
#define DATA_CNT_X0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x14)))
|
||
|
|
#define DATA_CNT_X1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x18)))
|
||
|
|
#define DATA_CNT_X2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x1C)))
|
||
|
|
#define AUX_DATA_TX0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x20)))
|
||
|
|
#define AUX_DATA_TX1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x24)))
|
||
|
|
#define AUX_DATA_TX2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x28)))
|
||
|
|
#define AUX_DATA_TX3 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x2C)))
|
||
|
|
#define AUX_DATA_TX4 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x30)))
|
||
|
|
#define AUX_DATA_TX5 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x34)))
|
||
|
|
#define AUX_DATA_TX6 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x38)))
|
||
|
|
#define AUX_DATA_TX7 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x3C)))
|
||
|
|
#define AUX_DATA_TX8 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x40)))
|
||
|
|
#define AUX_DATA_TX9 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x44)))
|
||
|
|
#define AUX_DATA_EN0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x48)))
|
||
|
|
#define AUX_DATA_EN1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x4C)))
|
||
|
|
#define AUX_DATA_EN2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x50)))
|
||
|
|
#define AUX_DATA_EN3 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x54)))
|
||
|
|
#define AUX_DATA_EN4 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x58)))
|
||
|
|
#define AUX_DATA_EN5 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x5C)))
|
||
|
|
#define AUX_DATA_EN6 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x60)))
|
||
|
|
#define AUX_DATA_EN7 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x64)))
|
||
|
|
#define AUX_DATA_EN8 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x68)))
|
||
|
|
#define AUX_DATA_EN9 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x6C)))
|
||
|
|
#define AUX_CTRL_TX0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x70)))
|
||
|
|
#define AUX_CTRL_TX1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x74)))
|
||
|
|
#define AUX_CTRL_EN_TX0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x78)))
|
||
|
|
#define AUX_CTRL_EN_TX1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x7C)))
|
||
|
|
#define CTRL_CNT_POS0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x80)))
|
||
|
|
#define CTRL_CNT_POS1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x84)))
|
||
|
|
#define CTRL_CNT_POS2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x88)))
|
||
|
|
#define CTRL_CNT_X0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x8C)))
|
||
|
|
#define CTRL_CNT_X1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x90)))
|
||
|
|
#define CTRL_CNT_X2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x94)))
|
||
|
|
#define AUX_INT_FLAG (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xA0)))
|
||
|
|
#define AUX_INT_EN (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xA4)))
|
||
|
|
#define AUX_QOS (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xA8)))
|
||
|
|
#define GMAC_STATUS (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xAC)))
|
||
|
|
#define GMAC_CTRL (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xB0)))
|
||
|
|
#define AWADDR0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xB4)))
|
||
|
|
#define AWADDR1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xB8)))
|
||
|
|
#define AXI_LEN0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xBC)))
|
||
|
|
#define AXI_LEN1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xC0)))
|
||
|
|
#define RX_RFP_WIDE (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xC4)))
|
||
|
|
#define ETH_RX_BUFFER (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xC8)))
|
||
|
|
#define ETH_TX_BUFFER (*((volatile uint32_t *)(CPRI_AUX_BASE + 0xCC)))
|
||
|
|
#define AXI_WADDR (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x00 + 0x4000)))//base 16'h4000 + AXI_WADDR
|
||
|
|
#define AUX_CNT0 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x00 + 0x8000)))//base 16'h8000 + AUX_CNT
|
||
|
|
#define AUX_CNT1 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x04 + 0x8000)))
|
||
|
|
#define AUX_CNT2 (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x08 + 0x8000)))
|
||
|
|
#define FIFO_STATUS (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x0C + 0x8000)))
|
||
|
|
#define AUX_RFP_INT_FLAG (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x10 + 0x8000)))
|
||
|
|
#define AUX_RFP_INT_EN (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x14 + 0x8000)))
|
||
|
|
#define ALARM_FLAG (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x18 + 0x8000)))
|
||
|
|
#define ALARM_INTEN (*((volatile uint32_t *)(CPRI_AUX_BASE + 0x1c + 0x8000)))
|
||
|
|
|
||
|
|
#define TOD_REG_CONFIG (*((volatile uint32_t *)(CPRI_STC_BASE + 0x000 )))
|
||
|
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#define TOD_REG_INT_STATUS (*((volatile uint32_t *)(CPRI_STC_BASE + 0x004 )))
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#define TOD_REG_IRQ_EN (*((volatile uint32_t *)(CPRI_STC_BASE + 0x008 )))
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#define TOD_REG_CLR (*((volatile uint32_t *)(CPRI_STC_BASE + 0x00C )))
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#define TOD_REG_NF (*((volatile uint32_t *)(CPRI_STC_BASE + 0x040 )))
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#define TOD_REG_HSCC (*((volatile uint32_t *)(CPRI_STC_BASE + 0x044 )))
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#define TOD_REG_NSF_INIT_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x048 )))
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#define TOD_REG_NSF_INIT_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x04C )))
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#define TOD_REG_FT_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x050 )))
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#define TOD_REG_FT_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x054 )))
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#define TOD_REG_RT_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x058 )))
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#define TOD_REG_RT_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x05C )))
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#define TOD_REG_SU_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x060 )))
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#define TOD_REG_SU_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x064 )))
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#define TOD_REG_NSF_1PPS_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x068 )))
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#define TOD_REG_NSF_1PPS_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x06C )))
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#define TOD_REG_TOD_LO (*((volatile uint32_t *)(CPRI_STC_BASE + 0x070 )))
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#define TOD_REG_TOD_MI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x074 )))
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#define TOD_REG_TOD_HI (*((volatile uint32_t *)(CPRI_STC_BASE + 0x078 )))
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#define LTBG0_REG_R (*((volatile uint32_t *)(CPRI_STC_BASE + 0x080 )))
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#define LTBG0_REG_N (*((volatile uint32_t *)(CPRI_STC_BASE + 0x084 )))
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#define LTBG0_REG_N1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x088 )))
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#define LTBG0_REG_C (*((volatile uint32_t *)(CPRI_STC_BASE + 0x08C )))
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#define LTBG0_REG_A (*((volatile uint32_t *)(CPRI_STC_BASE + 0x090 )))
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#define LTBG0_TIME_BASE (*((volatile uint32_t *)(CPRI_STC_BASE + 0x094 )))
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#define LTBG0_TIME_SET (*((volatile uint32_t *)(CPRI_STC_BASE + 0x098 )))
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#define LTBG1_REG_R (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0C0 )))
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#define LTBG1_REG_N (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0C4 )))
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#define LTBG1_REG_N1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0C8 )))
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#define LTBG1_REG_C (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0CC )))
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#define LTBG1_REG_A (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0D0 )))
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#define LTBG1_TIME_BASE (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0D4 )))
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#define LTBG1_TIME_SET (*((volatile uint32_t *)(CPRI_STC_BASE + 0x0D8 )))
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#define CTW_REG_TIMER_0_0 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x100 )))
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#define CTW_REG_TIMER_0_1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x104 )))
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#define CTW_REG_TIMER_0_2 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x108 )))
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#define CTW_REG_TIMER_0_3 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x10C )))
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#define CTW_REG_TIMER_1_0 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x110 )))
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#define CTW_REG_TIMER_1_1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x114 )))
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#define CTW_REG_TIMER_1_2 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x118 )))
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#define CTW_REG_TIMER_1_3 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x11C )))
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#define CTW_REG_IRQ_0_0 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x120 )))
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#define CTW_REG_IRQ_0_1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x124 )))
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#define CTW_REG_IRQ_0_2 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x128 )))
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#define CTW_REG_IRQ_0_3 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x12C )))
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#define CTW_REG_IRQ_1_0 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x130 )))
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#define CTW_REG_IRQ_1_1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x134 )))
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#define CTW_REG_IRQ_1_2 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x138 )))
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#define CTW_REG_IRQ_1_3 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x13C )))
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#define CTW_REG_STATUS (*((volatile uint32_t *)(CPRI_STC_BASE + 0x140 )))
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#define LTBG_REG_R (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4000 )))
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#define LTBG_REG_N (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4004 )))
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#define LTBG_REG_N1 (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4008 )))
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#define LTBG_REG_C (*((volatile uint32_t *)(CPRI_STC_BASE + 0x400C )))
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#define LTBG_REG_A (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4010 )))
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#define LTBG_TIME_BASE (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4014 )))
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#define LTBG_TIME_SET (*((volatile uint32_t *)(CPRI_STC_BASE + 0x4018 )))
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#endif
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