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2025-03-02 13:41:38 +08:00
/******************************************************************
* @file ape_common.h
* @brief: [file description]
* @author: xuekun.zhang
* @Date 2022111
* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
* Change_date Owner Change_content
* 2022111 xuekun.zhang create file
*****************************************************************/
#ifndef APE_COMMON_H
#define APE_COMMON_H
/**************************include******************************/
#include "type_define.h"
#define APE_DM0 DM7
#define APE_DM1 DM6
#define APE_DM2 DM5
#define APE_DM3 DM4
#define __APE_DM0 __DM7
#define __APE_DM1 __DM6
#define __APE_DM2 __DM5
#define __APE_DM3 __DM4
#define DM_TO_CSU_ADDR(addr) ((uint32_t)(addr))
#define IM_TO_CSU_ADDR(addr) (((uint32_t)(addr)) + 0x200000)
#define DMA_TAG_G2L 16
#define DMA_TAG_L2G 17
#define DMA_TAG_G2G 18
#define DMA_TAG_CHAIN 19
extern __APE_DM3 v16s32 SVRReg;
#endif