240 lines
8.1 KiB
Plaintext
240 lines
8.1 KiB
Plaintext
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ENTRY( __ucps2_init ) ;
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PROVIDE(__ucps2_istack_bottom = (0x40000 - 0x40)) ;
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PROVIDE(__ucps2_dstack_bottom = (0x240000 - 0x40)) ;/* DM0 */
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PROVIDE(__ucps2_heap_bottom = (0x40000 - 0x40)) ;
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PROVIDE(__ucps2_d0heap_bottom = 0x23C000) ;/* SPU Vector Stack = 4KB, no MPU Stack */
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PROVIDE(__ucps2_d1heap_bottom = 0x280000) ;
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PROVIDE(__ucps2_d2heap_bottom = 0x2c0000) ;
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PROVIDE(__ucps2_d3heap_bottom = 0x300000) ;
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PROVIDE(__ucps2_d4heap_bottom = 0x340000) ;
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PROVIDE(__ucps2_d5heap_bottom = 0x380000) ;
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PROVIDE(__ucps2_d6heap_bottom = 0x3c0000) ;
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PROVIDE(__ucps2_d7heap_bottom = 0x3FC000) ;
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PROVIDE(__ucps2_mim_dyn_start = 0x70000);
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CORE(ape0);
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CACHE_SIZE(128);
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/****************************************************************
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* The segments definition, which affect the load address of the
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* elf.
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*/
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/* All text code & data are in IM */
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SECTIONS {
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/* All .data & .bss are located in IM */
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. = 0x20000; /* icache size: 128KB */
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/* tag start point for bss */
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__ucps2_bss_start = ALIGN(0x4);
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.sbss : { *(.sbss.1*) }
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.sbss : { *(.sbss.2*) }
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.sbss : { *(.sbss.4*) }
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.sbss : { *(.sbss.8*) }
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.sbss : { *(.sbss*)
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ASSERT((. <= 0x40000), "Error: No room for .sbss");
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}
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.bss : { *(.bss*)
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ASSERT((. <= 0x40000), "Error: No room for .bss");
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}
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__ucps2_bss_end = ALIGN(0x4);
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.sdata : { *(.sdata.1*) }
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.sdata : { *(.sdata.2*) }
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.sdata : { *(.sdata.4*) }
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.sdata : { *(.sdata.8*) }
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.sdata : { *(.sdata*)
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ASSERT((. <= 0x40000), "Error: No room for .sdata");
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}
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HIDDEN(__section_end = ALIGN(4));
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/* tag start point for heap */
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__ucps2_heap_start = ALIGN(0x8);
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. = 0x40000;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0)
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ASSERT((. <= 0x70000), "Error: No room for MPU's .text");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/********************************************/
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. = 0x200000;
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HIDDEN(__section_start = .);
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.DM0 : AT(__section_end) { *( .DM0 )
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ASSERT((. <= 0x23C000), "Error: No room for .DM0");
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}
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.rodata : { *(.rodata*)
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ASSERT((. <= 0x23C000), "Error: No room for .rodata");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM0 */
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__ucps2_d0heap_start = ALIGN(0x8);
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. = 0x240000;
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HIDDEN(__section_start = .);
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.DM1 : AT(__section_end) { *( .DM1 )
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ASSERT((. <= 0x280000), "Error: No room for .DM1");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM1 */
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__ucps2_d1heap_start = ALIGN(0x8);
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. = 0x280000;
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HIDDEN(__section_start = .);
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.DM2 : AT(__section_end) { *( .DM2 )
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ASSERT((. <= 0x2c0000), "Error: No room for .DM2");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM2 */
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__ucps2_d2heap_start = ALIGN(0x8);
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. = 0x2c0000;
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HIDDEN(__section_start = .);
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.DM3 : AT(__section_end) { *( .DM3 )
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ASSERT((. <= 0x300000), "Error: No room for .DM3");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM3*/
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__ucps2_d3heap_start = ALIGN(0x8);
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. = 0x300000;
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HIDDEN(__section_start = .);
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.DM4 : AT(__section_end) { *( .DM4 )
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ASSERT((. <= 0x340000), "Error: No room for .DM4");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM4*/
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__ucps2_d4heap_start = ALIGN(0x8);
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. = 0x340000;
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HIDDEN(__section_start = .);
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.DM5 : AT(__section_end) { *( .DM5 )
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ASSERT((. <= 0x380000), "Error: No room for .DM5");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM5*/
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__ucps2_d5heap_start = ALIGN(0x8);
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. = 0x380000;
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HIDDEN(__section_start = .);
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.DM6 : AT(__section_end) { *( .DM6 )
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ASSERT((. <= 0x3c0000), "Error: No room for .DM6");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM6*/
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__ucps2_d6heap_start = ALIGN(0x8);
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. = 0x3C0000;
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HIDDEN(__section_start = .);
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.DM7 : AT(__section_end) { *( .DM7 )
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ASSERT((. <= 0x3FC000), "Error: No room for .DM7");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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/* tag start point for heap in DM7*/
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__ucps2_d7heap_start = ALIGN(0x8);
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. = 0x04000000;
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HIDDEN(__section_start = .);
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.virt.sm : AT(__section_end) { *(.virt.sm)
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ASSERT((. <= 0x04200000), "Error: No room for virtual share memory");
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}
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.noinit.MREG :
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{
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*(noinit.MREG)
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9a800000;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.start)
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ASSERT((. <= 0x9c400000), "Error: No room for SPU start .text");
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}
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.text : { *(.text)
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ASSERT((. <= 0x9c400000), "Error: No room for SPU's .text");
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}
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.text : { *(.text.[^m]*)
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ASSERT((. <= 0x9c400000), "Error: No room for SPU's .text");
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}
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.text : { *(.text.m[^0]*)
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ASSERT((. <= 0x9c400000), "Error: No room for SPU's .text");
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}
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ec00000;
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__ucps2_mim_ddr0_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr0)
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ASSERT((. <= 0x9ec40000), "Error: No room for MIM DDR0 .text");
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}
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__ucps2_mim_ddr0_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ec40000;
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__ucps2_mim_ddr1_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr1)
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ASSERT((. <= 0x9ec80000), "Error: No room for MIM DDR1 .text");
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}
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__ucps2_mim_ddr1_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ec80000;
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__ucps2_mim_ddr2_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr2)
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ASSERT((. <= 0x9ecc0000), "Error: No room for MIM DDR2 .text");
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}
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__ucps2_mim_ddr2_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ecc0000;
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__ucps2_mim_ddr3_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr3)
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ASSERT((. <= 0x9ed00000), "Error: No room for MIM DDR3 .text");
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}
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__ucps2_mim_ddr3_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ed00000;
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__ucps2_mim_ddr4_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr4)
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ASSERT((. <= 0x9ed40000), "Error: No room for MIM DDR4 .text");
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}
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__ucps2_mim_ddr4_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ed40000;
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__ucps2_mim_ddr5_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr5)
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ASSERT((. <= 0x9ed80000), "Error: No room for MIM DDR5 .text");
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}
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__ucps2_mim_ddr5_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9ed80000;
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__ucps2_mim_ddr6_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr6)
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ASSERT((. <= 0x9edc0000), "Error: No room for MIM DDR6 .text");
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}
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__ucps2_mim_ddr6_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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. = 0x9edc0000;
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__ucps2_mim_ddr7_start = .;
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HIDDEN(__section_start = .);
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.text : AT(__section_end) { *(.text.m0.ddr7)
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ASSERT((. <= 0x9ee00000), "Error: No room for MIM DDR7 .text");
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}
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__ucps2_mim_ddr7_end = .;
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HIDDEN(__section_end = ALIGN(4) - __section_start + __section_end);
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HIDDEN(__section_start = 0xffffffff);
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HIDDEN(__section_end = 0xffffffff);
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}
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