YB_TX_RX_APE_PRJ/Common/inc/mem_def.h

/******************************************************************
 * @file  ucp_mem_def.h
 * @brief:   两片UCP的内存分布头文件
 * @author: xuekun.zhang
 * @Date 2021年1月5日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
 * Change_date         Owner         Change_content
 * 2021年1月5日        xuekun.zhang       create file

*****************************************************************/

#ifndef     UCP_MEM_DEF_H
#define     UCP_MEM_DEF_H

//！命名宏定义时需要注意UCP使用的地址
/*********************************UCP************************************************/
#define SM0_BASE                    	(0x09D00000)//1M
#define SM1_BASE                    	(0x09E00000)//1M
#define SM2_BASE                    	(0x09F00000)//1.5M
#define SM3_BASE                    	(0x0A080000)//1.5M
#define SM4_BASE                    	(0x0A200000)//1.5M
#define SM5_BASE                    	(0x0A380000)//1.5M

//len define 
//SM0

//SM1
#define TIME_DATA_SLOT_LEN              (0x0003c000)  //61440*4byte = 240k
//SM2
#define TRANSMITTER_OUT_LEN              (0x0003c000)   //TODO:确定实际长度
//SM3
#define SM3_NR_PUCCH_LUT_LEN		    (0x00040000)  //256K
#define SM3_PHY_MSG_BUFFER_LEN          (0x00000400)  //1K
//DDR
#define TRACE_GRP_LEN                   (0x00000200)  //128Word    

/************************************SM0--1M*************************************************/
#define RECEIVER_SYNC_CFG_BASE             (SM0_BASE) 
#define RECEIVER_SYMB_CFG_BASE             (RECEIVER_SYNC_CFG_BASE + 0x100) 
#define RECEIVER_BIT_CFG_BASE              (RECEIVER_SYMB_CFG_BASE + 0x100) 
/************************************SM1---1M ***********************************************/ 
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR    (SM1_BASE)
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR    (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR    (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR    (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR  (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
/************************************SM2--1.5M***********************************************/
#define TRANSMITTER_OUT                  (SM2_BASE)
#define TRANSMITTER_BASE                 (TRANSMITTER_OUT) //4k对齐
/************************************SM3--1.5M***********************************************/
#define SM3_PHY_MSG_BUFFER_ADDR                    (SM3_BASE)
#define SM3_PHY_TASKS_MGR_ADDR                     (SM3_PHY_MSG_BUFFER_ADDR + SM3_PHY_MSG_BUFFER_LEN)
/************************************SM4--1.5M***********************************************/
//TODO:地址规划
#define RECEIVER_OUT1                  (SM4_BASE)
#define RECEIVER_OUT2                  (SM4_BASE + 0x4000)
#define RECEIVER_OUT3                  (SM4_BASE + 0x8000)
#define RECEIVER_SYMB_OUT              (RECEIVER_OUT1)

/************************************SM5--1.5M***********************************************/
#define RECEIVER_BASE                 (SM5_BASE) //4k对齐
/**************************************DDR***************************************************/
#define DDR_PHY_BASE                           (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
#define DDR_ERROR_RECORD_CNT_ADDR              (0x79FF8000)
#define DDR_STATE_RECORD_CNT_ADDR              (0x79FFc000)

//
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR	   (0x60F00000)	//0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR	   (0x610E0000)	//0x1E0000
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR      (0x6BC00000)  //!!!DDR_PHY_BASE 0x1E0000 
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR       (0x6BDE0000)  // 0x1E0000
#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR      (0x6BFC0000)  // 0x1E0000 用于暂存数据供first_sync处理
#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR      (0x6C1A0000)  // 0x1E0000 用于暂存数据供first_sync处理

#define SOURCE_DATA_DDR_ADDR                    (0x84C01000)
#define SOURCE_DATA_FLAG_DDR_ADDR               (0x84C00000)    // SPU READ FLAG
#define SOURCE_DATA_BYTE_LENGTH                 (16016)


#define TRACE_RECEIVER_ADDR                             (0x88700000)
#define TRACE_RECV_INIT_ADDR                            (TRACE_RECEIVER_ADDR) //0x88700000
#define TRACE_SLOTIND_ADDR                              (TRACE_RECV_INIT_ADDR + TRACE_GRP_LEN) //0x88700200
#define TRACE_RECEIVER_SYNC_ADDR                        (TRACE_SLOTIND_ADDR + TRACE_GRP_LEN) // 0x88700400
#define TRACE_RECEIVER_SYMB_ADDR                        (TRACE_RECEIVER_SYNC_ADDR + TRACE_GRP_LEN)// 0x88700600
#define TRACE_RECEIVER_BIT_ADDR                         (TRACE_RECEIVER_SYMB_ADDR + TRACE_GRP_LEN)// 0x88700800
#define TRACE_TESTTASK_ADDR                             (TRACE_RECEIVER_BIT_ADDR + TRACE_GRP_LEN) // 0x88700a00
#define TRACE_RECEIVER_SYNC_FIRST_ADDR                  (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700c00
#define TRACE_RECEIVER_SYNC_FINE_ADDR                   (TRACE_RECEIVER_SYNC_FIRST_ADDR + TRACE_GRP_LEN) // 0x88700e00
#define TRACE_PCIE_ADDR                                 (TRACE_RECEIVER_SYNC_FINE_ADDR + TRACE_GRP_LEN) //0x88701000

#define TRACE_TRANSMITTER_ADDR                          (TRACE_PCIE_ADDR + TRACE_GRP_LEN)  // 0x88701200
#define TRACE_TRANS_INIT_ADDR                           (TRACE_TRANSMITTER_ADDR + TRACE_GRP_LEN)  // 0x88701400

#endif