Merge branch 'PCIE' of http://47.100.68.68:3000/jinhong/YB_TX_RX_SPU into PCIE
This commit is contained in:
commit
168f1bb98e
@ -37,11 +37,12 @@ void ChannelEquImpl(
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){
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){
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volatile int a = 1;
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volatile int a = 1;
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int numSym = 7 ; ///7;
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int numSym = 7;
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int Scale = 13;
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int Scale = 13;
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int NRE=4096;
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int NRE=4096;
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int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
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int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
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int NumCB = 2;
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int NumCB = 2;
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CfgAgcShift[0] = 1;
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for(int i=0;i<NumCB;i++){
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for(int i=0;i<NumCB;i++){
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@ -83,6 +84,28 @@ void ChannelEquImpl(
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// TRACE(TRACE_RECEIVER_SYMB_ADDR, 24, *channelEst_dm0_ptr);
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// TRACE(TRACE_RECEIVER_SYMB_ADDR, 25, *(channelEst_dm0_ptr+1));
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// TRACE(TRACE_RECEIVER_SYMB_ADDR, 26, *(channelEst_dm0_ptr+2));
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// TRACE(TRACE_RECEIVER_SYMB_ADDR, 27, *(channelEst_dm0_ptr+3));
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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AgcShiftForFftInt32(
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(int)CfgAgcShift,
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MPU_ADDR(Fft_est_dm3_ptr),
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MPU_ADDR(Fft_est_dm3_ptr),
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4096,
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1,
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MPU_ADDR(AgcFactor),
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MPU_ADDR(AgcFactor),
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MPU_ADDR(channelEst_dm0_ptr),
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MPU_ADDR(channelEst_dm0_ptr)
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);
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SVRReg[0] = MPU_ADDR(CfgAgcShift);
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AgcShiftForFftInt32Asm(SVRReg);
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WAIT_MPU_STOP;
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Fft4096Int32(
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Fft4096Int32(
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(int)CfgFft4096,
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(int)CfgFft4096,
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1,
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1,
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@ -101,6 +124,22 @@ void ChannelEquImpl(
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WAIT_MPU_STOP;
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WAIT_MPU_STOP;
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
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(uint64_t)0x84c00000,
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4096*4 ,
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DMA_TAG_L2G,
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1);
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//构造第二根天线
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ByteCopy((int)CfgByteCopy, MPU_ADDR(channelEst_dm0_ptr),MPU_ADDR(Fft_est_dm3_ptr + 4096),16384);
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SVRReg[0] = MPU_ADDR(CfgByteCopy);
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ByteCopyAsm(SVRReg);
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if(i==1){
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InData_ddr_ptr = InData_ddr_ptr + 7*(68+4096) + 1024 + 72;
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}
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
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(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
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(uint64_t)0x84c00000,
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(uint64_t)0x84c00000,
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@ -121,6 +160,42 @@ void ChannelEquImpl(
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int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
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int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
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int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
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int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
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int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
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int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_dma_1D_G2L_ch0ch1_transfer(
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(uint64_t)(InData_ddr_ptr + 68) ,
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(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
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4096*4,
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DMA_TAG_G2L,
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1);
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WAIT_MPU_STOP;
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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for(int j=0;j<numSym;j++){
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AgcShiftForFftInt32(
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(int)CfgAgcShift,
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MPU_ADDR(Fft_outputdata_dm3_ptr),
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MPU_ADDR(Fft_outputdata_dm3_ptr),
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4096,
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1,
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MPU_ADDR(AgcFactor),
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MPU_ADDR(AgcFactor),
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MPU_ADDR(InData_dm0_ptr),
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MPU_ADDR(InData_dm0_ptr)
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);
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SVRReg[0] = MPU_ADDR(CfgAgcShift);
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AgcShiftForFftInt32Asm(SVRReg);
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WAIT_MPU_STOP;
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, *Fft_outputdata_dm3_ptr);
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, *(Fft_outputdata_dm3_ptr+1));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 14, *InData_dm0_ptr);
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 15, *(InData_dm0_ptr+1));
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_dma_1D_G2L_ch0ch1_transfer(
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ape_csu_dma_1D_G2L_ch0ch1_transfer(
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@ -175,6 +250,15 @@ void ChannelEquImpl(
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WAIT_MPU_STOP;
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WAIT_MPU_STOP;
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
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(uint64_t)0x84d00000,
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4096*4 ,
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DMA_TAG_L2G,
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1);
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
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(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
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(uint64_t)0x84d00000,
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(uint64_t)0x84d00000,
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@ -248,6 +332,27 @@ void ChannelEquImpl(
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/****************************** IFFT ****************************************8*/
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int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 16, *Equ_Output_2);
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, *(Equ_Output_2+1));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, *(Equ_Output_2+2));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, *(Equ_Output_2+3));
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//提前准备下一块数据
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if(j<numSym-1){
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*(j+1) + 68), //(68+4096)*(j+1) + 68)
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(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
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4096*4,
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DMA_TAG_G2L,
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0);
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}
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/****************************** IFFT ****************************************8*/
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/****************************** IFFT ****************************************8*/
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int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
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int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
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IFFT4096DataTurn(
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IFFT4096DataTurn(
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@ -264,6 +369,7 @@ void ChannelEquImpl(
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WAIT_MPU_STOP;
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WAIT_MPU_STOP;
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int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
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int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
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IFFT4096(
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IFFT4096(
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(int)CfgIFFT4096,
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(int)CfgIFFT4096,
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@ -301,6 +407,12 @@ void ChannelEquImpl(
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
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SVRReg[0] = MPU_ADDR(ConfigAddCp);
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AddCPAsm(SVRReg);
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WAIT_MPU_STOP;
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
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TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_task_lookup(DMA_TAG_G2L, 1);
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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ape_csu_dma_1D_L2G_ch0ch1_transfer(
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@ -38,7 +38,7 @@ void Receiver_Symb_Proc(
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//data读入
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//data读入
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//获取源数据地址
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//获取源数据地址
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receiver_sync2symb_t* para_dm_ptr = param_ptr;
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receiver_sync2symb_t* para_dm_ptr = param_ptr;
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//TODO: 计算完成结果需要存到下面两个buffer地址中的一个
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//TODO: 计算完成结果需要存到下面两个buffer地址中的一个
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uint32_t cur_out_ddr_ptr = (0 == g_symb2bit_buffer_sel) ? ((uint32_t)RECEIVER_SYMB2BIT_BUFFER0_ADDR) : ((uint32_t)RECEIVER_SYMB2BIT_BUFFER1_ADDR);
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uint32_t cur_out_ddr_ptr = (0 == g_symb2bit_buffer_sel) ? ((uint32_t)RECEIVER_SYMB2BIT_BUFFER0_ADDR) : ((uint32_t)RECEIVER_SYMB2BIT_BUFFER1_ADDR);
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//LOG_ERROR_S("%d %d %d %d 0x%08x 0x%08x %d %d\n",para_dm_ptr->sfn, para_dm_ptr->slot, para_dm_ptr->num_data_section,
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//LOG_ERROR_S("%d %d %d %d 0x%08x 0x%08x %d %d\n",para_dm_ptr->sfn, para_dm_ptr->slot, para_dm_ptr->num_data_section,
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@ -108,32 +108,18 @@ void Receiver_Symb_Proc(
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TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 8, time1 -time0);
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TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 8, time1 -time0);
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time0 = time1;
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time0 = time1;
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// #ifdef IDE_TEST
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#ifdef IDE_TEST
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// printf("DataTrans");
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printf("DataTrans");
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// #endif
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#endif
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//return ;
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return ;
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//7.核间消息to APE2
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//7.核间消息to APE2
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//需要定义结构体
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//需要定义结构体
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receiver_symb2bit_t data_send2bit_task;
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//更新buffer
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g_symb2bit_buffer_sel = (g_symb2bit_buffer_sel + 1) & 0x1;
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data_send2bit_task.proc_id = para_dm_ptr->proc_id;
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data_send2bit_task.sfn = para_dm_ptr->sfn;
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data_send2bit_task.slot = para_dm_ptr->slot;
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data_send2bit_task.data_ptr = cur_out_ddr_ptr;
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data_send2bit_task.data_length = 57344;//TODO:待确认,单位WORD
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//LOG_ERROR_S("%d 0x%08x %d\n",data_send2bit_task.proc_id, data_send2bit_task.data_ptr, g_symb2bit_buffer_sel);
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#ifdef CORE_ODD
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uint8_t cur_core_id = APE3_CORE_ID;
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#else
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uint8_t cur_core_id = APE5_CORE_ID;
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#endif
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phy_et_msg_send((uint32_t)(&data_send2bit_task),
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phy_et_msg_send((uint32_t)(&data_send2bit_task),
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sizeof(receiver_symb2bit_t),
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sizeof(receiver_symb2bit_t),
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UCP4008_KERNEL_INTER,
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UCP4008_KERNEL_INTER,
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cur_core_id,
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APE5_CORE_ID,
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APE6_CORE_ID,
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APE6_CORE_ID,
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PHY_TASK_RECEIVER_SYMB,
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PHY_TASK_RECEIVER_SYMB,
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PHY_TASK_RECEIVER_BIT);
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PHY_TASK_RECEIVER_BIT);
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@ -45,10 +45,15 @@ freOffEstAsm:
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IMA0: ReadMR(L) -> IMA0.T0; // real
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IMA0: ReadMR(L) -> IMA0.T0; // real
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IMA0: ReadMR(H) -> IMA1.T0; // imag
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IMA0: ReadMR(H) -> IMA1.T0; // imag
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NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;
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IMA0: T0 >> 12(W) -> IMA0.T0 || IMA1: T0 >> 12(W) -> IMA1.T0;
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IMA0: T0 >> 12(W) -> IMA0.T0 || IMA1: T0 >> 12(W) -> IMA1.T0;
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NOP;NOP;
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NOP;NOP;
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IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2;
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IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2;
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NOP;
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NOP;
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NOP;
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NOP;
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IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2;
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IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2;
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SHU1: VImm(0) -> SHU1.T0;
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SHU1: VImm(0) -> SHU1.T0;
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IMA0: V(0) -> IMA0.T1;
|
IMA0: V(0) -> IMA0.T1;
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@ -56,7 +61,8 @@ freOffEstAsm:
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SHU0: Index(T2,T6) -> IMA3.T1;
|
SHU0: Index(T2,T6) -> IMA3.T1;
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SHU1: Index(T2,T6) -> IMA3.T0;
|
SHU1: Index(T2,T6) -> IMA3.T0;
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NOP;NOP;
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NOP;NOP;NOP;NOP;
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IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0;
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IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0;
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IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1;
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IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1;
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@ -66,8 +72,8 @@ freOffEstAsm:
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IMA3: T1 -> IMA2.T1;
|
IMA3: T1 -> IMA2.T1;
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MFetch: REPEAT @(5);
|
MFetch: REPEAT @(5);
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//CORDIC ATAN2
|
|
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//CORDIC ATAN2
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Mfetch: Lpto %ENDCORDIC @(KI1);
|
Mfetch: Lpto %ENDCORDIC @(KI1);
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IMA3: T0>>8(W) -> M[19];
|
IMA3: T0>>8(W) -> M[19];
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@ -78,10 +84,11 @@ freOffEstAsm:
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NOP;NOP;NOP;NOP;
|
NOP;NOP;NOP;NOP;
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IMA3: T1 >> T4(W) -> IMA3.T2;
|
IMA3: T1 >> T4(W) -> IMA3.T2;
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IMA3: T0 >> T4(W) -> IMA3.T3;
|
IMA3: T0 >> T4(W) -> IMA3.T3;
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NOP;
|
NOP;NOP;NOP;NOP;NOP;NOP;NOP;
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|
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MFetch: IF(KI3>=KI11) JUMP %IFFI;
|
MFetch: IF(KI3>=KI11) JUMP %IFFI;
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//IMA1: 0 -> T0;
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IMA3: 0 - T2(W) -> IMA3.T2;
|
IMA3: 0 - T2(W) -> IMA3.T2;
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IMA0: 0 - T0(W) -> IMA0.T0;
|
IMA0: 0 - T0(W) -> IMA0.T0;
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IMA3: 0 - T3(W) -> IMA3.T3;
|
IMA3: 0 - T3(W) -> IMA3.T3;
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@ -96,13 +103,11 @@ freOffEstAsm:
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|||||||
|
|
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ENDCORDIC:
|
ENDCORDIC:
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MFetch: REPEAT @(10);
|
MFetch: REPEAT @(10);
|
||||||
|
|
||||||
IMA0: T1 -> BIU2.T0(Mode0);
|
IMA0: T1 -> BIU2.T0(Mode0);
|
||||||
NOP;NOP;NOP;NOP;
|
NOP;NOP;NOP;NOP;
|
||||||
BIU2: Store(T0,T1)(A++);
|
BIU2: Store(T0,T1)(A++);
|
||||||
|
MFetch: REPEAT @(15);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
MFetch:MPU.STOP;
|
MFetch:MPU.STOP;
|
||||||
|
|
||||||
|
Loading…
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Reference in New Issue
Block a user