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Merge branch 'PCIE' of http://47.100.68.68:3000/jinhong/YB_TX_RX_SPU into PCIE

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HUOHUO 2025-05-27 10:57:28 -07:00
commit 168f1bb98e
3 changed files with 133 additions and 30 deletions
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114
APELib/Receiver_symb/src/channelEquImpl.s.c
View File

@ -37,11 +37,12 @@ void ChannelEquImpl(
){
volatile int a = 1;
int numSym = 7 ; ///7;
int numSym = 7;
int Scale = 13;
int NRE=4096;
int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
int NumCB = 2;
CfgAgcShift[0] = 1;
for(int i=0;i<NumCB;i++){
@ -83,6 +84,28 @@ void ChannelEquImpl(
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 24, *channelEst_dm0_ptr);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 25, *(channelEst_dm0_ptr+1));
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 26, *(channelEst_dm0_ptr+2));
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 27, *(channelEst_dm0_ptr+3));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
AgcShiftForFftInt32(
(int)CfgAgcShift,
MPU_ADDR(Fft_est_dm3_ptr),
MPU_ADDR(Fft_est_dm3_ptr),
4096,
1,
MPU_ADDR(AgcFactor),
MPU_ADDR(AgcFactor),
MPU_ADDR(channelEst_dm0_ptr),
MPU_ADDR(channelEst_dm0_ptr)
);
SVRReg[0] = MPU_ADDR(CfgAgcShift);
AgcShiftForFftInt32Asm(SVRReg);
WAIT_MPU_STOP;
Fft4096Int32(
(int)CfgFft4096,
1,
@ -101,6 +124,22 @@ void ChannelEquImpl(
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
(uint64_t)0x84c00000,
4096*4 ,
DMA_TAG_L2G,
1);
//构造第二根天线
ByteCopy((int)CfgByteCopy, MPU_ADDR(channelEst_dm0_ptr),MPU_ADDR(Fft_est_dm3_ptr + 4096),16384);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
if(i==1){
InData_ddr_ptr = InData_ddr_ptr + 7*(68+4096) + 1024 + 72;
}
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
(uint64_t)0x84c00000,
@ -122,6 +161,42 @@ void ChannelEquImpl(
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)(InData_ddr_ptr + 68) ,
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
4096*4,
DMA_TAG_G2L,
1);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
for(int j=0;j<numSym;j++){
AgcShiftForFftInt32(
(int)CfgAgcShift,
MPU_ADDR(Fft_outputdata_dm3_ptr),
MPU_ADDR(Fft_outputdata_dm3_ptr),
4096,
1,
MPU_ADDR(AgcFactor),
MPU_ADDR(AgcFactor),
MPU_ADDR(InData_dm0_ptr),
MPU_ADDR(InData_dm0_ptr)
);
SVRReg[0] = MPU_ADDR(CfgAgcShift);
AgcShiftForFftInt32Asm(SVRReg);
WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, *Fft_outputdata_dm3_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, *(Fft_outputdata_dm3_ptr+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 14, *InData_dm0_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 15, *(InData_dm0_ptr+1));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)(InData_ddr_ptr + 68) ,
@ -175,6 +250,15 @@ void ChannelEquImpl(
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
(uint64_t)0x84d00000,
4096*4 ,
DMA_TAG_L2G,
1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
(uint64_t)0x84d00000,
@ -248,6 +332,27 @@ void ChannelEquImpl(
/****************************** IFFT ****************************************8*/
int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
TRACE(TRACE_RECEIVER_SYMB_ADDR, 16, *Equ_Output_2);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, *(Equ_Output_2+2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, *(Equ_Output_2+3));
//提前准备下一块数据
if(j<numSym-1){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*(j+1) + 68), //(68+4096)*(j+1) + 68)
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
4096*4,
DMA_TAG_G2L,
0);
}
/****************************** IFFT ****************************************8*/
int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
IFFT4096DataTurn(
@ -264,6 +369,7 @@ void ChannelEquImpl(
WAIT_MPU_STOP;
int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
IFFT4096(
(int)CfgIFFT4096,
@ -301,6 +407,12 @@ void ChannelEquImpl(
TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
SVRReg[0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(SVRReg);
WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(

26
APELib/Receiver_symb/src/receiver_Symb_Proc.s.c
View File

@ -108,32 +108,18 @@ void Receiver_Symb_Proc(
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 8, time1 -time0);
time0 = time1;
// #ifdef IDE_TEST
// printf("DataTrans");
// #endif
//return ;
#ifdef IDE_TEST
printf("DataTrans");
#endif
return ;
//7.核间消息to APE2
//需要定义结构体
//更新buffer
g_symb2bit_buffer_sel = (g_symb2bit_buffer_sel + 1) & 0x1;
data_send2bit_task.proc_id = para_dm_ptr->proc_id;
data_send2bit_task.sfn = para_dm_ptr->sfn;
data_send2bit_task.slot = para_dm_ptr->slot;
data_send2bit_task.data_ptr = cur_out_ddr_ptr;
data_send2bit_task.data_length = 57344;//TODO:待确认，单位WORD
//LOG_ERROR_S("%d 0x%08x %d\n",data_send2bit_task.proc_id, data_send2bit_task.data_ptr, g_symb2bit_buffer_sel);
#ifdef CORE_ODD
uint8_t cur_core_id = APE3_CORE_ID;
#else
uint8_t cur_core_id = APE5_CORE_ID;
#endif
receiver_symb2bit_t data_send2bit_task;
phy_et_msg_send((uint32_t)(&data_send2bit_task),
sizeof(receiver_symb2bit_t),
UCP4008_KERNEL_INTER,
cur_core_id,
APE5_CORE_ID,
APE6_CORE_ID,
PHY_TASK_RECEIVER_SYMB,
PHY_TASK_RECEIVER_BIT);

19
MicroCode/Fre_est/src/mpu0/freOffEstAsm.m0.asm
View File

@ -45,10 +45,15 @@ freOffEstAsm:
IMA0: ReadMR(L) -> IMA0.T0; // real
IMA0: ReadMR(H) -> IMA1.T0; // imag
NOP;NOP;NOP;NOP;
IMA0: T0 >> 12(W) -> IMA0.T0 || IMA1: T0 >> 12(W) -> IMA1.T0;
NOP;NOP;
IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2;
NOP;
NOP;
NOP;
NOP;
IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2;
SHU1: VImm(0) -> SHU1.T0;
IMA0: V(0) -> IMA0.T1;
@ -56,7 +61,8 @@ freOffEstAsm:
SHU0: Index(T2,T6) -> IMA3.T1;
SHU1: Index(T2,T6) -> IMA3.T0;
NOP;NOP;
NOP;NOP;NOP;NOP;
IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0;
IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1;
@ -66,8 +72,8 @@ freOffEstAsm:
IMA3: T1 -> IMA2.T1;
MFetch: REPEAT @(5);
//CORDIC ATAN2
//CORDIC ATAN2
Mfetch: Lpto %ENDCORDIC @(KI1);
IMA3: T0>>8(W) -> M[19];
@ -78,10 +84,11 @@ freOffEstAsm:
NOP;NOP;NOP;NOP;
IMA3: T1 >> T4(W) -> IMA3.T2;
IMA3: T0 >> T4(W) -> IMA3.T3;
NOP;
NOP;NOP;NOP;NOP;NOP;NOP;NOP;
MFetch: IF(KI3>=KI11) JUMP %IFFI;
//IMA1: 0 -> T0;
IMA3: 0 - T2(W) -> IMA3.T2;
IMA0: 0 - T0(W) -> IMA0.T0;
IMA3: 0 - T3(W) -> IMA3.T3;
@ -96,13 +103,11 @@ freOffEstAsm:
ENDCORDIC:
MFetch: REPEAT @(10);
IMA0: T1 -> BIU2.T0(Mode0);
NOP;NOP;NOP;NOP;
BIU2: Store(T0,T1)(A++);
MFetch: REPEAT @(15);
MFetch:MPU.STOP;