Merge branch 'PCIE_PILOT_FIX' of http://47.100.68.68:3000/jinhong/YB_TX_RX_SPU into PCIE
到5月27日为止的Recv_symb的修改和最新分支合并,遗留两个Recv编译通过问题待确认搜 TODO 带20250528字样的地方
This commit is contained in:
commit
1ec60e0b27
7
.vscode/settings.json
vendored
7
.vscode/settings.json
vendored
@ -43,6 +43,11 @@
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"trasnsmitter_transform_para_func.h": "c",
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"log_interface.h": "c",
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"transform_para_func.h": "c",
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"equalizer_1port.h": "c"
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"equalizer_1port.h": "c",
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"task_define.h": "c",
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"test_macro.h": "c",
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"receiver_sync_macro.h": "c",
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"osp_ape.h": "c",
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"transmitter_struct.h": "c"
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}
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}
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@ -22,6 +22,7 @@ void Slot_ind_Task()
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L1GeneralMsgHdr_t* msg_general_hdr = (L1GeneralMsgHdr_t*)(msg_header + 1);
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L1SlotIndication_t *slot_ind = (L1SlotIndication_t *)(msg_general_hdr + 1);
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// LOG_ERROR_S("ind %d %d %d\n", cur_sfn, cur_slot, GET_CNT_VAL(0));
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msg_header->msgNum = 1;
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msg_header->rev = 0;
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0
APE0/MpuAsmInc/.gitkeep
Normal file
0
APE0/MpuAsmInc/.gitkeep
Normal file
@ -58,6 +58,7 @@ void Phy_Task_Ape3_Reg()
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// osp_task_create(&ape3_event_task_info);
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// osp_task_create(&ape3_event_task_info_del);
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osp_task_create(&mgr_task);
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//osp_timer_sync(1);
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LOG_INFO_S("APE3 finish task create!\n");
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return ;
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@ -30,16 +30,16 @@ void ape4_event_task(uint32_t addr, uint32_t size)
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uint32_t ape_id = get_core_id();
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osp_task_info_ex mgr_task2 =
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{PHY_TASK_RECEIVER_SYNC, "Receiver_Sync", PHY_TASK_PRI_RECEIVER_SYNC, 2048, OSP_TIMER_TYPE, 0x000, 0x3FF, 50, (OSP_TASKINIT_FUNC)Receiver_Sync_Init, (OSP_TASKENTRY_FUNC)Receiver_Sync_Task};
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osp_task_info_ex mgr_task3 =
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{PHY_TASK_TEST, "Test_Task", PHY_TASK_PRI_TEST, 4096, OSP_TIMER_TYPE, 0x000, 0x3FF, 50, NULL, (OSP_TASKENTRY_FUNC)Test_Task};
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{PHY_TASK_RECEIVER_SYNC, "Receiver_Sync", PHY_TASK_PRI_RECEIVER_SYNC, 8192, OSP_TIMER_TYPE, 0x000, 0x3FF, 50, (OSP_TASKINIT_FUNC)Receiver_Sync_Init, (OSP_TASKENTRY_FUNC)Receiver_Sync_Task};
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// osp_task_info_ex mgr_task3 =
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// {PHY_TASK_TEST, "Test_Task", PHY_TASK_PRI_TEST, 4096, OSP_TIMER_TYPE, 0x000, 0x3FF, 50, NULL, (OSP_TASKENTRY_FUNC)Test_Task};
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TRACE(TRACE_RECV_INIT_ADDR, 2, 1);
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osp_task_create(&mgr_task2);
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TRACE(TRACE_RECV_INIT_ADDR, 3, 1);
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LOG_INFO_S("APE4 finish task create!\n");
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//LOG_INFO_S("APE4 finish task create!\n");
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osp_timer_sync(1);
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TRACE(TRACE_RECV_INIT_ADDR, 4, 1);
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@ -64,8 +64,8 @@ void ape4_event_task_del(uint32_t addr, uint32_t size)
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*/
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void Phy_Task_Ape4_Reg()
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{
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osp_task_info_ex ape4_event_task_info = {50, "ape4_event_task1", 50, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape4_event_task};
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osp_task_info_ex ape4_event_task_info_del = {51, "ape4_event_task_del1", 51, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape4_event_task_del};
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osp_task_info_ex ape4_event_task_info = {50, "ape4_event_task1", 50, 3072, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape4_event_task};
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osp_task_info_ex ape4_event_task_info_del = {51, "ape4_event_task_del1", 51, 3072, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape4_event_task_del};
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@ -90,8 +90,9 @@ void phy_init()
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// //初始化函数里面尽量不要输出log,因为可能初始化时msg_transfer_open还未完成
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log_level_e log_level = INFO;
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log_pool_init();
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TRACE(TRACE_RECV_INIT_ADDR, 1, 2);
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set_log_level(log_level);
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TRACE(TRACE_RECV_INIT_ADDR, 1, 3);
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//memset(&g_phy_cell_cfg, 0, sizeof(phy_cell_cfg_t));
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Phy_Task_Ape4_Reg();
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@ -1,6 +1,6 @@
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############################
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# mpu libs need to link to this APE, could be specified by user
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MICRO_CODE_LIBS:=ByteCopy SyncVer
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MICRO_CODE_LIBS:=ByteCopy SyncVer Sliding
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############################
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# tool path, could be specified by user
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#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin
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@ -58,6 +58,7 @@ void Phy_Task_Ape5_Reg()
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// osp_task_create(&ape5_event_task_info);
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// osp_task_create(&ape5_event_task_info_del);
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osp_task_create(&mgr_task);
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//osp_timer_sync(1);
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LOG_INFO_S("APE5 finish task create!\n");
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return ;
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@ -59,6 +59,7 @@ void Phy_Task_Ape6_Reg()
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// osp_task_create(&ape6_event_task_info);
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// osp_task_create(&ape6_event_task_info_del);
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osp_task_create(&mgr_task);
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//osp_timer_sync(1);
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LOG_INFO_S("APE6 finish task create!\n");
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@ -135,7 +135,7 @@ clean:
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@rm -rf *.daidir work *.lib++ *~ *.rc csrc *.key filelist.f simv*
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@rm -rf DVEfiles vc_hdrs.h urgReport *.rc *.vpd *.log
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@rm -rf *.sym *.data *.bak slot-*.txt PC_Line*.txt codes.txt UCPMDis.txt *.saif
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@rm -rf Simulator_*.dat saif.cmds Run_Cycle.dat *.elf ucps_pc_code.txt Receiver_bit Transform_func
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@rm -rf Simulator_*.dat saif.cmds Run_Cycle.dat *.elf ucps_pc_code.txt Receiver_bit Transform_func TestTask
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@rm -rf Executed_Pipeline.csv
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@find . -name "*.o" -exec rm -f {} \;
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@find . -name "*.a" -exec rm -f {} \;
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@ -1,14 +0,0 @@
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#ifndef FRAME_TEST_H
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#define FRAME_TEST_H
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#include "ape_common.h"
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#include "task_define.h"
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#include "log_interface.h"
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#include "msg_interface.h"
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#include "msg_transfer_layer.h"
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#include "drv_ape.h"
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#include "trace.h"
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void Test_Task();
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#endif
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@ -1,77 +0,0 @@
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#include "Frame_test.h"
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void Test_Task()
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{
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uint16_t start_slot = TIME_SLOT();
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g_time_start[0] = TIME_NS();
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RUN_CNT(TRACE_TESTTASK_ADDR, 0);
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uint32_t cur_sfn = get_rx_nr_sfn();
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uint32_t cur_slot = get_rx_nr_slot();
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int32_t *transmitter_malloc_dm0_ptr;
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LOG_ERROR_S("cur_sfn:%d, cur_slot:%d\n", cur_sfn, cur_slot);
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TRACE(TRACE_TESTTASK_ADDR, 3, 1);
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//0 空间回收
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dmalloc_trim(0, APE_DM0);
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dmalloc_trim(0, APE_DM1);
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dmalloc_trim(0, APE_DM2);
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dmalloc_trim(0, APE_DM3);
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//1. DM0空间申请
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transmitter_malloc_dm0_ptr = dmemalign_unit(0x4000, 131072, APE_DM0); //申请了128KiB 首地址16k对齐
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if (NULLPTR == transmitter_malloc_dm0_ptr)
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{
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//LOG_ERROR_S("alloc DM0 err\n", cur_sfn, cur_slot);
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return;
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}
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int32_t *output_data_ptr;// 最终输出数据地址(dm)
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output_data_ptr = transmitter_malloc_dm0_ptr;
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TRACE(TRACE_TESTTASK_ADDR, 3, 2);
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uint32_t idx = 0;
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for(idx =0; idx < 100; idx++)
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{
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*(output_data_ptr + idx) = cur_sfn * 100000 + cur_slot * 100 + idx;
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}
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uint32_t output_data_ptr_ddr_even = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;// 最终输出数据地址(ddr)
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uint32_t output_data_ptr_ddr_odd = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR ;// 最终输出数据地址(ddr)
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// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr),
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// output_data_ptr_ddr_even,
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// temp_len_32,
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// DMA_TAG_L2G,
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// 1);
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//LOG_ERROR_S("ddr_even:%08x, ddr_odd:%08x\n", output_data_ptr_ddr_even, output_data_ptr_ddr_odd);
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TRACE(TRACE_TESTTASK_ADDR, 3, 3);
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uint32_t temp_len_32 = 7168;
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if(cur_slot % 2 == 1){
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ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(output_data_ptr),
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output_data_ptr_ddr_even,
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temp_len_32,
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DMA_TAG_L2G,
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1);
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}else{
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ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(output_data_ptr),
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output_data_ptr_ddr_odd,
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temp_len_32,
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DMA_TAG_L2G,
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1);
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}
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dfree_unit(transmitter_malloc_dm0_ptr, APE_DM0);
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TRACE(TRACE_TESTTASK_ADDR, 3, 4);
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RUN_CNT(TRACE_TESTTASK_ADDR, 1);
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TRACE_MAX(TRACE_TESTTASK_ADDR, 2, Time_offset(0) );
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}
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@ -64,6 +64,7 @@ void Phy_Task_Ape7_Reg()
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test_case_cfgpar_pcie();
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osp_task_create(&pcie_normal_task_info);
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osp_task_create(&mgr_task);
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//osp_timer_sync(1);
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LOG_INFO_S("APE7 finish task create!\n");
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@ -27,7 +27,6 @@
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#include "msg_transfer_mem.h"
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#include "msg_transfer_mbuffer.h"
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//lxh 202501
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#include "mem_sections.h"
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#include "drv_ape.h"
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#include "trace.h"
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@ -35,12 +34,19 @@
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#include "Fucp_Ape7_pcie_testcase.h"
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#include "mem_def.h"
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#include "interface_rec_sync2_rec_sync_first.h"
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#include "log_interface.h"
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#include "transform_para_func.h"
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uint32_t g_thita1=0;
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uint32_t g_thita2=0;
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uint32_t g_thita34=0;
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static int g_msg_count=0;
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static int g_send_msg_flag=1;//0-停止给3588发送数据;1-启动给3588发数据
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uint32_t pcie_rx_callback_data(const char* buf,uint32_t payloadSize)
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{
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uint32_t ret = -1;
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TRACE(TRACE_PCIE_ADDR, 15, g_msg_count);
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char tmplogbuf[1024] = {0};
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debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701090);
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if(payloadSize < 1024)
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@ -52,7 +58,31 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701090);
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memcpy_ucp(tmplogbuf, buf, 1024);
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}
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uint32_t *data_tmp=(uint32_t *)tmplogbuf;
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g_thita1=data_tmp[0];
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g_thita2=data_tmp[1];
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g_thita34=data_tmp[2];
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//UCP_PRINT_LOG("received buf : %s\n", tmplogbuf);
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LOG_INFO_S("received buf : [0x%08x][0x%08x][0x%08x]\n", g_thita1,g_thita2,g_thita34);
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transform_decode_para(g_thita1, g_thita2, g_thita34);
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uint32_t temp1 = g_thita1_val;
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uint32_t temp2 = g_thita2_val;
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uint32_t temp3 = g_thita34_val;
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ret = transform_decode_para_check(g_thita1, g_thita2, g_thita34);
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if(0 == ret)
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{
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receiver_pcie2sync_t* pcie2sync = (receiver_pcie2sync_t*)TRANSFORM_REF_PARA_PCIE2SYNC_ADDR;//存储在DDR
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STORE_EX_W(&(pcie2sync->thita1_val) , temp1);
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STORE_EX_W(&(pcie2sync->thita2_val) , temp2);
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STORE_EX_W(&(pcie2sync->thita34_val) , temp3);
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STORE_EX_W(&(pcie2sync->status) , 1); // 0: not ready 1: wait APE4 read 2:APE4 read & done
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}
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g_msg_count=0;//为下一次向3588送数初始化
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return payloadSize;
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}
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@ -60,7 +90,7 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701090);
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uint32_t pcie_rx_callback_ctrl(const char* buf,uint32_t payloadSize)
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{
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char tmplogbuf[1024] = {0};
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debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701070);
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if(payloadSize < 1024)
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{
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memcpy_ucp(tmplogbuf, buf, payloadSize);
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@ -78,7 +108,7 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701070);
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uint32_t pcie_rx_callback_oam(const char* buf,uint32_t payloadSize)
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{
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char tmplogbuf[1024] = {0};
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debug_write(DBG_DDR_COMMON_IDX(get_core_id(),19), 0x70701080);
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if(payloadSize < 1024)
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{
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memcpy_ucp(tmplogbuf, buf, payloadSize);
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@ -134,7 +164,7 @@ int8_t get_id(uint16_t type_id, uint16_t cu_flag)
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//static uint32_t count = 0;
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void test_case_sendmsg_pcie()
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void test_case_sendmsg_pcie(uint32_t sfn ,uint32_t slot ,uint32_t data_addr ,uint32_t data_len )
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{
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uint32_t size = 512-16;
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char* buf = NULL;
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@ -150,7 +180,7 @@ void test_case_sendmsg_pcie()
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uint32_t offset = 0;
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uint32_t i = 0;
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char templogbuf[600] = {0};
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char templogbuf[256] = {0};
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int8_t que_id = 0;
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MsgQueueLocalMgt_t* pMsgQueueLocalMgt = get_msg_queue_local_mgt();
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@ -158,10 +188,7 @@ void test_case_sendmsg_pcie()
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//uint32_t core_id = get_core_id();
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//uint32_t bufsize = ch->bufSize - MSG_MBUF_HEAD_SIZE;
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//lxh 202501
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uint32_t tempdatabuf[65]={0};
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uint32_t srcAddr = 0;
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uint32_t dstAddr = 0;
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|
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/****************************test code************************************************/
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#ifdef PCIE_WITH_JESD
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debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
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@ -180,6 +207,7 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
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ret = msg_transfer_send_start(handler.value);
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/************C_PLANE***************/
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#if 0
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cu_flag = C_PLANE;
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que_id = get_id(handler.type_id, cu_flag);
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ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[i][que_id];
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@ -209,12 +237,13 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
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{
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//com_debug_log("ul msg_transfer_send_msg CU_SPLIT ctrl failed! ret = %d inst_id=%d\n", ret, handler.inst_id);
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}
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#endif
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/************U_PLANE***************/
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cu_flag = U_PLANE;
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que_id = get_id(handler.type_id, cu_flag);
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ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[i][que_id];
|
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size = ch->bufSize-MSG_MBUF_HEAD_SIZE;
|
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debug_write(DBG_DDR_COMMON_IDX(get_core_id(),4), size);
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ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
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//com_debug_log("alloc data msg ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, (uint64_t)ch, ch->bufSize);
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|
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@ -225,8 +254,8 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
|
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//size = availableSize;
|
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//buf = *bufAddr;
|
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UCP_PRINT_LOG("msg transfer alloced ul U_PLANE msg buf = 0x%x!\n", buf);
|
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memset(templogbuf, 0x00, sizeof(templogbuf));
|
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#if 1 //用于测试
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||||
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#if 0 //用于测试
|
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sprintf(templogbuf, "%s", "this is test for ul CU_SPLIT data transfer!\n");
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memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
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#endif
|
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@ -237,36 +266,22 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
|
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*(uint32_t*)(buf + 8) = 0x12345678;
|
||||
*(uint32_t*)(buf + 12) = 0xa5a5a5a5; */
|
||||
#if 1 //testNPU
|
||||
srcAddr = RSV_BASE_ADDR;
|
||||
dstAddr = (uint32_t)(&tempdatabuf[0]);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, 260, 0, 1);
|
||||
|
||||
uint32_t n;
|
||||
uint32_t theData;
|
||||
for (n=0;n<63;n++){
|
||||
char bufData[9]={};
|
||||
theData=tempdatabuf[n+1];
|
||||
snprintf(bufData,sizeof(bufData),"%08x",theData);
|
||||
strcat(templogbuf,(char *)bufData);
|
||||
strcat(templogbuf,",");
|
||||
}
|
||||
char bufData[9]={};
|
||||
theData=tempdatabuf[64];//最后一个单独处理
|
||||
snprintf(bufData,sizeof(bufData),"%08x",theData);
|
||||
strcat(templogbuf,(char *)bufData);
|
||||
strcat(templogbuf,"\n");
|
||||
memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
|
||||
*(uint32_t*)(buf + 0) = sfn;
|
||||
*(uint32_t*)(buf + 4) = slot;
|
||||
memcpy_ucp(buf + 8, data_addr, data_len);
|
||||
|
||||
/* debug_write(DBG_DDR_COMMON_IDX(get_core_id(),5), 0x70701010);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),6), sfn);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),7), slot);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),8), *(uint32_t *)(buf+0));
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),9), *(uint32_t *)(buf+4));
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),10), *(uint32_t *)(buf+0));
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),11), *(uint32_t *)(buf+4));
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),12), *(uint32_t *)(data_addr+0));
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),13), *(uint32_t *)(data_addr+4));
|
||||
*/
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),5), 0x70701010);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),6), templogbuf[8]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),7), templogbuf[9]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),8), templogbuf[10]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),9), templogbuf[11]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),10), templogbuf[12]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),11), templogbuf[13]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),12), templogbuf[14]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),13), templogbuf[15]);
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),14), templogbuf[16]);
|
||||
#endif
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
if(ret != SUCCESS)
|
||||
@ -281,7 +296,7 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
|
||||
}
|
||||
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),16), 0x70701030);
|
||||
}
|
||||
|
||||
#if 0
|
||||
handler.type_id = OAM;
|
||||
if(1 == slot_ind_flag)
|
||||
{
|
||||
@ -328,6 +343,7 @@ debug_write(DBG_DDR_COMMON_IDX(get_core_id(),18), 0x70701051);
|
||||
//com_debug_log("ul msg_transfer_send_end CU_SPLIT oam failed! ret = %d inst_id = %d\n", ret, handler.inst_id);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*********************************************************************************/
|
||||
|
||||
@ -476,21 +492,24 @@ void test_speed_recv_msg_pcie()
|
||||
/*********************************************************************************/
|
||||
}
|
||||
|
||||
|
||||
void pcie_test_task_init()
|
||||
{
|
||||
transform_para_init(0, 0, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void pcie_test_task_func(receiver_sync2pcie_t* msg_ptr, uint32_t msg_len)
|
||||
{
|
||||
|
||||
RUN_CNT(TRACE_PCIE_ADDR, 0);
|
||||
TRACE(TRACE_PCIE_ADDR, 3, 1);
|
||||
g_time_start[1] = TIME_NS();
|
||||
//获取状态机状态
|
||||
receiver_sync_status_t* status_SM_addr= (uint32_t)RECEIVER_SYNC2SYNC_FIRST_INF_ADDR;
|
||||
volatile uint32_t sync_status = LOAD_EX_W(&(status_SM_addr->sync_status));
|
||||
TRACE(TRACE_PCIE_ADDR, 4, status_SM_addr);
|
||||
TRACE(TRACE_PCIE_ADDR, 5, sync_status);
|
||||
|
||||
/*typedef enum
|
||||
{
|
||||
SYNC_IDLE=0,
|
||||
@ -498,54 +517,45 @@ void pcie_test_task_func(receiver_sync2pcie_t* msg_ptr, uint32_t msg_len)
|
||||
SYNC_AI_PROCECING,
|
||||
SYNC_TRACKING
|
||||
}receiver_sync_status_e;*/
|
||||
if(2 != LOAD_EX_W(&(status_SM_addr->sync_status)))
|
||||
if(2 != sync_status){
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
//提供的数据地址(DDR)和本次数据的SFN SLOT号
|
||||
uint32_t sfn = msg_ptr->sfn;
|
||||
uint32_t slot = msg_ptr->slot;
|
||||
uint32_t data_addr = msg_ptr->data_section0_ptr;
|
||||
uint32_t sfn = LOAD_EX_S(&msg_ptr->sfn) ;
|
||||
uint32_t slot = LOAD_EX_S(&msg_ptr->slot);
|
||||
uint32_t data_addr = LOAD_EX_W(&msg_ptr->data_section0_ptr);
|
||||
uint32_t data_len = 1024*4;
|
||||
|
||||
|
||||
TRACE(TRACE_PCIE_ADDR, 6, sfn);
|
||||
TRACE(TRACE_PCIE_ADDR, 7, slot);
|
||||
TRACE(TRACE_PCIE_ADDR, 8, data_addr);
|
||||
TRACE(TRACE_PCIE_ADDR, 9, *(uint32_t *)data_addr);
|
||||
//return ;
|
||||
|
||||
|
||||
// //uint32_t clockTick = 0;
|
||||
// // uint32_t clockOffset = 0;
|
||||
// TRACE(TRACE_PCIE_ADDR, 3, 1);
|
||||
// test_case_sendmsg_pcie();
|
||||
// TRACE(TRACE_PCIE_ADDR, 3, 2);
|
||||
// #ifdef PCIE_WITH_JESD
|
||||
//uint32_t clockTick = 0;
|
||||
// uint32_t clockOffset = 0;
|
||||
|
||||
// #endif
|
||||
// test_speed_recv_msg_pcie();
|
||||
// debug_write(DBG_DDR_COMMON_IDX(get_core_id(),17), 0x70701040);
|
||||
// //delay_us(50);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//TODO:接收到RK3588的数据后,必须更新状态机后级模块才能工作
|
||||
//WARNING:需要使用这个代码
|
||||
#if 1
|
||||
uint32_t ref_sfn = 0, ref_slot = 0;//PCIE解算存下来的时序值
|
||||
uint32_t bit9 = 0, bit11 = 0, bit13 = 0;
|
||||
transform_decode_para(bit9, bit11, bit13);
|
||||
//置为1以后,APE4改变状态时会重置状态值,
|
||||
if(g_msg_count==0)
|
||||
{ //状态机中存储第一组数据发送时的sfn和slot用于后面计算
|
||||
receiver_pcie2sync_t* pcie2sync = (receiver_pcie2sync_t*)TRANSFORM_REF_PARA_PCIE2SYNC_ADDR;//存储在DDR
|
||||
STORE_EX_W(&(pcie2sync->ref_sfn) , ref_sfn);
|
||||
STORE_EX_W(&(pcie2sync->ref_slot) , ref_slot);
|
||||
STORE_EX_W(&(pcie2sync->thita1_val) , g_thita1_val);
|
||||
STORE_EX_W(&(pcie2sync->thita2_val) , g_thita2_val);
|
||||
STORE_EX_W(&(pcie2sync->thita34_val) , g_thita34_val);
|
||||
STORE_EX_W(&(pcie2sync->status) , 1); // 0: not ready 1: wait APE4 read 2:APE4 read & done
|
||||
STORE_EX_W(&(pcie2sync->ref_sfn) , sfn);
|
||||
STORE_EX_W(&(pcie2sync->ref_slot) , slot);
|
||||
}
|
||||
|
||||
STORE_EX_W(&(status_SM_addr->sync_status) , 3);
|
||||
__ucps2_synch(0);
|
||||
//一次处理只送8组数据
|
||||
// if(g_msg_count < 8)
|
||||
// {
|
||||
test_case_sendmsg_pcie(sfn,slot,data_addr,data_len);
|
||||
// }
|
||||
g_msg_count++;
|
||||
TRACE(TRACE_PCIE_ADDR, 13, g_msg_count);
|
||||
|
||||
TRACE(TRACE_PCIE_ADDR, 3, 2);
|
||||
|
||||
#endif
|
||||
test_speed_recv_msg_pcie();
|
||||
//delay_us(50);
|
||||
|
||||
TRACE(TRACE_PCIE_ADDR, 3, 0xffff);
|
||||
RUN_CNT(TRACE_PCIE_ADDR, 1);
|
||||
|
@ -27,6 +27,7 @@
|
||||
#include "ByteCopy.h"
|
||||
#include "ByteShift.h"
|
||||
#include "LdpcDecBG1AllZc.h"
|
||||
#include "interface_rec_symb2_rec_bit.h"
|
||||
|
||||
|
||||
//微码配置空间偏移结构体
|
||||
@ -39,6 +40,7 @@ extern uint32_t *receiver_bit_config_dm3_ptr;
|
||||
void Receiver_Bit_Init();
|
||||
void Receiver_Bit_Task(void* msg_ptr, uint32_t msg_len);
|
||||
void Receiver_Bit_Proc(
|
||||
receiver_symb2bit_t* symb2bit_info,
|
||||
uint32_t* param_ptr,
|
||||
int32_t* temp_dm0_ptr,
|
||||
int32_t* temp_dm1_ptr,
|
||||
|
@ -62,30 +62,30 @@ void Receiver_Bit_Init()
|
||||
ret = osp_get_cfgfile("Receiver_Bit_cfg_dm0.dat",
|
||||
(uint32_t *)&(g_receiver_bit_table_param.receiver_bit_config0_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_bit_table_param.receiver_bit_config0_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Bit_cfg_dm0.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Bit_cfg_dm0.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Bit_cfg_dm1.dat",
|
||||
(uint32_t *)&(g_receiver_bit_table_param.receiver_bit_config1_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_bit_table_param.receiver_bit_config1_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Bit_cfg_dm1.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Bit_cfg_dm1.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Bit_cfg_dm2.dat",
|
||||
(uint32_t *)&(g_receiver_bit_table_param.receiver_bit_config2_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_bit_table_param.receiver_bit_config2_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Bit_cfg_dm2.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Bit_cfg_dm2.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Bit_cfg_dm3.dat",
|
||||
(uint32_t *)&(g_receiver_bit_table_param.receiver_bit_config3_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_bit_table_param.receiver_bit_config3_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Bit_cfg_dm3.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Bit_cfg_dm3.dat not found!\n");
|
||||
}
|
||||
//10.输入测试数据
|
||||
uint32_t timedata_ptr;
|
||||
@ -93,18 +93,18 @@ void Receiver_Bit_Init()
|
||||
ret = osp_get_cfgfile("timedata.dat",
|
||||
(uint32_t *)&(timedata_ptr),
|
||||
(int32_t *)&(timedata_len));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("timedata.dat not found!\n");
|
||||
//LOG_ERROR_S("timedata.dat not found!\n");
|
||||
}
|
||||
uint32_t gain_mmse_test_ptr;
|
||||
int32_t gain_mmse_test_len;
|
||||
ret = osp_get_cfgfile("gain_test.dat",
|
||||
(uint32_t *)&(gain_mmse_test_ptr),
|
||||
(int32_t *)&(gain_mmse_test_len));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("gain_test.dat not found!\n");
|
||||
//LOG_ERROR_S("gain_test.dat not found!\n");
|
||||
}
|
||||
int* param_ptr = (int *)RECEIVER_BIT_CFG_BASE;
|
||||
STORE_EX_W(param_ptr, timedata_ptr);
|
||||
|
@ -16,6 +16,7 @@
|
||||
* @Date: 2024年10月30日
|
||||
*/
|
||||
void Receiver_Bit_Proc(
|
||||
receiver_symb2bit_t* symb2bit_info,
|
||||
uint32_t *param_ptr,
|
||||
int32_t *temp_dm0_ptr,
|
||||
int32_t *temp_dm1_ptr,
|
||||
@ -35,8 +36,9 @@ void Receiver_Bit_Proc(
|
||||
uint32_t mpu_temp_dm3_ptr;
|
||||
uint32_t temp_u32;
|
||||
uint32_t time_data_dm0_ptr = ((((uint32_t)&temp_dm0_ptr[0] + 4095)>>12)<<12);
|
||||
uint32_t res_ptr = RECEIVER_OUT3;
|
||||
|
||||
uint32_t res_counter_ptr = RECV_BIT_OUT_DATA_FLAG_DDR_ADDR;
|
||||
uint32_t res_ptr = RECV_BIT_OUT_DATA_DDR_ADDR;;
|
||||
//LOG_ERROR_S("%d %d 0x%08x %d\n", symb2bit_info->sfn, symb2bit_info->slot, symb2bit_info->data_ptr, symb2bit_info->proc_id);
|
||||
// 16QAM_LDPC-----------------------------------------------------------------------------------------------
|
||||
int i;
|
||||
int NumCB = 28;
|
||||
@ -64,11 +66,16 @@ void Receiver_Bit_Proc(
|
||||
// uint32_t LdpcOut = (uint32_t)(temp_dm1_ptr);
|
||||
uint32_t LdpcOut;
|
||||
|
||||
|
||||
static volatile unsigned char counter = 0;
|
||||
if (counter == 7) counter = 0;
|
||||
|
||||
int out_len = 4576 / 8;
|
||||
for (i=0; i<NumCB; i++){
|
||||
//TODO: test data ptr
|
||||
time_data_ddr_ptr = (uint32_t)*param_ptr + 4 * i * ReNum;//addr->4;(ReNum*4)byte/4=(ReNum)word
|
||||
//symb2bit data ptr
|
||||
//time_data_ddr_ptr = (uint32_t)(symb2bit_info->data_ptr + 4 * i * ReNum);
|
||||
|
||||
time_data_length = (uint32_t)*(param_ptr + 1) / NumCB;
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
|
||||
(uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
|
||||
@ -135,50 +142,23 @@ void Receiver_Bit_Proc(
|
||||
MPU_ADDR(time_data_dm0_ptr));
|
||||
SVRReg[0] = MPU_ADDR(cfg_addr);
|
||||
LdpcDecBG1AllZcAsm(SVRReg);
|
||||
// __ucps2_getStatB();
|
||||
// __ucps2_delay();
|
||||
// unsigned int ACK = __ucps2_getKI(5);
|
||||
// unsigned int CYC = __ucps2_getKI(9);
|
||||
WAIT_MPU_STOP;
|
||||
|
||||
LdpcOut = res_ptr + out_len * i;
|
||||
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(LdpcOut),
|
||||
LdpcOut = res_ptr + counter * NumCB * out_len + i * out_len;
|
||||
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)time_data_dm0_ptr),
|
||||
// (uint64_t)res_ptr,
|
||||
(uint64_t)LdpcOut,
|
||||
out_len,
|
||||
// 2048,
|
||||
DMA_TAG_L2G,
|
||||
1);
|
||||
ape_csu_task_lookup(DMA_TAG_L2G, 1);
|
||||
};
|
||||
counter = counter + 1;
|
||||
STORE_EX_W(res_counter_ptr, counter);
|
||||
|
||||
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)receiver_bit_config_dm0_ptr),
|
||||
// (uint64_t)res_ptr,
|
||||
// 37568,
|
||||
// DMA_TAG_L2G,
|
||||
// 1);
|
||||
|
||||
//data读入
|
||||
//获取源数据地址
|
||||
// time_data_ddr_ptr = (uint32_t)*param_ptr;
|
||||
// time_data_length = (uint32_t)((*(param_ptr + 1) +7)>>3);//计算byte数
|
||||
// ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
|
||||
// ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
|
||||
// (uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
|
||||
// time_data_length,
|
||||
// DMA_TAG_G2L,
|
||||
// 0);
|
||||
|
||||
|
||||
|
||||
// //计算结果搬移到外存
|
||||
// temp_u32 = 1000;//计算byte数
|
||||
// WAIT_MPU_STOP;
|
||||
// ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
|
||||
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
|
||||
// (uint64_t)res_ptr,
|
||||
// temp_u32,
|
||||
// DMA_TAG_L2G,
|
||||
// 1);
|
||||
|
||||
return;
|
||||
}
|
||||
|
@ -24,7 +24,9 @@ void Receiver_Bit_Task(void* msg_ptr, uint32_t msg_len)
|
||||
g_time_start[0] = TIME_NS();
|
||||
RUN_CNT(TRACE_RECEIVER_BIT_ADDR, 0);
|
||||
|
||||
|
||||
receiver_symb2bit_t symb2bit_info;
|
||||
memcpy_ext(&symb2bit_info, msg_ptr, msg_len);
|
||||
//LOG_ERROR_S("0x%08x %d %d 0x%08x %d\n", msg_ptr, symb2bit_info.sfn, symb2bit_info.slot, symb2bit_info.data_ptr, symb2bit_info.proc_id);
|
||||
int32_t *receiver_bit_malloc_dm0_ptr;
|
||||
int32_t *receiver_bit_malloc_dm1_ptr;
|
||||
int32_t *receiver_bit_malloc_dm2_ptr;
|
||||
@ -154,6 +156,7 @@ void Receiver_Bit_Task(void* msg_ptr, uint32_t msg_len)
|
||||
|
||||
//6. 计算流程
|
||||
Receiver_Bit_Proc(
|
||||
&symb2bit_info,
|
||||
(uint32_t*)receiver_bit_param_ptr,
|
||||
receiver_bit_temp_dm0_ptr,
|
||||
receiver_bit_temp_dm1_ptr,
|
||||
|
@ -25,6 +25,7 @@
|
||||
#include "freOffEstImpl.h"
|
||||
#include "freOffCompImpl.h"
|
||||
#include "Transform.h"
|
||||
#include "interface_rec_symb2_rec_bit.h"
|
||||
//include mpu header files
|
||||
|
||||
|
||||
|
@ -49,11 +49,6 @@ typedef struct receiver_symb_table_param_s
|
||||
|
||||
}receiver_symb_table_param_t;
|
||||
|
||||
//TODO:需要接口设计
|
||||
typedef struct receiver_symb2bit_s
|
||||
{
|
||||
uint8_t rev[4];
|
||||
}receiver_symb2bit_t;
|
||||
|
||||
//=======================================================================
|
||||
#endif
|
@ -10,7 +10,7 @@
|
||||
*****************************************************************/
|
||||
#include "receiver_symb_func.h"
|
||||
|
||||
|
||||
extern uint32_t g_symb2bit_buffer_sel;
|
||||
/*!
|
||||
* @brief: Receiver任务启动前的初始化工作
|
||||
* 初始化全局参数,ddr查找表搬入SM
|
||||
@ -32,36 +32,36 @@ void Receiver_Symb_Init()
|
||||
|
||||
//SM
|
||||
|
||||
|
||||
g_symb2bit_buffer_sel = 0;
|
||||
|
||||
//9. 微码配置文件ddr地址初始化
|
||||
ret = osp_get_cfgfile("Receiver_Symb_cfg_dm0.dat",
|
||||
(uint32_t *)&(g_receiver_symb_table_param.receiver_symb_config0_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_symb_table_param.receiver_symb_config0_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Symb_cfg_dm0.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Symb_cfg_dm0.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Symb_cfg_dm1.dat",
|
||||
(uint32_t *)&(g_receiver_symb_table_param.receiver_symb_config1_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_symb_table_param.receiver_symb_config1_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Symb_cfg_dm1.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Symb_cfg_dm1.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Symb_cfg_dm2.dat",
|
||||
(uint32_t *)&(g_receiver_symb_table_param.receiver_symb_config2_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_symb_table_param.receiver_symb_config2_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Symb_cfg_dm2.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Symb_cfg_dm2.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Receiver_Symb_cfg_dm3.dat",
|
||||
(uint32_t *)&(g_receiver_symb_table_param.receiver_symb_config3_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_symb_table_param.receiver_symb_config3_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Symb_cfg_dm3.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Symb_cfg_dm3.dat not found!\n");
|
||||
}
|
||||
|
||||
uint32_t timedata_ptr;
|
||||
@ -116,4 +116,6 @@ void Receiver_Symb_Init()
|
||||
len2,
|
||||
DMA_TAG_G2G,
|
||||
1);
|
||||
|
||||
|
||||
}
|
||||
|
@ -9,7 +9,8 @@
|
||||
|
||||
*****************************************************************/
|
||||
#include "receiver_symb_func.h"
|
||||
|
||||
uint32_t g_symb2bit_buffer_sel;
|
||||
receiver_symb2bit_t data_send2bit_task;
|
||||
/*!
|
||||
* @brief: Receiver_sync链路处理
|
||||
* @author: HUOHUO
|
||||
@ -37,12 +38,11 @@ void Receiver_Symb_Proc(
|
||||
//data读入
|
||||
//获取源数据地址
|
||||
receiver_sync2symb_t* para_dm_ptr = param_ptr;
|
||||
//TODO: 计算完成结果需要存到下面两个buffer地址中的一个
|
||||
uint32_t cur_out_ddr_ptr = (0 == g_symb2bit_buffer_sel) ? ((uint32_t)RECEIVER_SYMB2BIT_BUFFER0_ADDR) : ((uint32_t)RECEIVER_SYMB2BIT_BUFFER1_ADDR);
|
||||
|
||||
uint32_t cur_sfn = get_rx_nr_sfn();
|
||||
uint32_t cur_slot = get_rx_nr_slot();
|
||||
uint32_t cur_time = TIME_NS();
|
||||
LOG_ERROR_S("%d %d %d %d %d %d %d 0x%08x 0x%08x %d %d\n", cur_sfn, cur_slot, cur_time, para_dm_ptr->sfn, para_dm_ptr->slot, para_dm_ptr->num_data_section,
|
||||
para_dm_ptr->proc_id, para_dm_ptr->data_section0_ptr, para_dm_ptr->data_section1_ptr, para_dm_ptr->data_section0_length, para_dm_ptr->data_section1_length);
|
||||
//LOG_ERROR_S("%d %d %d %d 0x%08x 0x%08x %d %d\n",para_dm_ptr->sfn, para_dm_ptr->slot, para_dm_ptr->num_data_section,
|
||||
// para_dm_ptr->proc_id, para_dm_ptr->data_section0_ptr, para_dm_ptr->data_section1_ptr, para_dm_ptr->data_section0_length, para_dm_ptr->data_section1_length);
|
||||
|
||||
// if(1 == para_dm_ptr->num_data_section)
|
||||
// {
|
||||
@ -85,41 +85,55 @@ void Receiver_Symb_Proc(
|
||||
time0 = time1;
|
||||
|
||||
|
||||
ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr,temp_dm2_ptr,temp_dm3_ptr);
|
||||
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 4);
|
||||
time1 = Time_offset(0);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 6, time1 -time0);
|
||||
time0 = time1;
|
||||
// ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr,temp_dm2_ptr,temp_dm3_ptr);
|
||||
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 4);
|
||||
// time1 = Time_offset(0);
|
||||
// TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 6, time1 -time0);
|
||||
// time0 = time1;
|
||||
|
||||
ChannelEqu_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
|
||||
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 5);
|
||||
time1 = Time_offset(0);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 7, time1 -time0);
|
||||
time0 = time1;
|
||||
__ucps2_synch(0);
|
||||
__ucps2_synch(0);
|
||||
__ucps2_synch(0);
|
||||
__ucps2_synch(0);
|
||||
__ucps2_synch(0);
|
||||
__ucps2_dbgbreak();
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_dbgbreak();
|
||||
Transform_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
|
||||
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 6);
|
||||
time1 = Time_offset(0);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 8, time1 -time0);
|
||||
time0 = time1;
|
||||
|
||||
#ifdef IDE_TEST
|
||||
printf("DataTrans");
|
||||
#endif
|
||||
// #ifdef IDE_TEST
|
||||
// printf("DataTrans");
|
||||
// #endif
|
||||
//return ;
|
||||
|
||||
return ;
|
||||
//7.核间消息to APE2
|
||||
//需要定义结构体
|
||||
receiver_symb2bit_t data_send2bit_task;
|
||||
|
||||
//更新buffer
|
||||
g_symb2bit_buffer_sel = (g_symb2bit_buffer_sel + 1) & 0x1;
|
||||
|
||||
data_send2bit_task.proc_id = para_dm_ptr->proc_id;
|
||||
data_send2bit_task.sfn = para_dm_ptr->sfn;
|
||||
data_send2bit_task.slot = para_dm_ptr->slot;
|
||||
data_send2bit_task.data_ptr = cur_out_ddr_ptr;
|
||||
data_send2bit_task.data_length = 57344;//TODO:待确认,单位WORD
|
||||
//LOG_ERROR_S("%d 0x%08x %d\n",data_send2bit_task.proc_id, data_send2bit_task.data_ptr, g_symb2bit_buffer_sel);
|
||||
#ifdef CORE_ODD
|
||||
uint8_t cur_core_id = APE3_CORE_ID;
|
||||
#else
|
||||
uint8_t cur_core_id = APE5_CORE_ID;
|
||||
#endif
|
||||
phy_et_msg_send((uint32_t)(&data_send2bit_task),
|
||||
sizeof(receiver_symb2bit_t),
|
||||
UCP4008_KERNEL_INTER,
|
||||
APE5_CORE_ID,
|
||||
cur_core_id,
|
||||
APE6_CORE_ID,
|
||||
PHY_TASK_RECEIVER_SYMB,
|
||||
PHY_TASK_RECEIVER_BIT);
|
||||
|
@ -70,7 +70,16 @@ void Transform_Proc(
|
||||
2, //reggroup
|
||||
DMA_DIR_G2L);
|
||||
|
||||
Transform((int)Cfg_DeTransform2,MPU_ADDR(InputAddr_Trans),MPU_ADDR(TransTemp), 2, db_real*1.375, db_imag*1.375, -1);
|
||||
//TODO:待确认地址合理性,db_real指针指向DM空间,自动变量是IM, 后续可以查表节约时间 20250528
|
||||
double db_real_tmp[4];// = *db_real *1.375;
|
||||
double db_imag_tmp[4];// = *db_imag *1.375;
|
||||
uint32_t loop_idx;
|
||||
for (loop_idx = 0; loop_idx < 4; loop_idx++)
|
||||
{
|
||||
db_real_tmp[loop_idx] = *(db_real + loop_idx) * 1.375;
|
||||
db_imag_tmp[loop_idx] = *(db_imag + loop_idx) * 1.375;
|
||||
}
|
||||
Transform((int)Cfg_DeTransform2,MPU_ADDR(InputAddr_Trans),MPU_ADDR(TransTemp), 2, &db_real_tmp[0], &db_imag_tmp[0], -1);
|
||||
SVRReg[0] = MPU_ADDR(Cfg_DeTransform2);
|
||||
Transform2Asm(SVRReg);
|
||||
WAIT_MPU_STOP;
|
||||
|
@ -31,6 +31,7 @@
|
||||
//include mpu header files
|
||||
#include "ByteCopy.h"
|
||||
#include "SyncVer.h"
|
||||
#include "Sliding.h"
|
||||
|
||||
|
||||
//微码配置空间偏移结构体
|
||||
@ -60,6 +61,6 @@ void Receiver_Sync_Proc();
|
||||
void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type);
|
||||
|
||||
//debug
|
||||
extern uint32_t* last_mem_dm[8];
|
||||
extern int32_t* last_mem_dm[8];
|
||||
|
||||
#endif
|
||||
|
@ -15,9 +15,10 @@
|
||||
//=======================================================================
|
||||
//微码配置空间长度定义,单位为word(4Byte)
|
||||
#define RECEIVER_SYNC_ConfigByteCopy_CFG1_LENGTH (0x0030)
|
||||
#define RECEIVER_SYNC_ConfigSlidingCorrelation_CFG2_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_ConfigSlidingCorrelation_CFG2_LENGTH (0x00a0)
|
||||
#define RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH (0x00a0)
|
||||
#define RECEIVER_SYNC_ConfigSliding_CFG5_LENGTH (0x0060)
|
||||
|
||||
//SPU查找表各字段长度定义,单位为word(4Byte)
|
||||
|
||||
|
@ -25,6 +25,7 @@ typedef struct receiver_sync_table_param_s
|
||||
uint32_t ConfigSlidingCorrelation_CFG2_Offset;
|
||||
uint32_t ConfigSlidingCorrelationSecond_CFG3_Offset;
|
||||
uint32_t ConfigSyncVer_CFG4_Offset;
|
||||
uint32_t ConfigSliding_CFG5_Offset;
|
||||
// 存储微码参数表的ddr基地址和长度
|
||||
uint32_t receiver_sync_config0_ddr_ptr;//receiver DM0微码配置文件ddr地址
|
||||
uint32_t receiver_sync_config0_length;//receiver DM0微码配置文件ddr长度
|
||||
@ -39,7 +40,8 @@ typedef struct receiver_sync_table_param_s
|
||||
|
||||
|
||||
// SPU LUT SM基地址和长度
|
||||
|
||||
uint32_t receiver_sync_pilot_ptr;//receiver DM0微码配置文件ddr地址
|
||||
uint32_t receiver_sync_pilot_length;//receiver DM0微码配置文件ddr长度
|
||||
|
||||
}receiver_sync_table_param_t;
|
||||
|
||||
|
@ -2,5 +2,16 @@
|
||||
#define RECEIVER_SYNC_VARS_H
|
||||
|
||||
#define RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER (6)
|
||||
typedef struct receiver_sync_cylic_buffer_s
|
||||
{
|
||||
int32_t buffer_head;
|
||||
int32_t buffer_tail;
|
||||
int32_t buffer_max;
|
||||
int32_t buffer_min;
|
||||
uint32_t* buffer_ptr;
|
||||
uint32_t buffer_in_sel;
|
||||
uint32_t buffer_out_sel;
|
||||
}receiver_sync_cylic_buffer_t;
|
||||
|
||||
extern receiver_sync_cylic_buffer_t g_receiver_sync_cylic_buffer;
|
||||
#endif
|
@ -20,6 +20,7 @@
|
||||
*/
|
||||
void Receiver_Sync_Init()
|
||||
{
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 1);
|
||||
int32_t ret;
|
||||
|
||||
//DM0
|
||||
@ -27,6 +28,7 @@ void Receiver_Sync_Init()
|
||||
g_receiver_sync_table_param.ConfigSlidingCorrelation_CFG2_Offset = g_receiver_sync_table_param.ConfigByteCopy_CFG1_Offset + RECEIVER_SYNC_ConfigByteCopy_CFG1_LENGTH;
|
||||
g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelation_CFG2_Offset + RECEIVER_SYNC_ConfigSlidingCorrelation_CFG2_LENGTH;
|
||||
g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset + RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH;
|
||||
g_receiver_sync_table_param.ConfigSliding_CFG5_Offset = g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset + RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH;
|
||||
//DM1
|
||||
|
||||
//DM2
|
||||
@ -57,10 +59,19 @@ void Receiver_Sync_Init()
|
||||
ret = osp_get_cfgfile("Receiver_Sync_cfg_dm0.dat",
|
||||
(uint32_t *)&(g_receiver_sync_table_param.receiver_sync_config0_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_sync_table_param.receiver_sync_config0_length));
|
||||
|
||||
if(-1 == ret)
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 2);
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Sync_cfg_dm0.dat not found!\n");
|
||||
//LOG_ERROR_S("Receiver_Sync_cfg_dm0.dat not found!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("Recv_Pilot.dat",
|
||||
(uint32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_ptr),
|
||||
(int32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_length));
|
||||
//LOG_ERROR_S("Recv_Pilot.dat %d %d %d\n", g_receiver_sync_table_param.receiver_sync_pilot_ptr, g_receiver_sync_table_param.receiver_sync_pilot_length, ret);
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 3);
|
||||
if(0 != ret)
|
||||
{
|
||||
//LOG_ERROR_S("Recv_Pilot.dat not found!\n");
|
||||
}
|
||||
// ret = osp_get_cfgfile("Receiver_Sync_cfg_dm1.dat",
|
||||
// (uint32_t *)&(g_receiver_sync_table_param.receiver_sync_config1_ddr_ptr),
|
||||
@ -78,10 +89,17 @@ void Receiver_Sync_Init()
|
||||
g_receiver_sync_status_SM_ptr = (uint32_t)RECEIVER_SYNC2SYNC_FIRST_INF_ADDR;
|
||||
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status, SYNC_IDLE);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset, -1);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len, 0);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset, 0);
|
||||
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 4);
|
||||
g_receiver_sync_cylic_buffer.buffer_head = 0;
|
||||
g_receiver_sync_cylic_buffer.buffer_tail = 0;
|
||||
g_receiver_sync_cylic_buffer.buffer_min = 0;
|
||||
g_receiver_sync_cylic_buffer.buffer_max = 61440*RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER;
|
||||
g_receiver_sync_cylic_buffer.buffer_ptr = RECEIVER_SYNC2SYMB_BUFFER0_ADDR;
|
||||
g_receiver_sync_cylic_buffer.buffer_in_sel = 0;
|
||||
g_receiver_sync_cylic_buffer.buffer_out_sel = 0;
|
||||
|
||||
//sync2symb buffer地址初始化
|
||||
sync2symb_data_buffer[0] = RECEIVER_SYNC2SYMB_BUFFER0_ADDR;
|
||||
sync2symb_data_buffer[1] = RECEIVER_SYNC2SYMB_BUFFER1_ADDR;
|
||||
@ -92,33 +110,75 @@ void Receiver_Sync_Init()
|
||||
g_proc_id = 0;
|
||||
|
||||
#ifdef RECV_DBG_DATA_TEST
|
||||
uint32_t dbg_addr,dbg_len;
|
||||
ret = osp_get_cfgfile("timedatasym.dat", //timedatasym.dat frame_0x610e0000_245760.dat
|
||||
(uint32_t *)&(dbg_addr),
|
||||
(int32_t *)&(dbg_len));
|
||||
//uint32_t dbg_addr,dbg_len;
|
||||
// ret = osp_get_cfgfile("timedatasym.dat", //timedatasym.dat frame_0x610e0000_245760.dat
|
||||
// (uint32_t *)&(dbg_addr),
|
||||
// (int32_t *)&(dbg_len));
|
||||
|
||||
if(-1 == ret)
|
||||
// if(0 != ret)
|
||||
// {
|
||||
// //LOG_ERROR_S("frame_0x610e0000_245760.dat not found!\n");
|
||||
// LOG_ERROR_S("timedatasym.dat not found!\n");
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr,dbg_len);
|
||||
|
||||
// ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
|
||||
// (uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0
|
||||
// dbg_len,
|
||||
// DMA_TAG_G2G,
|
||||
// 1);
|
||||
// ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
|
||||
// (uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0
|
||||
// dbg_len,
|
||||
// DMA_TAG_G2G,
|
||||
// 1);
|
||||
// }
|
||||
uint32_t dbg_addr0,dbg_len0,dbg_addr1,dbg_len1;
|
||||
ret = osp_get_cfgfile("even.dat",
|
||||
(uint32_t *)&(dbg_addr0),
|
||||
(int32_t *)&(dbg_len0));
|
||||
|
||||
if(0 != ret)
|
||||
{
|
||||
//LOG_ERROR_S("frame_0x610e0000_245760.dat not found!\n");
|
||||
LOG_ERROR_S("timedatasym.dat not found!\n");
|
||||
//LOG_ERROR_S("even.dat not found!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr,dbg_len);
|
||||
//LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr0,dbg_len0);
|
||||
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr0),
|
||||
(uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0
|
||||
dbg_len,
|
||||
dbg_len0,
|
||||
DMA_TAG_G2G,
|
||||
1);
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
|
||||
|
||||
}
|
||||
TRACE(TRACE_RECEIVER_SYNC_ADDR, 8, 1);
|
||||
ret = osp_get_cfgfile("odd.dat",
|
||||
(uint32_t *)&(dbg_addr1),
|
||||
(int32_t *)&(dbg_len1));
|
||||
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("odd.dat not found!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr1,dbg_len1);
|
||||
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr1),
|
||||
(uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0
|
||||
dbg_len,
|
||||
dbg_len1,
|
||||
DMA_TAG_G2G,
|
||||
1);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 5);
|
||||
transform_para_init(0, 0, 0);
|
||||
TRACE(TRACE_RECV_INIT_ADDR, 6, 6);
|
||||
|
||||
}
|
||||
|
@ -10,6 +10,8 @@
|
||||
*****************************************************************/
|
||||
#include "receiver_sync_func.h"
|
||||
#define ADDR_ALIGN(addr, val) ((((uint32_t)(addr) + (2<<(val)) - 1)>>(val))<<(val))
|
||||
#define CALC_BUFFER_INTERVAL(val1, val2) ((val1 > val2) ? (val2 + g_receiver_sync_cylic_buffer.buffer_max - val1) : (val2 - val1) )
|
||||
#define HEAD_OFFSET 15
|
||||
|
||||
void dm_check(uint32_t mark)
|
||||
{
|
||||
@ -73,6 +75,7 @@ void Receiver_Sync_Memory_Alloc( )
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
|
||||
|
||||
//DM0第二段,堆空间
|
||||
receiver_sync_temp_dm0_ptr = (int32_t *)ADDR_ALIGN(receiver_sync_config_dm0_ptr + \
|
||||
(g_receiver_sync_table_param.receiver_sync_config0_length>>2), 2); //起始地址4byte对齐
|
||||
@ -161,6 +164,8 @@ void Receiver_Sync_Memory_Free( )
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* @brief: Receiver_sync链路处理
|
||||
* @author: HUOHUO
|
||||
@ -177,6 +182,7 @@ void Receiver_Sync_Proc(
|
||||
uint32_t cur_sfn = get_rx_nr_sfn();
|
||||
uint32_t cur_slot = get_rx_nr_slot();
|
||||
volatile sync_status = LOAD_EX_W(&(g_receiver_sync_status_SM_ptr->sync_status));
|
||||
TRACE(TRACE_RECEIVER_SYNC_ADDR, 12, sync_status);
|
||||
|
||||
if(SYNC_FIRST_RUNING == sync_status)
|
||||
{
|
||||
@ -196,14 +202,6 @@ void Receiver_Sync_Proc(
|
||||
receiver_sync2first_sync_t temp_msg;
|
||||
temp_msg.sfn = cur_sfn;
|
||||
temp_msg.slot = cur_slot;
|
||||
|
||||
// phy_et_msg_send((uint32_t)(&temp_msg),
|
||||
// sizeof(receiver_sync2first_sync_t),
|
||||
// UCP4008_KERNEL_INTER,
|
||||
// APE4_CORE_ID,
|
||||
// APE6_CORE_ID,
|
||||
// PHY_TASK_RECEIVER_SYNC,
|
||||
// PHY_TASK_RECEIVER_BIT);
|
||||
phy_et_msg_send((uint32_t)(&temp_msg),
|
||||
sizeof(receiver_sync2first_sync_t),
|
||||
UCP4008_KERNEL_INNER,
|
||||
@ -228,6 +226,7 @@ void Receiver_Sync_Proc(
|
||||
TRACE(TRACE_RECEIVER_SYNC_ADDR, 3, 5);
|
||||
receiver_pcie2sync_t* pcie2sync = (receiver_pcie2sync_t*)TRANSFORM_REF_PARA_PCIE2SYNC_ADDR;//存储在DDR
|
||||
volatile uint32_t transform_para_status = LOAD_EX_W(&(pcie2sync->status));
|
||||
TRACE(TRACE_RECEIVER_SYNC_ADDR, 12, LOAD_EX_W(&(pcie2sync->status)));
|
||||
if(1 == transform_para_status)
|
||||
{
|
||||
g_thita1_val = LOAD_EX_W(&(pcie2sync->thita1_val));
|
||||
@ -240,6 +239,9 @@ void Receiver_Sync_Proc(
|
||||
//同步transform参数后,置位状态位2,表示APE4完成了本次同步,等待下一次被置1
|
||||
STORE_EX_W(&(pcie2sync->status) , 2); // 0: not ready 1: wait APE4 read 2:APE4 read & done
|
||||
__ucps2_synch(0);
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_ADDR, 13, LOAD_EX_W(&(pcie2sync->status)));
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_FIRST_RUNING);
|
||||
}
|
||||
|
||||
Receiver_Fine_Sync_Proc(cur_sfn, cur_slot, sync_status);
|
||||
@ -269,17 +271,13 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
|
||||
uint32_t ret;
|
||||
int32_t *cfg_addr;// 配置地址指针
|
||||
uint32_t time0 = g_time_start;
|
||||
volatile uint32_t time1 = time0;
|
||||
uint32_t time0 = g_time_start[2];
|
||||
volatile uint32_t time1 = Time_offset(2);
|
||||
uint32_t task_idx = 0;
|
||||
volatile uint32_t frame_head_offset;
|
||||
volatile int32_t frame_head_offset;
|
||||
uint32_t src_addr0;
|
||||
uint32_t src_addr1;
|
||||
|
||||
//用于指示循环buffer空口数据的存储头
|
||||
uint32_t buffer_sel = (slot + RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER -1) % RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER;
|
||||
uint32_t buffer_sel2 = (buffer_sel + 1) % RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER;
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 1);
|
||||
//Proc的DM空间申请
|
||||
|
||||
@ -305,71 +303,88 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
#endif
|
||||
|
||||
ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
//取数方式,同步点为中心,前16,后15,相关长度1024
|
||||
frame_head_offset = LOAD_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset);
|
||||
LOG_ERROR_S("frame_head_offset=%d\n", frame_head_offset );
|
||||
|
||||
if(16 > frame_head_offset)
|
||||
frame_head_offset = LOAD_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset);
|
||||
|
||||
//取数方式,同步点为中心,前15,后16,相关长度1024
|
||||
/*
|
||||
| receiver_sync_temp_dm0_ptr |
|
||||
| |
|
||||
| |
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
| 15 | 1024 - 15 | 15 | 16 | 1024 - 16 | 16 |
|
||||
| | | | | | |
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
|
|
||||
HEAD
|
||||
|
||||
|
||||
*/
|
||||
#define TOT_LEN (2079)
|
||||
#define FRONT_LEN (15)
|
||||
|
||||
|
||||
if(15 > frame_head_offset)
|
||||
{
|
||||
//当前buffer头
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr + (16 - frame_head_offset) ),
|
||||
(1055 - (16 - frame_head_offset) )<<2,
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr + (FRONT_LEN - frame_head_offset) ),
|
||||
(TOT_LEN - (FRONT_LEN - frame_head_offset) )<<2,
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
//上个buffer尾
|
||||
memcpy_ext(receiver_sync_temp_dm0_ptr, src_addr1 + ((61440 - (16 - frame_head_offset) ) <<2), (16 - frame_head_offset)<<2 );
|
||||
memcpy_ext(receiver_sync_temp_dm0_ptr, src_addr1 + ((61440 - (FRONT_LEN - frame_head_offset) ) <<2), (FRONT_LEN - frame_head_offset)<<2 );
|
||||
|
||||
|
||||
// LOG_ERROR_S("csu1:%d %d\n", (16 - frame_head_offset)<<2 , (1055 - (16 - frame_head_offset) )<<2 );
|
||||
// LOG_ERROR_S("csu1:%d %d\n", (FRONT_LEN - frame_head_offset)<<2 , (2079 - (FRONT_LEN - frame_head_offset) )<<2 );
|
||||
}
|
||||
else if(61440 - (15 + 1024) < frame_head_offset)
|
||||
else if(59376 < frame_head_offset) // 61440 - (2079-15)
|
||||
{
|
||||
//当前buffer尾
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + ((frame_head_offset -16) <<2) ),
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + ((frame_head_offset -FRONT_LEN) <<2) ),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr),
|
||||
((61440 - (frame_head_offset -16)) )<<2,
|
||||
((61440 - (frame_head_offset -FRONT_LEN)) )<<2,
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
//下个buffer头 等待保证数据被jesd_csu存入
|
||||
while(time1 - time0 < 10000)
|
||||
while(time1 > 20000)
|
||||
{
|
||||
time1 = Time_offset(2);
|
||||
}
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(src_addr1),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr + (61440 - (frame_head_offset -16) ) ),
|
||||
(1055 - (61440 - (frame_head_offset -16)) )<<2,
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr + (61440 - (frame_head_offset -FRONT_LEN) ) ),
|
||||
(TOT_LEN - (61440 - (frame_head_offset -FRONT_LEN)) )<<2,
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
|
||||
// LOG_ERROR_S("csu2:%d %d\n", ((61440 - (frame_head_offset -16)) )<<2 , (1055 - (61440 - (frame_head_offset -16)) )<<2 );
|
||||
// LOG_ERROR_S("csu2:%d %d\n", ((61440 - (frame_head_offset -FRONT_LEN)) )<<2 , (2079 - (61440 - (frame_head_offset -FRONT_LEN)) )<<2 );
|
||||
}
|
||||
else
|
||||
{
|
||||
//当前buffer
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + ((frame_head_offset -16) <<2) ),
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + ((frame_head_offset -FRONT_LEN) <<2) ),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm0_ptr),
|
||||
(1055)<<2,
|
||||
(TOT_LEN)<<2,
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
|
||||
// LOG_ERROR_S("csu3:0x%08x 0x%08x\n", (src_addr0 + ((frame_head_offset -16) <<2) ) , receiver_sync_temp_dm0_ptr );
|
||||
// LOG_ERROR_S("csu3:0x%08x 0x%08x\n", (src_addr0 + ((frame_head_offset -FRONT_LEN) <<2) ) , receiver_sync_temp_dm0_ptr );
|
||||
}
|
||||
|
||||
//复制数据DM0 -> DM1
|
||||
cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigByteCopy_CFG1_Offset;
|
||||
ByteCopy((int)cfg_addr,
|
||||
MPU_ADDR(receiver_sync_temp_dm0_ptr),
|
||||
MPU_ADDR(receiver_sync_temp_dm1_ptr),
|
||||
(1055) << 2);
|
||||
// cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigByteCopy_CFG1_Offset;
|
||||
// ByteCopy((int)cfg_addr,
|
||||
// MPU_ADDR(receiver_sync_temp_dm0_ptr+1024),
|
||||
// MPU_ADDR(receiver_sync_temp_dm1_ptr),
|
||||
// (1024+15+16) << 2);
|
||||
|
||||
WAIT_MPU_STOP;
|
||||
ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 3);
|
||||
// WAIT_MPU_STOP;
|
||||
// ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
// TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 3);
|
||||
|
||||
dbg_time1 = Time_offset(2);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 5, dbg_time1-dbg_time0 );
|
||||
dbg_time0 = dbg_time1;
|
||||
// dbg_time1 = Time_offset(2);
|
||||
// TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 5, dbg_time1-dbg_time0 );
|
||||
// dbg_time0 = dbg_time1;
|
||||
// LOG_ERROR_S("%d %d %d\n", sfn, slot , dbg_cur_time);
|
||||
// if(100 < dbg_cur_time )
|
||||
// {
|
||||
@ -382,81 +397,119 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
// __ucps2_dbgbreak();
|
||||
// }
|
||||
|
||||
//插空拷贝数据到SM,提供给sync_symb数据输入来源
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0),
|
||||
(uint64_t)(sync2symb_data_buffer[buffer_sel]),
|
||||
(61440)<<2,
|
||||
DMA_TAG_G2G,
|
||||
|
||||
g_receiver_sync_cylic_buffer.buffer_in_sel = (g_receiver_sync_cylic_buffer.buffer_in_sel + 1) % RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER;
|
||||
|
||||
// SVRReg[0] = MPU_ADDR(cfg_addr);
|
||||
// ByteCopyAsm(SVRReg);
|
||||
|
||||
// cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset;
|
||||
|
||||
// SyncVer((int)cfg_addr,
|
||||
// MPU_ADDR(receiver_sync_temp_dm0_ptr),
|
||||
// MPU_ADDR(receiver_sync_temp_dm1_ptr),
|
||||
// //MPU_ADDR(receiver_sync_temp_dm2_ptr),
|
||||
// MPU_ADDR(receiver_sync_temp_dm3_ptr));
|
||||
|
||||
// WAIT_MPU_STOP;
|
||||
// TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 4);
|
||||
// dbg_time1 = Time_offset(2);
|
||||
// TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 6, dbg_time1-dbg_time0 );
|
||||
// dbg_time0 = dbg_time1;
|
||||
// SVRReg[0] = MPU_ADDR(cfg_addr);
|
||||
// SyncVerAsm(SVRReg);
|
||||
|
||||
//搬移导频
|
||||
ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(g_receiver_sync_table_param.receiver_sync_pilot_ptr),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_temp_dm1_ptr),
|
||||
(1024)<<2,
|
||||
DMA_TAG_G2L,
|
||||
0);
|
||||
|
||||
SVRReg[0] = MPU_ADDR(cfg_addr);
|
||||
ByteCopyAsm(SVRReg);
|
||||
//相关计算
|
||||
cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigSliding_CFG5_Offset;
|
||||
|
||||
|
||||
cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset;
|
||||
SyncVer((int)cfg_addr,
|
||||
MPU_ADDR(receiver_sync_temp_dm0_ptr),
|
||||
Sliding((int)cfg_addr,
|
||||
MPU_ADDR(receiver_sync_temp_dm0_ptr + 1024),
|
||||
MPU_ADDR(receiver_sync_temp_dm1_ptr),
|
||||
MPU_ADDR(receiver_sync_temp_dm2_ptr),
|
||||
MPU_ADDR(receiver_sync_temp_dm3_ptr));
|
||||
|
||||
WAIT_MPU_STOP;
|
||||
|
||||
ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
//插空拷贝数据到SM,提供给sync_symb数据输入来源
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0),
|
||||
(uint64_t)(sync2symb_data_buffer[g_receiver_sync_cylic_buffer.buffer_in_sel]),
|
||||
(61440)<<2,
|
||||
DMA_TAG_G2G,
|
||||
0);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 4);
|
||||
dbg_time1 = Time_offset(2);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 6, dbg_time1-dbg_time0 );
|
||||
dbg_time0 = dbg_time1;
|
||||
SVRReg[0] = MPU_ADDR(cfg_addr);
|
||||
SyncVerAsm(SVRReg);
|
||||
SlidingAsm(SVRReg);
|
||||
|
||||
|
||||
|
||||
|
||||
// 得到验证后的同步位置
|
||||
WAIT_MPU_STOP;
|
||||
uint32_t maxPosition = 0;
|
||||
uint32_t maxsum = 0;
|
||||
uint32_t loop_idx;
|
||||
for(loop_idx = 0; loop_idx < 32; loop_idx++)
|
||||
{
|
||||
if(receiver_sync_temp_dm3_ptr[loop_idx] > maxsum)
|
||||
{
|
||||
maxPosition = loop_idx;
|
||||
maxsum = receiver_sync_temp_dm3_ptr[loop_idx];
|
||||
}
|
||||
}
|
||||
// maxPosition = 0xffff & receiver_sync_temp_dm3_ptr[0];
|
||||
// maxsum = receiver_sync_temp_dm3_ptr[1];
|
||||
LOG_ERROR_S("1 maxPosition:%d maxsum:%d\n",maxPosition, maxsum);
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 12, maxPosition);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 13, maxsum);
|
||||
|
||||
|
||||
dbg_time1 = Time_offset(2);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 7, dbg_time1-dbg_time0 );
|
||||
dbg_time0 = dbg_time1;
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 5);
|
||||
uint32_t maxWindowSum = receiver_sync_temp_dm3_ptr[1];
|
||||
//更新最佳位置
|
||||
int32_t bestPosition =receiver_sync_temp_dm3_ptr[0]-16 + frame_head_offset;
|
||||
LOG_ERROR_S("bestpos %d %d %d\n", receiver_sync_temp_dm3_ptr[0], maxWindowSum, bestPosition);
|
||||
int32_t bestPosition = maxPosition-15 + frame_head_offset;
|
||||
// LOG_ERROR_S("bestpos %d %d %d\n", receiver_sync_temp_dm3_ptr[0], maxWindowSum, bestPosition);
|
||||
//更新sync2symb的buffer状态记录
|
||||
volatile uint32_t cylic_buffer_data_len = LOAD_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len) + 61440;
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len, cylic_buffer_data_len);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_offset , 61440 * buffer_sel2);
|
||||
|
||||
//找到本次同步参考点
|
||||
int32_t ref_pos = (g_receiver_sync_cylic_buffer.buffer_head + LOAD_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset)) % (g_receiver_sync_cylic_buffer.buffer_max);
|
||||
//更新循环buffer head
|
||||
g_receiver_sync_cylic_buffer.buffer_head = (g_receiver_sync_cylic_buffer.buffer_head + 61440) % (g_receiver_sync_cylic_buffer.buffer_max);
|
||||
|
||||
|
||||
volatile int32_t cylic_buffer_proc_data_offset = LOAD_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset);
|
||||
if(-1 == cylic_buffer_proc_data_offset ) //初始态,初始化数据处理偏移
|
||||
int32_t temp_interval = CALC_BUFFER_INTERVAL(g_receiver_sync_cylic_buffer.buffer_tail, ref_pos);
|
||||
|
||||
|
||||
if(temp_interval >= 61440)
|
||||
{
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset , 61440 * buffer_sel);
|
||||
__ucps2_synch(0);
|
||||
cylic_buffer_proc_data_offset = 61440 * buffer_sel;
|
||||
}
|
||||
|
||||
int32_t proc_head = ((g_receiver_sync_cylic_buffer.buffer_tail + temp_interval - 61440) % (g_receiver_sync_cylic_buffer.buffer_max));
|
||||
|
||||
volatile int32_t cylic_buffer_data_offset = 61440 * buffer_sel2;
|
||||
uint32_t cylic_buffer_data_offset_temp = (cylic_buffer_data_offset >= cylic_buffer_proc_data_offset) ?
|
||||
cylic_buffer_data_offset :
|
||||
(cylic_buffer_data_offset + 61440 * RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER);
|
||||
|
||||
uint32_t offset_temp = 0 + frame_head_offset;
|
||||
|
||||
//while(offset_temp <= cylic_buffer_data_offset_temp)
|
||||
{
|
||||
LOG_ERROR_S("%d %d %d\n", offset_temp, cylic_buffer_data_offset_temp, cylic_buffer_proc_data_offset);
|
||||
//if( (cylic_buffer_proc_data_offset + 61440 <= offset_temp) )
|
||||
//{
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 6);
|
||||
//更新tail
|
||||
g_receiver_sync_cylic_buffer.buffer_tail = (proc_head + 61440 + g_receiver_sync_cylic_buffer.buffer_max - 20) % (g_receiver_sync_cylic_buffer.buffer_max);
|
||||
//填写给symb任务的调度信息
|
||||
data_send2symb_task[task_idx].sfn = sfn;
|
||||
data_send2symb_task[task_idx].slot = slot;
|
||||
data_send2symb_task[task_idx].num_data_section = 1;//(offset_temp >= (61440 * RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER) && (offset_temp < (61440 * (RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER+1))) ) ? 2 : 1;
|
||||
data_send2symb_task[task_idx].data_section0_ptr = (uint32_t)(g_receiver_sync_cylic_buffer.buffer_ptr + proc_head);
|
||||
data_send2symb_task[task_idx].num_data_section = (g_receiver_sync_cylic_buffer.buffer_max >= proc_head + 61440) ? 1 : 2;
|
||||
data_send2symb_task[task_idx].data_section0_length = (2 == data_send2symb_task[task_idx].num_data_section) ? (g_receiver_sync_cylic_buffer.buffer_max - proc_head) : (61440);
|
||||
data_send2symb_task[task_idx].data_section1_ptr = (uint32_t)(g_receiver_sync_cylic_buffer.buffer_ptr);
|
||||
data_send2symb_task[task_idx].data_section1_length = 61440 - data_send2symb_task[task_idx].data_section0_length;
|
||||
data_send2symb_task[task_idx].proc_id = g_proc_id;
|
||||
data_send2symb_task[task_idx].data_section0_ptr = ((slot & 0x1) == 1) ? JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR : JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;//sync2symb_data_buffer[0] + (((offset_temp - 61440) % (61440*RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER))<<2);
|
||||
data_send2symb_task[task_idx].data_section0_length = 61440;//(offset_temp > (61440 * RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER)) ? ((61440 * RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER) - (offset_temp - 61440)) : 61440;
|
||||
data_send2symb_task[task_idx].data_section1_ptr = 0;// (2 == data_send2symb_task[task_idx].num_data_section) ? (sync2symb_data_buffer[0]) : 0;
|
||||
data_send2symb_task[task_idx].data_section1_length = 0;//(2 == data_send2symb_task[task_idx].num_data_section) ? (61440 - data_send2symb_task[task_idx].data_section0_length) : 0;
|
||||
data_send2symb_task[task_idx].transform_para_real[0] = transform_get_thita1_real();
|
||||
data_send2symb_task[task_idx].transform_para_real[1] = transform_get_thita2_real();
|
||||
data_send2symb_task[task_idx].transform_para_real[2] = transform_get_thita3_real();
|
||||
@ -465,10 +518,9 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
data_send2symb_task[task_idx].transform_para_imag[1] = transform_get_thita2_imag();
|
||||
data_send2symb_task[task_idx].transform_para_imag[2] = transform_get_thita3_imag();
|
||||
data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag();
|
||||
g_proc_id++;
|
||||
|
||||
//维护状态信息
|
||||
cylic_buffer_data_len = cylic_buffer_data_offset_temp - offset_temp;
|
||||
cylic_buffer_proc_data_offset = offset_temp % (61440*RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER);
|
||||
LOG_ERROR_S("data1 %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset);
|
||||
|
||||
//为了适配SYMB接口,如果数据是两段,搬移成一块
|
||||
if(2 == data_send2symb_task[task_idx].num_data_section)
|
||||
@ -481,11 +533,10 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
1);
|
||||
}
|
||||
//发核间消息给SYMB_TASK, slot号为偶数APE5处理,奇数APE3处理
|
||||
uint32_t symb_proc_core_sel = (0 == (g_receiver_sync_cylic_buffer.buffer_out_sel & 0x1)) ? APE5_CORE_ID : APE3_CORE_ID;
|
||||
g_receiver_sync_cylic_buffer.buffer_out_sel = (g_receiver_sync_cylic_buffer.buffer_out_sel + 1) & 0x1;
|
||||
if(SYNC_TRACKING == proc_type)
|
||||
{
|
||||
uint32_t symb_proc_core_sel = (0 == (slot & 0x1)) ? APE5_CORE_ID : APE3_CORE_ID;
|
||||
|
||||
|
||||
phy_et_msg_send((uint32_t)(&data_send2symb_task[task_idx]),
|
||||
sizeof(receiver_sync2symb_t),
|
||||
UCP4008_KERNEL_INTER,
|
||||
@ -494,6 +545,7 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
PHY_TASK_RECEIVER_SYNC,
|
||||
PHY_TASK_RECEIVER_SYMB);
|
||||
//递推1次
|
||||
LOG_ERROR_S("dt %d %d %d %d %d %d\n", sfn, slot, g_thita1_val, g_thita2_val, g_thita34_val);
|
||||
transform_para_update(1);
|
||||
}
|
||||
else
|
||||
@ -506,14 +558,83 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
PHY_TASK_RECEIVER_SYNC,
|
||||
PHY_TASK_PCIE);
|
||||
}
|
||||
g_proc_id++;
|
||||
task_idx++;
|
||||
//}
|
||||
|
||||
offset_temp += 61440;
|
||||
}
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len , cylic_buffer_data_len);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset, cylic_buffer_proc_data_offset);
|
||||
|
||||
|
||||
temp_interval = CALC_BUFFER_INTERVAL(ref_pos, g_receiver_sync_cylic_buffer.buffer_head);
|
||||
if(temp_interval >= 61440)
|
||||
{
|
||||
|
||||
int32_t proc_head = ref_pos;
|
||||
|
||||
//更新tail
|
||||
g_receiver_sync_cylic_buffer.buffer_tail = (proc_head + 61440 + g_receiver_sync_cylic_buffer.buffer_max - 20) % (g_receiver_sync_cylic_buffer.buffer_max);
|
||||
//填写给symb任务的调度信息
|
||||
data_send2symb_task[task_idx].sfn = sfn;
|
||||
data_send2symb_task[task_idx].slot = slot;
|
||||
data_send2symb_task[task_idx].data_section0_ptr = (uint32_t)(g_receiver_sync_cylic_buffer.buffer_ptr + proc_head);
|
||||
data_send2symb_task[task_idx].num_data_section = (g_receiver_sync_cylic_buffer.buffer_max >= proc_head + 61440) ? 1 : 2;
|
||||
data_send2symb_task[task_idx].data_section0_length = (2 == data_send2symb_task[task_idx].num_data_section) ? (g_receiver_sync_cylic_buffer.buffer_max - proc_head) : (61440);
|
||||
data_send2symb_task[task_idx].data_section1_ptr = (uint32_t)(g_receiver_sync_cylic_buffer.buffer_ptr);
|
||||
data_send2symb_task[task_idx].data_section1_length = 61440 - data_send2symb_task[task_idx].data_section0_length;
|
||||
data_send2symb_task[task_idx].proc_id = g_proc_id;
|
||||
data_send2symb_task[task_idx].transform_para_real[0] = transform_get_thita1_real();
|
||||
data_send2symb_task[task_idx].transform_para_real[1] = transform_get_thita2_real();
|
||||
data_send2symb_task[task_idx].transform_para_real[2] = transform_get_thita3_real();
|
||||
data_send2symb_task[task_idx].transform_para_real[3] = transform_get_thita4_real();
|
||||
data_send2symb_task[task_idx].transform_para_imag[0] = transform_get_thita1_imag();
|
||||
data_send2symb_task[task_idx].transform_para_imag[1] = transform_get_thita2_imag();
|
||||
data_send2symb_task[task_idx].transform_para_imag[2] = transform_get_thita3_imag();
|
||||
data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag();
|
||||
g_proc_id++;
|
||||
LOG_ERROR_S("data2 %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset);
|
||||
//为了适配SYMB接口,如果数据是两段,搬移成一块
|
||||
if(2 == data_send2symb_task[task_idx].num_data_section)
|
||||
{
|
||||
ape_csu_task_lookup(DMA_TAG_G2G,1);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(data_send2symb_task[task_idx].data_section1_ptr),
|
||||
(uint64_t)(data_send2symb_task[task_idx].data_section0_ptr + data_send2symb_task[task_idx].data_section0_length),
|
||||
(data_send2symb_task[task_idx].data_section1_length)<<2,
|
||||
DMA_TAG_G2G,
|
||||
1);
|
||||
}
|
||||
//发核间消息给SYMB_TASK, slot号为偶数APE5处理,奇数APE3处理
|
||||
uint32_t symb_proc_core_sel = (0 == (g_receiver_sync_cylic_buffer.buffer_out_sel & 0x1)) ? APE5_CORE_ID : APE3_CORE_ID;
|
||||
g_receiver_sync_cylic_buffer.buffer_out_sel = (g_receiver_sync_cylic_buffer.buffer_out_sel + 1) & 0x1;
|
||||
if(SYNC_TRACKING == proc_type)
|
||||
{
|
||||
phy_et_msg_send((uint32_t)(&data_send2symb_task[task_idx]),
|
||||
sizeof(receiver_sync2symb_t),
|
||||
UCP4008_KERNEL_INTER,
|
||||
get_core_id(),
|
||||
symb_proc_core_sel,
|
||||
PHY_TASK_RECEIVER_SYNC,
|
||||
PHY_TASK_RECEIVER_SYMB);
|
||||
//递推1次
|
||||
LOG_ERROR_S("dt %d %d %d %d %d %d\n", sfn, slot, g_thita1_val, g_thita2_val, g_thita34_val);
|
||||
transform_para_update(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
phy_et_msg_send((uint32_t)(&data_send2symb_task[task_idx]),
|
||||
sizeof(receiver_sync2pcie_t),
|
||||
UCP4008_KERNEL_INTER,
|
||||
get_core_id(),
|
||||
APE7_CORE_ID,
|
||||
PHY_TASK_RECEIVER_SYNC,
|
||||
PHY_TASK_PCIE);
|
||||
}
|
||||
task_idx++;
|
||||
}
|
||||
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_synch(0);
|
||||
// __ucps2_dbgbreak();
|
||||
|
||||
dbg_time1 = Time_offset(2);
|
||||
TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 8, dbg_time1-dbg_time0 );
|
||||
@ -539,8 +660,6 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
|
||||
else
|
||||
{
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_IDLE);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset , -1);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len, 0);
|
||||
}
|
||||
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 7);
|
||||
|
||||
|
@ -28,6 +28,8 @@ int32_t *receiver_sync_temp_dm3_ptr;
|
||||
|
||||
receiver_sync_status_t* g_receiver_sync_status_SM_ptr;
|
||||
receiver_sync2symb_t data_send2symb_task[3];
|
||||
|
||||
receiver_sync_cylic_buffer_t g_receiver_sync_cylic_buffer;
|
||||
uint16_t g_proc_id;
|
||||
|
||||
|
||||
@ -35,5 +37,5 @@ uint16_t g_proc_id;
|
||||
uint32_t sync2symb_data_buffer[RECEIVER_SYNC_SYNC2SYMB_NUM_BUFFER];
|
||||
|
||||
//debug
|
||||
uint32_t* last_mem_dm[8];
|
||||
int32_t* last_mem_dm[8];
|
||||
|
||||
|
@ -58,6 +58,6 @@ void Receiver_Sync_First_Init();
|
||||
void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_len);
|
||||
|
||||
//debug
|
||||
extern uint32_t* last_mem_dm[8];
|
||||
extern int32_t* last_mem_dm[8];
|
||||
|
||||
#endif
|
||||
|
@ -15,9 +15,9 @@
|
||||
//=======================================================================
|
||||
//微码配置空间长度定义,单位为word(4Byte)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigByteCopy_CFG1_LENGTH (0x0030)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelation_CFG2_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelation_CFG2_LENGTH (0x00a0)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigSyncVer_CFG4_LENGTH (0x0080)
|
||||
#define RECEIVER_SYNC_FIRST_ConfigSyncVer_CFG4_LENGTH (0x00a0)
|
||||
|
||||
//SPU查找表各字段长度定义,单位为word(4Byte)
|
||||
|
||||
|
@ -58,9 +58,10 @@ void Receiver_Sync_First_Init()
|
||||
ret = osp_get_cfgfile("Receiver_Sync_First_cfg_dm0.dat",
|
||||
(uint32_t *)&(g_receiver_sync_first_table_param.receiver_sync_first_config0_ddr_ptr),
|
||||
(int32_t *)&(g_receiver_sync_first_table_param.receiver_sync_first_config0_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Receiver_Sync_First_cfg_dm0.dat not found!\n");
|
||||
|
||||
//LOG_ERROR_S("Receiver_Sync_First_cfg_dm0.dat not found!\n");
|
||||
}
|
||||
// ret = osp_get_cfgfile("Receiver_Sync_First_cfg_dm1.dat",
|
||||
// (uint32_t *)&(g_receiver_sync_first_table_param.receiver_sync_config1_ddr_ptr),
|
||||
@ -74,7 +75,7 @@ void Receiver_Sync_First_Init()
|
||||
// (int32_t *)&(g_receiver_sync_first_table_param.receiver_sync_config3_length));
|
||||
|
||||
// LOG_ERROR_S("init %d 0x%08x %d\n", ret, g_receiver_sync_first_table_param.receiver_sync_config0_ddr_ptr, g_receiver_sync_first_table_param.receiver_sync_config0_length);
|
||||
g_receiver_sync_status_SM_ptr = (uint32_t)RECEIVER_SYNC2SYNC_FIRST_INF_ADDR;
|
||||
g_receiver_sync_status_SM_ptr = (receiver_sync_status_t*)RECEIVER_SYNC2SYNC_FIRST_INF_ADDR;
|
||||
|
||||
|
||||
}
|
||||
|
@ -271,7 +271,7 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
|
||||
SlidingCorrelation((int)cfg_addr,
|
||||
MPU_ADDR(receiver_sync_first_temp_dm0_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm1_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm2_ptr),
|
||||
//MPU_ADDR(receiver_sync_first_temp_dm2_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm3_ptr));
|
||||
|
||||
WAIT_MPU_STOP;
|
||||
@ -283,10 +283,14 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
|
||||
WAIT_MPU_STOP;
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 3, 5);
|
||||
//dm_check(1);
|
||||
maxPosition = receiver_sync_first_temp_dm3_ptr[0];
|
||||
maxPosition = 0xffff & receiver_sync_first_temp_dm3_ptr[0];
|
||||
maxsum = receiver_sync_first_temp_dm3_ptr[1];
|
||||
LOG_ERROR_S("1 maxPosition:%d maxsum:%d\n",maxPosition, maxsum);
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 12, maxPosition);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 13, maxsum);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 14, receiver_sync_first_temp_dm3_ptr[2]);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 15, receiver_sync_first_temp_dm3_ptr[3]);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + (sample_per_csu<<2)),
|
||||
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_first_temp_dm0_ptr),//
|
||||
(61440 - sample_per_csu)<<2,
|
||||
@ -331,7 +335,7 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
|
||||
SlidingCorrelationSecond((int)cfg_addr,
|
||||
MPU_ADDR(receiver_sync_first_temp_dm0_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm1_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm2_ptr),
|
||||
// MPU_ADDR(receiver_sync_first_temp_dm2_ptr),
|
||||
MPU_ADDR(receiver_sync_first_temp_dm3_ptr));
|
||||
WAIT_MPU_STOP;
|
||||
|
||||
@ -342,10 +346,10 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
|
||||
WAIT_MPU_STOP;
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 3, 7);
|
||||
LOG_ERROR_S("2 maxPosition:%d maxsum:%d\n",receiver_sync_first_temp_dm3_ptr[0], receiver_sync_first_temp_dm3_ptr[1]);
|
||||
LOG_ERROR_S("2 maxPosition:%d maxsum:%d\n",0xffff & receiver_sync_first_temp_dm3_ptr[0], receiver_sync_first_temp_dm3_ptr[1]);
|
||||
if(maxsum < receiver_sync_first_temp_dm3_ptr[1])
|
||||
{
|
||||
maxPosition = receiver_sync_first_temp_dm3_ptr[0];
|
||||
maxPosition = 0xffff & receiver_sync_first_temp_dm3_ptr[0];
|
||||
maxsum = receiver_sync_first_temp_dm3_ptr[1];
|
||||
}
|
||||
LOG_ERROR_S("3 maxPosition:%d maxsum:%d\n",maxPosition, maxsum);
|
||||
@ -358,18 +362,21 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
|
||||
LOG_INFO_S("rec sync first offset: %d %d\n", maxPosition, maxsum );
|
||||
ret = SYNC_OK;
|
||||
}
|
||||
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 16,maxPosition);
|
||||
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 17, maxsum);
|
||||
//执行完成,更新状态机
|
||||
if(SYNC_OK == ret)
|
||||
{
|
||||
#ifndef CLOSE_AI_PROCECING
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_AI_PROCECING);
|
||||
#else
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_TRACKING);
|
||||
#endif
|
||||
__ucps2_synch(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_IDLE);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_proc_data_offset , -1);
|
||||
STORE_EX_W(&g_receiver_sync_status_SM_ptr->cylic_buffer_data_len, 0);
|
||||
__ucps2_synch(0);
|
||||
}
|
||||
Receiver_Sync_First_Memory_Free();
|
||||
|
@ -32,5 +32,5 @@ uint16_t g_proc_id;
|
||||
|
||||
|
||||
//debug
|
||||
uint32_t* last_mem_dm[8];
|
||||
int32_t* last_mem_dm[8];
|
||||
|
||||
|
@ -39,8 +39,8 @@ extern double thita2imag[4][4];
|
||||
#define transform_get_thita4_imag() (thita2imag[3][LOAD_EX_W(g_thita4_addr + (g_thita34_val<<2))])
|
||||
|
||||
//获得当前8bit随机数值
|
||||
#define get_transform_8bit() (uint8_t)(transform_get_thita1_2bit() || (transform_get_thita2_2bit() << 2) || \
|
||||
(transform_get_thita3_2bit()<<4) || (transform_get_thita4_2bit() << 8))
|
||||
#define get_transform_8bit() (uint8_t)(transform_get_thita1_2bit() | (transform_get_thita2_2bit() << 2) | \
|
||||
(transform_get_thita3_2bit()<<4) | (transform_get_thita4_2bit() << 6))
|
||||
|
||||
/*初始化transform_para操作相关的变量,发送和接收使用同一个全局标量 note:发送和接受任务不能部署在同一个核上,否则维护的变量会冲突
|
||||
*设置存储寄存器序号
|
||||
@ -61,13 +61,21 @@ int transform_set_para(uint32_t thita1_init, uint32_t thita2_init, uint32_t thit
|
||||
int transform_para_update(uint32_t n);
|
||||
|
||||
/*根据pcie返回的结果计算当前状态,并更新寄存器参数
|
||||
*param: thita1_para:pcie提供的9bit
|
||||
*param: thita2_para:pcie提供的11bit
|
||||
*param: thita3_para:pcie提供的13bit
|
||||
*param: thita1_para:pcie提供的对应全部bit
|
||||
*param: thita2_para:pcie提供的对应全部bit
|
||||
*param: thita3_para:pcie提供的对应全部bit
|
||||
*/
|
||||
int transform_decode_para(uint32_t thita1_para, uint32_t thita2_para, uint32_t thita34_para);
|
||||
|
||||
|
||||
/*根据pcie返回的结果计算当前状态,并更新寄存器参数
|
||||
*param: thita1_para:pcie提供的对应全部bit
|
||||
*param: thita2_para:pcie提供的对应全部bit
|
||||
*param: thita3_para:pcie提供的对应全部bit
|
||||
*/
|
||||
int transform_decode_para_check(uint32_t thita1_para, uint32_t thita2_para, uint32_t thita34_para);
|
||||
|
||||
|
||||
/*根据时序偏差更新寄存器参数
|
||||
*param: cur_sfn:当前sfn号
|
||||
*param: cur_slot:当前slot号
|
||||
|
@ -43,72 +43,72 @@ int transform_para_init(uint32_t thita1_init, uint32_t thita2_init, uint32_t thi
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("thita1.dat load fail!\n");
|
||||
//LOG_ERROR_S("thita1.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("thita2.dat",
|
||||
(uint32_t *)&(g_thita2_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("thita2.dat load fail!\n");
|
||||
//LOG_ERROR_S("thita2.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("thita3.dat",
|
||||
(uint32_t *)&(g_thita3_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("thita3.dat load fail!\n");
|
||||
//LOG_ERROR_S("thita3.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("thita4.dat",
|
||||
(uint32_t *)&(g_thita4_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("thita4.dat load fail!\n");
|
||||
//LOG_ERROR_S("thita4.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("no1.dat",
|
||||
(uint32_t *)&(g_no1_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("no1.dat load fail!\n");
|
||||
//LOG_ERROR_S("no1.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("no2.dat",
|
||||
(uint32_t *)&(g_no2_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("no2.dat load fail!\n");
|
||||
//LOG_ERROR_S("no2.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("no3.dat",
|
||||
(uint32_t *)&(g_no3_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("no3.dat load fail!\n");
|
||||
//LOG_ERROR_S("no3.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("nextstate9.dat",
|
||||
(uint32_t *)&(g_nxtstate9_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("nextstate9.dat load fail!\n");
|
||||
//LOG_ERROR_S("nextstate9.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("nextstate11.dat",
|
||||
(uint32_t *)&(g_nxtstate11_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("nextstate11.dat load fail!\n");
|
||||
//LOG_ERROR_S("nextstate11.dat load fail!\n");
|
||||
}
|
||||
ret = osp_get_cfgfile("nextstate13.dat",
|
||||
(uint32_t *)&(g_nxtstate13_addr),
|
||||
(int32_t *)&(g_thita_len));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("nextstate13.dat load fail!\n");
|
||||
//LOG_ERROR_S("nextstate13.dat load fail!\n");
|
||||
}
|
||||
LOG_INFO_S("trasnform para dat init & load finish!\n");
|
||||
//LOG_INFO_S("trasnform para dat init & load finish!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -134,10 +134,11 @@ int transform_para_update(uint32_t n)
|
||||
//根据pcie返回的结果计算当前状态
|
||||
int transform_decode_para(uint32_t thita1_para, uint32_t thita2_para, uint32_t thita34_para)
|
||||
{
|
||||
//根据pcie提供的值查no1/2/3系列表,得到next偏移量
|
||||
volatile uint32_t temp1 = LOAD_EX_W(g_no1_addr + (thita1_para<<2));
|
||||
volatile uint32_t temp2 = LOAD_EX_W(g_no2_addr + (thita2_para<<2));
|
||||
volatile uint32_t temp3 = LOAD_EX_W(g_no3_addr + (thita34_para<<2));
|
||||
int32_t ret = -1;
|
||||
//根据pcie提供的值查no1/2/3系列表,得到next偏移量, 分别取9,11,13bit作为查表值,左移两位后再分别右移7/5/19位
|
||||
volatile uint32_t temp1 = LOAD_EX_W(g_no1_addr + ((thita1_para & 0xff80)>>5));
|
||||
volatile uint32_t temp2 = LOAD_EX_W(g_no2_addr + ((thita2_para & 0xffe0)>>3));
|
||||
volatile uint32_t temp3 = LOAD_EX_W(g_no3_addr + ((thita34_para & 0xfff80000)>>17));
|
||||
|
||||
//根据next9/11/13系列表,结合偏移量查询计算的时间点下的参数
|
||||
temp1 = LOAD_EX_W(g_nxtstate9_addr + (temp1<<2));
|
||||
@ -146,9 +147,45 @@ int transform_decode_para(uint32_t thita1_para, uint32_t thita2_para, uint32_t t
|
||||
|
||||
//算好后更新参数
|
||||
transform_set_para(temp1, temp2, temp3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int transform_decode_para_check(uint32_t thita1_para, uint32_t thita2_para, uint32_t thita34_para)
|
||||
{
|
||||
//取出用来对比的部分
|
||||
|
||||
uint32_t temp1 = (uint32_t)0xff & thita1_para;
|
||||
uint32_t temp2 = (uint32_t)0xff & thita2_para;
|
||||
uint32_t temp3 = (uint32_t)0xffff & thita34_para;
|
||||
uint32_t cnt = 0;
|
||||
uint32_t cmp_temp1 = 0;
|
||||
uint32_t cmp_temp2 = 0;
|
||||
uint32_t cmp_temp3 = 0;
|
||||
|
||||
|
||||
//初次递推
|
||||
transform_para_update(4);
|
||||
while(cnt < 4)
|
||||
{
|
||||
|
||||
cmp_temp1 = (cmp_temp1 <<2) | transform_get_thita1_2bit();
|
||||
cmp_temp2 = (cmp_temp2 <<2) | transform_get_thita2_2bit();
|
||||
cmp_temp3 = (cmp_temp3 <<4) | (transform_get_thita3_2bit() | (transform_get_thita4_2bit() << 2));
|
||||
|
||||
transform_para_update(1);
|
||||
cnt++;
|
||||
}
|
||||
|
||||
uint32_t cmp_res = ( (temp1 == cmp_temp1) && (temp2 == cmp_temp2) && (temp3 == cmp_temp3) );
|
||||
|
||||
LOG_INFO_S("transform check:%d %d %d %d\n", cmp_res, (temp1 == cmp_temp1) , (temp2 == cmp_temp2), (temp3 == cmp_temp3) );
|
||||
|
||||
return (cmp_res == 1) ? 0 : -1;
|
||||
}
|
||||
|
||||
|
||||
//根据时序偏差更新寄存器参数
|
||||
int transform_update_cur_para(uint32_t cur_sfn, uint32_t cur_slot, uint32_t ref_sfn, uint32_t ref_slot)
|
||||
{
|
||||
|
@ -36,6 +36,12 @@ extern uint32_t *transmitter_config_dm1_ptr;
|
||||
extern uint32_t *transmitter_config_dm2_ptr;
|
||||
extern uint32_t *transmitter_config_dm3_ptr;
|
||||
|
||||
#ifdef TRANS_DBG_DATA_TEST
|
||||
extern uint32_t g_trans_m_src_pos;
|
||||
extern uint32_t g_trans_dat_ptr;
|
||||
extern uint32_t g_trans_dat_length;
|
||||
#endif
|
||||
|
||||
void Transmitter_Init();
|
||||
void Transmitter_Task();
|
||||
void Transmitter_Proc(
|
||||
|
@ -63,9 +63,9 @@ void Transmitter_Init()
|
||||
ret = osp_get_cfgfile("Transmitter_cfg_dm1.dat",
|
||||
(uint32_t *)&(g_transmitter_table_param.transmitter_config1_ddr_ptr),
|
||||
(int32_t *)&(g_transmitter_table_param.transmitter_config1_length));
|
||||
if(-1 == ret)
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Transmitter_cfg_dm1.dat not found!\n");
|
||||
//LOG_ERROR_S("Transmitter_cfg_dm1.dat not found!\n");
|
||||
}
|
||||
//ret = osp_get_cfgfile("Transmitter_cfg_dm2.dat",
|
||||
// (uint32_t *)&(g_transmitter_table_param.transmitter_config2_ddr_ptr),
|
||||
@ -73,7 +73,30 @@ void Transmitter_Init()
|
||||
//ret = osp_get_cfgfile("Transmitter_cfg_dm3.dat",
|
||||
// (uint32_t *)&(g_transmitter_table_param.transmitter_config3_ddr_ptr),
|
||||
// (int32_t *)&(g_transmitter_table_param.transmitter_config3_length));
|
||||
LOG_ERROR_S("Transmitter_INIT finish\n");
|
||||
|
||||
#ifdef TRANS_DBG_DATA_TEST
|
||||
ret = osp_get_cfgfile("Trans.dat",
|
||||
(uint32_t *)&(g_trans_dat_ptr),
|
||||
(int32_t *)&(g_trans_dat_length));
|
||||
if(0 != ret)
|
||||
{
|
||||
LOG_ERROR_S("Trans.dat not found!\n");
|
||||
}
|
||||
if(0 != g_trans_dat_length)
|
||||
{
|
||||
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(g_trans_dat_ptr),
|
||||
(uint64_t)SOURCE_DATA_DDR_ADDR,//第一次固定搬移到dm0
|
||||
g_trans_dat_length,
|
||||
DMA_TAG_G2G,
|
||||
1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef TRANS_SRC_AUTO_GEN
|
||||
g_trans_m_src_pos = 0;
|
||||
#endif
|
||||
|
||||
transform_para_init(0, 0, 0);
|
||||
|
||||
LOG_ERROR_S("Transmitter_INIT finish\n");
|
||||
}
|
||||
|
@ -13,6 +13,29 @@
|
||||
#include "transform_para_func.h"
|
||||
//#include "log_interface.h"
|
||||
|
||||
|
||||
/*!
|
||||
* @brief: Transmitter链路处理
|
||||
* @author: HUOHUO
|
||||
* @Date: 2025年5月28日
|
||||
*/
|
||||
#ifdef TRANS_SRC_AUTO_GEN
|
||||
uint32_t get_src_addr()
|
||||
{
|
||||
if(0 != g_trans_dat_length)
|
||||
{
|
||||
uint32_t cur_pos = g_trans_m_src_pos;
|
||||
g_trans_m_src_pos = (g_trans_m_src_pos + SOURCE_DATA_BYTE_LENGTH) % g_trans_dat_length;
|
||||
return cur_pos;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*!
|
||||
* @brief: Transmitter链路处理
|
||||
* @author: HUOHUO
|
||||
@ -69,7 +92,17 @@ void Transmitter_Proc(
|
||||
*/
|
||||
|
||||
//**********************************for board begin**********************************
|
||||
source_bit_ddr_ptr = (SOURCE_DATA_DDR_ADDR + 16016 * cur_slot); // 0-19 帧数循环
|
||||
#ifdef TRANS_SRC_AUTO_GEN_DBG
|
||||
//数据来源M序列初始值
|
||||
source_bit_ddr_ptr = (uint32_t)SOURCE_DATA_DDR_ADDR; // 0-19 帧数循环
|
||||
#elif (defined(TRANS_SRC_AUTO_GEN))
|
||||
//数据来源M序列递推
|
||||
source_bit_ddr_ptr = (uint32_t)SOURCE_DATA_DDR_ADDR + get_src_addr();
|
||||
#else
|
||||
//数据来源ARM放数
|
||||
source_bit_ddr_ptr = (SOURCE_DATA_DDR_ADDR + SOURCE_DATA_BYTE_LENGTH * cur_slot); // 0-19 帧数循环
|
||||
#endif
|
||||
|
||||
// source_bit_ddr_ptr = (SOURCE_DATA_DDR_ADDR); //固定读第一帧数据
|
||||
//等待 DMA 通道可用
|
||||
ape_csu_task_lookup(DMA_TAG_G2L, 1);
|
||||
@ -317,19 +350,24 @@ void Transmitter_Proc(
|
||||
uint32_t TRANSMOUT_symbol_SM_addr_in = TRANSMITTER_OUT;//SM
|
||||
uint32_t TRANSMOUT_symbol_SM_addr_out = TRANSMITTER_OUT + 14*4096*4 + 4*1024;
|
||||
uint32_t TRANSMOUT_DATA_SM_addr_out = TRANSMOUT_symbol_SM_addr_out + 14*4096*4 + 4*1024;
|
||||
double thita[4] = {0};
|
||||
double i_real[4] = {0};
|
||||
double i_imag[4] = {0};
|
||||
//打桩固定参数
|
||||
double thita[6] = {0.435,2.784,1.864,1.211,2.546,2.011};
|
||||
// double i_real[8] = {0.906870042299337, -0.936742157061748, -0.289020652644219, 0.352083608864027, -0.827816165894850, -0.426123729901221};
|
||||
// double i_imag[8] = {0.421410401366648, 0.350020186822565, 0.957322862123907, 0.935968553087807, 0.560999461214670, 0.904664891998729};
|
||||
double i_real[8] = {-0.3827, 0.8660, -0.7071, 0.5};
|
||||
double i_imag[8] = {0.9239, 0.5, -0.7071, 0.8660};
|
||||
// double i_real[8] = {0};
|
||||
// double i_imag[8] = {0};
|
||||
|
||||
i_real[0] = transform_get_thita1_real();
|
||||
i_real[1] = transform_get_thita2_real();
|
||||
i_real[2] = transform_get_thita3_real();
|
||||
i_real[3] = transform_get_thita4_real();
|
||||
// i_real[0] = transform_get_thita1_real();
|
||||
// i_real[1] = transform_get_thita2_real();
|
||||
// i_real[2] = transform_get_thita3_real();
|
||||
// i_real[3] = transform_get_thita4_real();
|
||||
|
||||
i_imag[0] = transform_get_thita1_imag();
|
||||
i_imag[1] = transform_get_thita2_imag();
|
||||
i_imag[2] = transform_get_thita3_imag();
|
||||
i_imag[3] = transform_get_thita4_imag();
|
||||
// i_imag[0] = transform_get_thita1_imag();
|
||||
// i_imag[1] = transform_get_thita2_imag();
|
||||
// i_imag[2] = transform_get_thita3_imag();
|
||||
// i_imag[3] = transform_get_thita4_imag();
|
||||
|
||||
double* thita1, * thita2, * thita3;
|
||||
thita1 = thita2 = thita3 = thita;
|
||||
@ -562,6 +600,7 @@ void Transmitter_Proc(
|
||||
}
|
||||
//**********************pilot trans**********************
|
||||
//发送数据后更新递推
|
||||
//LOG_ERROR_S("dt %d %d %d %d %d %d\n", cur_sfn, cur_slot, g_thita1_val, g_thita2_val, g_thita34_val, GET_CNT_VAL(0));
|
||||
transform_para_update(1);
|
||||
|
||||
|
||||
|
@ -24,8 +24,8 @@
|
||||
*/
|
||||
void Transmitter_Task()
|
||||
{
|
||||
//!!!DBG
|
||||
return;
|
||||
// //!!!DBG
|
||||
// return;
|
||||
//时间统计
|
||||
g_time_start[1] = TIME_NS();
|
||||
uint16_t time0_us, time1_us;
|
||||
|
@ -8,6 +8,7 @@
|
||||
* 2024年4月20日 HUOHUO create file
|
||||
*****************************************************************/
|
||||
#include "transmitter_struct.h"
|
||||
#include "test_macro.h"
|
||||
|
||||
//Transmitter微码配置空间offset结构体
|
||||
transmitter_table_param_t g_transmitter_table_param;
|
||||
@ -15,3 +16,9 @@ uint32_t *transmitter_config_dm0_ptr = NULLPTR;
|
||||
uint32_t *transmitter_config_dm1_ptr = NULLPTR;
|
||||
uint32_t *transmitter_config_dm2_ptr = NULLPTR;
|
||||
uint32_t *transmitter_config_dm3_ptr = NULLPTR;
|
||||
|
||||
#ifdef TRANS_DBG_DATA_TEST
|
||||
uint32_t g_trans_m_src_pos;
|
||||
uint32_t g_trans_dat_ptr;
|
||||
uint32_t g_trans_dat_length;
|
||||
#endif
|
@ -12,7 +12,8 @@
|
||||
#ifndef UCP_MEM_DEF_H
|
||||
#define UCP_MEM_DEF_H
|
||||
|
||||
#define RECV_DBG_DATA_TEST
|
||||
#include "test_macro.h"
|
||||
|
||||
|
||||
//!命名宏定义时需要注意UCP使用的地址
|
||||
/*********************************UCP************************************************/
|
||||
@ -41,6 +42,8 @@
|
||||
//SM3
|
||||
#define SM3_NR_PUCCH_LUT_LEN (0x00040000) //256K
|
||||
#define SM3_PHY_MSG_BUFFER_LEN (0x00000400) //1K
|
||||
//SM5
|
||||
#define SM5_SYMB2_BIT_LEN (0x00038000)
|
||||
//DDR
|
||||
#define TRACE_GRP_LEN (0x00000200) //128Word
|
||||
|
||||
@ -81,7 +84,15 @@
|
||||
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
|
||||
|
||||
/************************************SM5--1.5M***********************************************/
|
||||
|
||||
//SM5前面区域被占用
|
||||
#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t)
|
||||
#ifdef CORE_ODD
|
||||
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN)
|
||||
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN)
|
||||
#else
|
||||
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 2*SM5_SYMB2_BIT_LEN)
|
||||
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 3*SM5_SYMB2_BIT_LEN)
|
||||
#endif
|
||||
/**************************************DDR***************************************************/
|
||||
//1.93GB可用0x14400000-0x8FFFFFFF
|
||||
#define DDR_PHY_BASE (0x14400000)
|
||||
@ -93,7 +104,11 @@
|
||||
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
|
||||
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
|
||||
|
||||
#ifndef RECV_DBG_DATA_TEST
|
||||
|
||||
#ifdef TX_RX_LOOP
|
||||
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR)
|
||||
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR)
|
||||
#elif !defined(TX_RX_LOOP) && !defined(RECV_DBG_DATA_TEST)
|
||||
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000) //!!!DDR_PHY_BASE 0x1E0000
|
||||
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000) // 0x1E0000
|
||||
#else
|
||||
@ -110,7 +125,7 @@
|
||||
|
||||
//---------------ARM Transmitter比特存放地址,大小SOURCE_DATA_BYTE_LENGTH*SOURCE_DATA_BUFFER_NUM = 313KB
|
||||
#define SOURCE_DATA_FLAG_DDR_ADDR (0x84000000) // SPU READ FLAG
|
||||
#define SOURCE_DATA_DDR_ADDR (0x84001000)
|
||||
#define SOURCE_DATA_DDR_ADDR (0x84C00000)
|
||||
#define SOURCE_DATA_BUFFER_NUM (20)
|
||||
#define SOURCE_DATA_BYTE_LENGTH (16016)
|
||||
#define SOURCE_DATA_DDR_ADDR_END (SOURCE_DATA_DDR_ADDR + SOURCE_DATA_BUFFER_NUM*SOURCE_DATA_BYTE_LENGTH + 0x100)
|
||||
@ -140,5 +155,6 @@
|
||||
|
||||
#define TRACE_TRANSMITTER_ADDR (TRACE_PCIE_ADDR + TRACE_GRP_LEN) // 0x88701400
|
||||
#define TRACE_TRANS_INIT_ADDR (TRACE_TRANSMITTER_ADDR + TRACE_GRP_LEN) // 0x88701600
|
||||
#define TRACE_RECEIVER_SYNC_INIT_ADDR (TRACE_TRANS_INIT_ADDR + TRACE_GRP_LEN) // 0x88701800
|
||||
|
||||
#endif
|
||||
|
24
Common/inc/test_macro.h
Normal file
24
Common/inc/test_macro.h
Normal file
@ -0,0 +1,24 @@
|
||||
#ifndef _TEST_MACRO_H_
|
||||
#define _TEST_MACRO_H_
|
||||
|
||||
/*Recv从receiver_Sync_Init.s.c打桩数据时打开此宏*/
|
||||
#define RECV_DBG_DATA_TEST
|
||||
|
||||
/*RX数据输入直接从TX Buffer读入,数据环回开关*/
|
||||
//#define TX_RX_LOOP
|
||||
|
||||
/*Transmit加载Trans.dat作为输入数据*/
|
||||
//#define TRANS_DBG_DATA_TEST
|
||||
|
||||
/*二选一或者都不打开,都不打开数据源是ARM,否则需要配合TRANS_DBG_DATA_TEST打开使用*/
|
||||
/*Transmit m序列自行递推,*/
|
||||
//#define TRANS_SRC_AUTO_GEN
|
||||
/*Transmit m序列固定为起始值*/
|
||||
//#define TRANS_SRC_AUTO_GEN_DBG
|
||||
|
||||
|
||||
/*状态机跳过RK3588计算*/
|
||||
#define CLOSE_AI_PROCECING
|
||||
|
||||
|
||||
#endif /*_TEST_MACRO_H_*/
|
@ -278,7 +278,7 @@ int32_t phy_et_msg_send(uint32_t msg_addr,
|
||||
}
|
||||
else
|
||||
{
|
||||
//TASK_MSG_RECORD(src_core_id, src_task_id, TASK_MSG_SEND_ERR);
|
||||
LOG_ERROR_S("osp_send_msg ERR\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
@ -46,59 +46,27 @@
|
||||
0x004000ce,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -146,6 +114,166 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000400,
|
||||
0x00000400,
|
||||
0x00007600,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -160,7 +288,7 @@
|
||||
0x00000000,
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00007a00,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -174,59 +302,59 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -274,108 +402,12 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
@ -414,9 +446,41 @@
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000016,
|
||||
0x00000400,
|
||||
0x00000020,
|
||||
0x00000400,
|
||||
0x0000001f,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
@ -46,59 +46,27 @@
|
||||
0x004000ce,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -146,6 +114,166 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000400,
|
||||
0x00000400,
|
||||
0x00007600,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -160,7 +288,7 @@
|
||||
0x00000000,
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00007a00,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -174,59 +302,59 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -274,108 +402,12 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
@ -414,9 +446,9 @@
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000016,
|
||||
0x00000400,
|
||||
0x00000020,
|
||||
0x00000400,
|
||||
0x0000001f,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -430,3 +462,131 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0x04000400,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000400,
|
||||
0x0000001f,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
1024
Config/Recv_Pilot.dat
Normal file
1024
Config/Recv_Pilot.dat
Normal file
File diff suppressed because it is too large
Load Diff
32768
Config/Trans.dat
Normal file
32768
Config/Trans.dat
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
61440
Config/even.dat
Normal file
61440
Config/even.dat
Normal file
File diff suppressed because it is too large
Load Diff
57344
Config/gain_test.dat
57344
Config/gain_test.dat
File diff suppressed because it is too large
Load Diff
2048
Config/odd.dat
Normal file
2048
Config/odd.dat
Normal file
File diff suppressed because it is too large
Load Diff
114688
Config/timedata.dat
114688
Config/timedata.dat
File diff suppressed because it is too large
Load Diff
18
Interface/interface_rec_symb2_rec_bit.h
Normal file
18
Interface/interface_rec_symb2_rec_bit.h
Normal file
@ -0,0 +1,18 @@
|
||||
#ifndef INTERFACE_REC_SYMB2_REC_BIT_H
|
||||
#define INTERFACE_REC_SYMB2_REC_BIT_H
|
||||
#include "type_define.h"
|
||||
|
||||
typedef struct receiver_symb2bit_s
|
||||
{
|
||||
uint16_t sfn;//创建任务时刻的sfn
|
||||
uint16_t slot;//创建任务时刻的slot
|
||||
uint16_t proc_id;//记录包的顺序
|
||||
uint16_t rev;
|
||||
uint32_t data_ptr;
|
||||
uint32_t data_length;//单位Word
|
||||
}receiver_symb2bit_t;
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*INTERFACE_REC_SYMB2_REC_BIT_H*/
|
@ -5,12 +5,11 @@
|
||||
|
||||
typedef struct receiver_sync_status_s
|
||||
{
|
||||
uint32_t cylic_buffer_data_offset;//循环buffer指示数据存入的头相对buffer_ptr[0]偏移
|
||||
int32_t cylic_buffer_proc_data_offset;//循环buffer指示数据处理的头相对buffer_ptr[0]偏移
|
||||
uint32_t cylic_buffer_data_len;//单位是Word
|
||||
uint32_t sync_status;//参见receiver_sync_status_e
|
||||
uint32_t frame_head_offset;//每个500us中帧头的偏移值,范围0~61439
|
||||
|
||||
int32_t frame_head_offset;//每个500us中帧头的偏移值,范围0~61439
|
||||
}receiver_sync_status_t;
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
2
Makefile
2
Makefile
@ -12,7 +12,7 @@ REMOVE_MC_TEST:=1
|
||||
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin
|
||||
#GDB_PATH=/opt/sdk/ucp2.0_sdk/simulator/ucp2-gdb
|
||||
#SIM_PATH=/opt/sdk/ucp2.0_sdk/simulator/UCP_Simulator_V2.0
|
||||
|
||||
# export MaPU_TC_HOME=/home/useryb/ucpcompile/toolchain
|
||||
UCP_HOME=${MaPU_TC_HOME}/bin/ucp2
|
||||
GDB_PATH=${MaPU_TC_HOME}/bin/ucp2/ucp2-gdb
|
||||
SIM_PATH=${MaPU_TC_HOME}/bin/ucp2/ucp2-simulator
|
||||
|
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x000000e0,//224
|
||||
0x000000e0,//224
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -37,16 +37,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00003800,//14336
|
||||
0x00000800,//2048
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00020002,//2<<16+2
|
||||
0x00070007,//7<<16+7
|
||||
0x00200020,//32<<16+32
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00003800,//14336
|
||||
0x00000800,//2048
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00020002,//2<<16+2
|
||||
0x00070007,//7<<16+7
|
||||
0x00200020,//32<<16+32
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -99,4 +99,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
@ -1,8 +1,8 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000080,//128
|
||||
0x00000080,
|
||||
0x00000080,
|
||||
0x00000080,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -16,37 +16,37 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//ShiftMode 1 right move 2
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
//input 2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,//4096
|
||||
0x00000040,//64
|
||||
0x00004000,//16384
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00400040,//64<<16+64
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,//4096
|
||||
0x00000040,//64
|
||||
0x00004000,//16384
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00400040,//64<<16+64
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -133,4 +133,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
@ -1,12 +1,12 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -16,37 +16,37 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//ShiftMode 1 right move 2
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000203,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
0x00000204,
|
||||
//input 2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,//512
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00000000,//0
|
||||
0x00080008,//8<<16+8
|
||||
0x00080008,//8<<16+8
|
||||
0x00080008,//8<<16+8
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,//512
|
||||
0x00000040,//64
|
||||
0x00000800,//2048
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00080008,//8<<16+8
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -201,4 +201,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
57344
MicroCode/BlockTransform/inc/Input_0.dat
Normal file
57344
MicroCode/BlockTransform/inc/Input_0.dat
Normal file
File diff suppressed because it is too large
Load Diff
57344
MicroCode/BlockTransform/inc/Input_1.dat
Normal file
57344
MicroCode/BlockTransform/inc/Input_1.dat
Normal file
File diff suppressed because it is too large
Load Diff
12293
MicroCode/BlockTransform/inc/Input_Test.dat
Normal file
12293
MicroCode/BlockTransform/inc/Input_Test.dat
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -5,6 +5,8 @@
|
||||
|
||||
void Transform(int ConfigAddr, int InAddr, int OutAddr, int N, double* db_real, double* db_imag, int direct);
|
||||
void get_thita(int* current_state, double* thita);
|
||||
void RowCopy(int* Matrix,int* Block,int idx,int direct);
|
||||
void ColCopy(int* Matrix,int* Block,int idx,int direct);
|
||||
MPU_ENTRY void Transform2Asm(v16u32 src);
|
||||
MPU_ENTRY void Transform4Asm(v16u32 src);
|
||||
MPU_ENTRY void Transform8Asm(v16u32 src);
|
||||
|
@ -1,6 +1,6 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x000000e0,//224
|
||||
0x000000e0,//224
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -37,16 +37,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00003800,//14336
|
||||
0x00000800,//2048
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00020002,//2<<16+2
|
||||
0x00070007,//7<<16+7
|
||||
0x00200020,//32<<16+32
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00003800,//14336
|
||||
0x00000800,//2048
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00020002,//2<<16+2
|
||||
0x00070007,//7<<16+7
|
||||
0x00200020,//32<<16+32
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -99,4 +99,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
@ -1,8 +1,8 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000080,//128
|
||||
0x00000080,
|
||||
0x00000080,
|
||||
0x00000080,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -16,37 +16,37 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//ShiftMode 1
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
//input 2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,//4096
|
||||
0x00000040,//64
|
||||
0x00004000,//16384
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00400040,//64<<16+64
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,//4096
|
||||
0x00000040,//64
|
||||
0x00004000,//16384
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00400040,//64<<16+64
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -133,4 +133,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
@ -1,12 +1,12 @@
|
||||
//Mfetch 0
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000008,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -16,37 +16,37 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//ShiftMode 1
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000003,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
0x00000002,
|
||||
//input 2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,//512
|
||||
0x00000040,//64
|
||||
0x00000000,//0
|
||||
0x00000000,//0
|
||||
0x00080008,//8<<16+8
|
||||
0x00080008,//8<<16+8
|
||||
0x00080008,//8<<16+8
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//output 3
|
||||
@ -54,16 +54,16 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,//512
|
||||
0x00000040,//64
|
||||
0x00000800,//2048
|
||||
0x00000000,//0
|
||||
0x00040004,//4<<16+4
|
||||
0x00080008,//8<<16+8
|
||||
0x00020002,//2<<16+2
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000006,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//Index1 4
|
||||
@ -201,4 +201,4 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000
|
||||
0x00000000,
|
||||
|
@ -11,50 +11,45 @@ Transform2Asm:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
|
||||
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
|
||||
BIU1:Load(T0)(A++) -> M[0]; //KI
|
||||
BIU1:Load(T0)(A++) -> M[1]; //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2]; //Input
|
||||
BIU1:Load(T0)(A++) -> M[3]; //Output
|
||||
BIU1:Load(T0)(A++) -> M[10]; //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11]; //factor2
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
R5:PreConfig(M[0])(Mode0);
|
||||
R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);
|
||||
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0);
|
||||
R3:M[3] -> BIU3.T1(Mode0);
|
||||
R0:M[10] -> IMA0.T1(Mode0) ||R1:M[10] -> IMA1.T2(Mode0) ;
|
||||
R0:M[11] -> IMA0.T2(Mode0) ||R1:M[11] -> IMA1.T1(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
|
||||
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R5:PreConfig(M[0]);
|
||||
R0:M[1] -> IMA0.T0 || R5:WriteConf(Mfetch)->KI[0-3];
|
||||
R0:M[1] -> IMA1.T0 || R2:M[2] -> BIU2.T0;
|
||||
R3:M[3] -> BIU3.T1;
|
||||
R0:M[10] -> IMA0.T1 ||R1:M[10] -> IMA1.T2 ;
|
||||
R0:M[11] -> IMA0.T2 ||R1:M[11] -> IMA1.T1 || IMA0:SetShiftMode(T0) -> SHIFTMODE0;//load factor to IMA
|
||||
IMA1:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:wait 0 || R0: wait 9 ||IMA0: wait 12 || IMA1: wait 12 || SHU0: wait 16 ||SHU1: wait 16 ||BIU3: wait 19;
|
||||
MFetch:LPTO %BLOCK @(KI0 - 0);
|
||||
BIU2:Load(T0)(A++) -> M[20] || R0: M[20] -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0;
|
||||
R0: M[20] -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0;
|
||||
BIU2:Load(T0)(A++) -> M[20] || R0: M[20] -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || SHU0: T0+T1(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R0: M[20] -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || SHU1: T0+T1(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BLOCK:
|
||||
BIU2:wait 0 || R0: wait 0 || IMA0: wait 0 || IMA1: wait 0 || SHU0: wait 0 || SHU1: wait 0 || BIU3: wait 0;
|
||||
/*
|
||||
BIU2:wait 0 || IMA0: wait 10 || IMA1: wait 10|| SHU0: wait 14 ||SHU1: wait 14 ||BIU3: wait 17;
|
||||
MFetch:LPTO %BLOCK @(KI0 - 0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || SHU0: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || SHU1: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0;
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0;
|
||||
BIU2:Load(T0) -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || SHU0: T0+T1(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || SHU1: T0+T1(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
NOP;
|
||||
NOP;
|
||||
BLOCK:
|
||||
BIU2:wait 0 || IMA0: wait 0 || IMA1: wait 0 || SHU0: wait 0 || SHU1: wait 0 || BIU3: wait 0;
|
||||
|
||||
/*
|
||||
BIU2:wait 0 || IMA0: wait 10 || IMA1: wait 10|| SHU0: wait 10 ||SHU1: wait 10 ||BIU3: wait 13;
|
||||
MFetch:LPTO %BLOCK_0 @(KI0 - 0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
SHU0: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
SHU1: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BLOCK_0:
|
||||
BIU2:wait 0 || IMA0: wait 0 || IMA1: wait 0 || SHU0: wait 0 || SHU1: wait 0 || BIU3: wait 0;
|
||||
*/
|
||||
MFetch:REPEAT @(35);
|
||||
MFetch:MPU.STOP;
|
||||
|
@ -11,46 +11,69 @@ Transform4Asm:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
|
||||
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
|
||||
BIU1:Load(T0)(A++) -> M[12](Mode0); //factor3
|
||||
BIU1:Load(T0)(A++) -> M[13](Mode0); //factor4
|
||||
BIU1:Load(T0)(A++) -> M[0]; //KI
|
||||
BIU1:Load(T0)(A++) -> M[1]; //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2]; //Input
|
||||
BIU1:Load(T0)(A++) -> M[3]; //Output
|
||||
BIU1:Load(T0)(A++) -> M[10]; //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11]; //factor2
|
||||
BIU1:Load(T0)(A++) -> M[12]; //factor3
|
||||
BIU1:Load(T0)(A++) -> M[13]; //factor4
|
||||
NOP;
|
||||
NOP;
|
||||
R5:PreConfig(M[0])(Mode0);
|
||||
R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);
|
||||
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0);
|
||||
R2:M[1] -> IMA2.T0(Mode0) || R3:M[3] -> BIU3.T1(Mode0);
|
||||
R0:M[10] -> IMA0.T1(Mode0) ||R2:M[1] -> IMA3.T0(Mode0) ;
|
||||
R0:M[11] -> IMA0.T2(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || R2: M[10] -> IMA2.T3(Mode0) || R3: M[10] -> IMA3.T4(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
|
||||
R0:M[12] -> IMA0.T3(Mode0) || R1: M[11] -> IMA1.T3(Mode0) || R2: M[11] -> IMA2.T4(Mode0) || R3: M[11] -> IMA3.T1(Mode0) || IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R0:M[13] -> IMA0.T4(Mode0) || R1: M[12] -> IMA1.T4(Mode0) || R2: M[12] -> IMA2.T1(Mode0) || R3: M[12] -> IMA3.T2(Mode0) || IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R1: M[13] -> IMA1.T1(Mode0) || R2: M[13] -> IMA2.T2(Mode0) || R3: M[13] -> IMA3.T3(Mode0) ||IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R5:PreConfig(M[0]);
|
||||
R0:M[1] -> IMA0.T0 || R5:WriteConf(Mfetch)->KI[0-3];
|
||||
R0:M[1] -> IMA1.T0 || R2:M[2] -> BIU2.T0;
|
||||
R2:M[1] -> IMA2.T0 || R3:M[3] -> BIU3.T1;
|
||||
R0:M[10] -> IMA0.T1 ||R2:M[1] -> IMA3.T0 ;
|
||||
R0:M[11] -> IMA0.T2 || R1: M[10] -> IMA1.T2 || R2: M[10] -> IMA2.T3 || R3: M[10] -> IMA3.T4 || IMA0:SetShiftMode(T0) -> SHIFTMODE0;//load factor to IMA
|
||||
R0:M[12] -> IMA0.T3 || R1: M[11] -> IMA1.T3 || R2: M[11] -> IMA2.T4 || R3: M[11] -> IMA3.T1 || IMA1:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
R0:M[13] -> IMA0.T4 || R1: M[12] -> IMA1.T4 || R2: M[12] -> IMA2.T1 || R3: M[12] -> IMA3.T2 || IMA2:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
R1: M[13] -> IMA1.T1 || R2: M[13] -> IMA2.T2 || R3: M[13] -> IMA3.T3 ||IMA3:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:wait 0 ||R0: wait 9 || R2: wait 9 || IMA0: wait 12 ||IMA1: wait 12 || IMA2: wait 12 || IMA3: wait 12 || SHU0: wait 16 || SHU1: wait 16 || SHU2: wait 16 || SHU3: wait 16 ||BIU3: wait 19;
|
||||
MFetch:LPTO %BLOCK @(KI0 - 0);
|
||||
BIU2:Load(T0)(A++) -> M[20] || R0: M[20] -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0;
|
||||
R0: M[20] -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0;
|
||||
R2: M[20] -> IMA2.T0 || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0;
|
||||
R2: M[20] -> IMA3.T0 || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0;
|
||||
BIU2:Load(T0)(A++) -> M[21] || R0: M[21] -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || SHU0: T0+T1(S) -> SHU0.T2;
|
||||
R0: M[21] -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || SHU1: T0+T1(S) -> SHU1.T2;
|
||||
R2: M[21] -> IMA2.T0 || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1 || SHU2: T0+T1(S) -> SHU2.T2;
|
||||
R2: M[21] -> IMA3.T0 || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1 || SHU3: T0+T1(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[22] || R0: M[22] -> IMA0.T0 ||IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[22] -> IMA1.T0 ||IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[22] -> IMA2.T0 ||IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[22] -> IMA3.T0 ||IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[23] || R0: M[23] -> IMA0.T0 ||IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0 || SHU0: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R0: M[23] -> IMA1.T0 ||IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0 || SHU1: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[23] -> IMA2.T0 ||IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0 || SHU2: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[23] -> IMA3.T0 ||IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0 || SHU3: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BLOCK:
|
||||
BIU2:wait 0 ||R0: wait 0 || R2: wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
/*
|
||||
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
|
||||
MFetch:LPTO %BLOCK @(KI0 - 0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) ||IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) ||IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) ||IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) ||IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) ||IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) ||IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) ||IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) ||IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0;
|
||||
BIU2:Load(T0) -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0;
|
||||
BIU2:Load(T0) -> IMA2.T0 || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0;
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0 || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0;
|
||||
BIU2:Load(T0) -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || SHU0: T0+T1(S) -> SHU0.T2;
|
||||
BIU2:Load(T0) -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || SHU1: T0+T1(S) -> SHU1.T2;
|
||||
BIU2:Load(T0) -> IMA2.T0 || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1 || SHU2: T0+T1(S) -> SHU2.T2;
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0 || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1 || SHU3: T0+T1(S) -> SHU3.T2;
|
||||
BIU2:Load(T0) -> IMA0.T0 ||IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
BIU2:Load(T0) -> IMA1.T0 ||IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
BIU2:Load(T0) -> IMA2.T0 ||IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0 ||IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0) -> IMA0.T0 ||IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0 || SHU0: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BIU2:Load(T0) -> IMA1.T0 ||IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0 || SHU1: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BIU2:Load(T0) -> IMA2.T0 ||IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0 || SHU2: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0 ||IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0 || SHU3: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BLOCK:
|
||||
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
|
||||
*/
|
||||
MFetch:REPEAT @(35);
|
||||
MFetch:MPU.STOP;
|
||||
|
@ -11,108 +11,110 @@ Transform8Asm:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
|
||||
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
|
||||
BIU1:Load(T0)(A++) -> M[12](Mode0); //factor3
|
||||
BIU1:Load(T0)(A++) -> M[13](Mode0); //factor4
|
||||
BIU1:Load(T0)(A++) -> M[14](Mode0); //factor5
|
||||
BIU1:Load(T0)(A++) -> M[15](Mode0); //factor6
|
||||
BIU1:Load(T0)(A++) -> M[16](Mode0) || R5:PreConfig(M[0])(Mode0);//factor 7
|
||||
BIU1:Load(T0)(A++) -> M[17](Mode0) || R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);//factor 8
|
||||
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0) || R5:WriteConf(Mfetch)->KI[4-7](Mode0);
|
||||
R2:M[1] -> IMA2.T0(Mode0) || R3:M[3] -> BIU3.T1(Mode0) ;
|
||||
R0:M[10] -> IMA0.T1(Mode0) ||R2:M[1] -> IMA3.T0(Mode0) ;
|
||||
R0:M[11] -> IMA0.T2(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || R2: M[10] -> IMA2.T3(Mode0) || R3: M[10] -> IMA3.T4(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
|
||||
R0:M[12] -> IMA0.T3(Mode0) || R1: M[11] -> IMA1.T3(Mode0) || R2: M[11] -> IMA2.T4(Mode0) ||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R0:M[13] -> IMA0.T4(Mode0) || R1: M[12] -> IMA1.T4(Mode0) || IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R3: M[15] -> IMA3.T1(Mode0);
|
||||
R2: M[16] -> IMA2.T1(Mode0) || R3: M[16] -> IMA3.T2(Mode0);
|
||||
R1: M[17] -> IMA1.T1(Mode0) || R2: M[17] -> IMA2.T2(Mode0) || R3: M[17] -> IMA3.T3(Mode0);
|
||||
BIU1:Load(T0)(A++) -> M[0]; //KI
|
||||
BIU1:Load(T0)(A++) -> M[1]; //ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[2]; //Input
|
||||
BIU1:Load(T0)(A++) -> M[3]; //Output
|
||||
BIU1:Load(T0)(A++) -> M[10]; //factor1
|
||||
BIU1:Load(T0)(A++) -> M[11]; //factor2
|
||||
BIU1:Load(T0)(A++) -> M[12]; //factor3
|
||||
BIU1:Load(T0)(A++) -> M[13]; //factor4
|
||||
BIU1:Load(T0)(A++) -> M[14]; //factor5
|
||||
BIU1:Load(T0)(A++) -> M[15]; //factor6
|
||||
BIU1:Load(T0)(A++) -> M[16] || R5:PreConfig(M[0]);//factor 7
|
||||
BIU1:Load(T0)(A++) -> M[17] || R0:M[1] -> IMA0.T0 || R5:WriteConf(Mfetch)->KI[0-3];//factor 8
|
||||
R0:M[1] -> IMA1.T0 || R2:M[2] -> BIU2.T0 || R5:WriteConf(Mfetch)->KI[4-7];
|
||||
R2:M[1] -> IMA2.T0 || R3:M[3] -> BIU3.T1 ;
|
||||
R0:M[10] -> IMA0.T1 ||R2:M[1] -> IMA3.T0 ;
|
||||
R0:M[11] -> IMA0.T2 || R1: M[10] -> IMA1.T2 || R2: M[10] -> IMA2.T3 || R3: M[10] -> IMA3.T4 || IMA0:SetShiftMode(T0) -> SHIFTMODE0;//load factor to IMA
|
||||
R0:M[12] -> IMA0.T3 || R1: M[11] -> IMA1.T3 || R2: M[11] -> IMA2.T4 ||IMA1:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
R0:M[13] -> IMA0.T4 || R1: M[12] -> IMA1.T4 || IMA2:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
IMA3:SetShiftMode(T0) -> SHIFTMODE0;
|
||||
R3: M[15] -> IMA3.T1;
|
||||
R2: M[16] -> IMA2.T1 || R3: M[16] -> IMA3.T2;
|
||||
R1: M[17] -> IMA1.T1 || R2: M[17] -> IMA2.T2 || R3: M[17] -> IMA3.T3;
|
||||
|
||||
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || R0: wait 10 || R1: wait 10 || R2: wait 10 || R3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:wait 0 || R0: wait 9 || R2: wait 9 || IMA0: wait 12 ||IMA1: wait 12 || IMA2: wait 12 || IMA3: wait 12 || R1: wait 12 || R3: wait 12 || SHU0: wait 16 || SHU1: wait 16 || SHU2: wait 16 || SHU3: wait 16 ||BIU3: wait 19;
|
||||
MFetch:LPTO %BLOCK_0 @(KI0 - 0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || R0: M[14] -> IMA0.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || R1: M[13] -> IMA1.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || R2: M[12] -> IMA2.T1(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || R3: M[11] -> IMA3.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || R0: M[15] -> IMA0.T2(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || R1: M[14] -> IMA1.T2(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || R2: M[13] -> IMA2.T2(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || R3: M[12] -> IMA3.T2(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[16] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[15] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[14] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[13] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[17] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[16] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[15] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[14] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[10] -> IMA0.T1(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[17] -> IMA1.T1(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[16] -> IMA2.T1(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[15] -> IMA3.T1(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[11] -> IMA0.T2(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[10] -> IMA1.T2(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[17] -> IMA2.T2(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[16] -> IMA3.T2(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[12] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[11] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[10] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[17] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0)|| R0: M[13] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0)|| R1: M[12] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0)|| R2: M[11] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0)|| R3: M[10] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> M[20] || R0: M[20] -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0 || R1: M[14] -> IMA0.T1;
|
||||
R0: M[20] -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0 || R1: M[13] -> IMA1.T1;
|
||||
R2: M[20] -> IMA2.T0 || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0 || R3: M[12] -> IMA2.T1;
|
||||
R2: M[20] -> IMA3.T0 || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0 || R3: M[11] -> IMA3.T1;
|
||||
BIU2:Load(T0)(A++) -> M[21] || R0: M[21] -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || R1: M[15] -> IMA0.T2 || SHU0: T0+T1(S) -> SHU0.T2;
|
||||
R0: M[21] -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || R1: M[14] -> IMA1.T2 || SHU1: T0+T1(S) -> SHU1.T2;
|
||||
R2: M[21] -> IMA2.T0 || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1 || R3: M[13] -> IMA2.T2 || SHU2: T0+T1(S) -> SHU2.T2;
|
||||
R2: M[21] -> IMA3.T0 || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1 || R3: M[12] -> IMA3.T2 || SHU3: T0+T1(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[22] || R0: M[22] -> IMA0.T0 || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[16] -> IMA0.T3 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[22] -> IMA1.T0 || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[15] -> IMA1.T3 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[22] -> IMA2.T0 || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[14] -> IMA2.T3 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[22] -> IMA3.T0 || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[13] -> IMA3.T3 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[23] || R0: M[23] -> IMA0.T0 || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[17] -> IMA0.T4 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[23] -> IMA1.T0 || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[16] -> IMA1.T4 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[23] -> IMA2.T0 || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[15] -> IMA2.T4 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[23] -> IMA3.T0 || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[14] -> IMA3.T4 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[24] || R0: M[24] -> IMA0.T0 || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[10] -> IMA0.T1 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[24] -> IMA1.T0 || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[17] -> IMA1.T1 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[24] -> IMA2.T0 || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[16] -> IMA2.T1 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[24] -> IMA3.T0 || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[15] -> IMA3.T1 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[25] || R0: M[25] -> IMA0.T0 || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[11] -> IMA0.T2 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[25] -> IMA1.T0 || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[10] -> IMA1.T2 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[25] -> IMA2.T0 || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[17] -> IMA2.T2 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[25] -> IMA3.T0 || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[16] -> IMA3.T2 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[26] || R0: M[26] -> IMA0.T0 || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[12] -> IMA0.T3 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[26] -> IMA1.T0 || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[11] -> IMA1.T3 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[26] -> IMA2.T0 || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[10] -> IMA2.T3 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[26] -> IMA3.T0 || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[17] -> IMA3.T3 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[27] || R0: M[27] -> IMA0.T0 || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0|| R1: M[13] -> IMA0.T4 || SHU0: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R0: M[27] -> IMA1.T0 || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0|| R1: M[12] -> IMA1.T4 || SHU1: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[27] -> IMA2.T0 || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0|| R3: M[11] -> IMA2.T4 || SHU2: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[27] -> IMA3.T0 || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0|| R3: M[10] -> IMA3.T4 || SHU3: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BLOCK_0:
|
||||
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R0: wait 0 || R1: wait 0 || R2: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
BIU2:wait 0 || R0: wait 0 || R2: wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R1: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
|
||||
MFetch:REPEAT @(20);
|
||||
R0:M[14] -> IMA0.T1(Mode0) || R1:M[13] -> IMA1.T1(Mode0) || R2:M[12] -> IMA2.T1(Mode0) || R3:M[11] -> IMA3.T1(Mode0);
|
||||
R0:M[15] -> IMA0.T2(Mode0) || R1:M[14] -> IMA1.T2(Mode0) || R2:M[13] -> IMA2.T2(Mode0) || R3:M[12] -> IMA3.T2(Mode0);
|
||||
R0:M[16] -> IMA0.T3(Mode0) || R1:M[15] -> IMA1.T3(Mode0) || R2:M[14] -> IMA2.T3(Mode0) || R3:M[13] -> IMA3.T3(Mode0);
|
||||
R0:M[17] -> IMA0.T4(Mode0) || R1:M[16] -> IMA1.T4(Mode0) || R2:M[15] -> IMA2.T4(Mode0) || R3:M[14] -> IMA3.T4(Mode0);
|
||||
R0:M[14] -> IMA0.T1 || R1:M[13] -> IMA1.T1 || R2:M[12] -> IMA2.T1 || R3:M[11] -> IMA3.T1;
|
||||
R0:M[15] -> IMA0.T2 || R1:M[14] -> IMA1.T2 || R2:M[13] -> IMA2.T2 || R3:M[12] -> IMA3.T2;
|
||||
R0:M[16] -> IMA0.T3 || R1:M[15] -> IMA1.T3 || R2:M[14] -> IMA2.T3 || R3:M[13] -> IMA3.T3;
|
||||
R0:M[17] -> IMA0.T4 || R1:M[16] -> IMA1.T4 || R2:M[15] -> IMA2.T4 || R3:M[14] -> IMA3.T4;
|
||||
|
||||
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || R0: wait 10 || R1: wait 10 || R2: wait 10 || R3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
|
||||
BIU2:wait 0 || R0: wait 9 || R2: wait 9 || IMA0: wait 12 ||IMA1: wait 12 || IMA2: wait 12 || IMA3: wait 12 || R1: wait 12 || R3: wait 12 || SHU0: wait 16 || SHU1: wait 16 || SHU2: wait 16 || SHU3: wait 16 ||BIU3: wait 19;
|
||||
MFetch:LPTO %BLOCK_1 @(KI0 - 0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || R0: M[10] -> IMA0.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || R1: M[17] -> IMA1.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || R2: M[16] -> IMA2.T1(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || R3: M[15] -> IMA3.T1(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || R0: M[11] -> IMA0.T2(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || R2: M[17] -> IMA2.T2(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || R3: M[16] -> IMA3.T2(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[12] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[11] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[10] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[17] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[13] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[12] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[11] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[10] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[14] -> IMA0.T1(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[13] -> IMA1.T1(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[12] -> IMA2.T1(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[11] -> IMA3.T1(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[15] -> IMA0.T2(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[14] -> IMA1.T2(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[13] -> IMA2.T2(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[12] -> IMA3.T2(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[16] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[15] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[14] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[13] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
|
||||
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0)|| R0: M[17] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0)|| R1: M[16] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0)|| R2: M[15] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0)|| R3: M[14] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
|
||||
BIU2:Load(T0)(A++) -> M[30] || R0: M[30] -> IMA0.T0 || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0 || R1: M[10] -> IMA0.T1;
|
||||
R0: M[30] -> IMA1.T0 || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0 || R1: M[17] -> IMA1.T1;
|
||||
R2: M[30] -> IMA2.T0 || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0 || R3: M[16] -> IMA2.T1;
|
||||
R2: M[30] -> IMA3.T0 || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0 || R3: M[15] -> IMA3.T1;
|
||||
BIU2:Load(T0)(A++) -> M[31] || R0: M[31] -> IMA0.T0 || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1 || R1: M[11] -> IMA0.T2 || SHU0: T0+T1(S) -> SHU0.T2;
|
||||
R0: M[31] -> IMA1.T0 || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1 || R1: M[10] -> IMA1.T2 || SHU1: T0+T1(S) -> SHU1.T2;
|
||||
R2: M[31] -> IMA2.T0 || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1 || R3: M[17] -> IMA2.T2 || SHU2: T0+T1(S) -> SHU2.T2;
|
||||
R2: M[31] -> IMA3.T0 || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1 || R3: M[16] -> IMA3.T2 || SHU3: T0+T1(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[32] || R0: M[32] -> IMA0.T0 || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[12] -> IMA0.T3 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[32] -> IMA1.T0 || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[11] -> IMA1.T3 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[32] -> IMA2.T0 || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[10] -> IMA2.T3 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[32] -> IMA3.T0 || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[17] -> IMA3.T3 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[33] || R0: M[33] -> IMA0.T0 || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[13] -> IMA0.T4 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[33] -> IMA1.T0 || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[12] -> IMA1.T4 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[33] -> IMA2.T0 || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[11] -> IMA2.T4 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[33] -> IMA3.T0 || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[10] -> IMA3.T4 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[34] || R0: M[34] -> IMA0.T0 || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[14] -> IMA0.T1 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[34] -> IMA1.T0 || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[13] -> IMA1.T1 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[34] -> IMA2.T0 || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[12] -> IMA2.T1 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[34] -> IMA3.T0 || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[11] -> IMA3.T1 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[35] || R0: M[35] -> IMA0.T0 || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[15] -> IMA0.T2 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[35] -> IMA1.T0 || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[14] -> IMA1.T2 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[35] -> IMA2.T0 || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[13] -> IMA2.T2 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[35] -> IMA3.T0 || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[12] -> IMA3.T2 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[36] || R0: M[36] -> IMA0.T0 || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0|| R1: M[16] -> IMA0.T3 || SHU0: T2+T0(S) -> SHU0.T2;
|
||||
R0: M[36] -> IMA1.T0 || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0|| R1: M[15] -> IMA1.T3 || SHU1: T2+T0(S) -> SHU1.T2;
|
||||
R2: M[36] -> IMA2.T0 || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0|| R3: M[14] -> IMA2.T3 || SHU2: T2+T0(S) -> SHU2.T2;
|
||||
R2: M[36] -> IMA3.T0 || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0|| R3: M[13] -> IMA3.T3 || SHU3: T2+T0(S) -> SHU3.T2;
|
||||
BIU2:Load(T0)(A++) -> M[37] || R0: M[37] -> IMA0.T0 || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0|| R1: M[17] -> IMA0.T4 || SHU0: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R0: M[37] -> IMA1.T0 || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0|| R1: M[16] -> IMA1.T4 || SHU1: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[37] -> IMA2.T0 || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0|| R3: M[15] -> IMA2.T4 || SHU2: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
R2: M[37] -> IMA3.T0 || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0|| R3: M[14] -> IMA3.T4 || SHU3: T2+T0(S) -> BIU3.T0 || BIU3:Store(T0,T1)(A++);
|
||||
BLOCK_1:
|
||||
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R0: wait 0 || R1: wait 0 || R2: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
BIU2:wait 0 || R0: wait 0 || R2: wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R1: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
|
||||
|
||||
MFetch:REPEAT @(35);
|
||||
MFetch:MPU.STOP;
|
||||
|
@ -360,6 +360,54 @@ void Transform(int ConfigAddr, int InAddr, int OutAddr, int N, double* db_real,
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void RowCopy(int* Matrix,int* Block,int idx,int direct)
|
||||
{
|
||||
int RowOffset = 4096*2;
|
||||
//idx from 0 to 6
|
||||
int BaseAddr = RowOffset*idx;
|
||||
if(direct == 1)
|
||||
{
|
||||
//load data from Matrix
|
||||
for(int i = BaseAddr;i<BaseAddr+RowOffset;i++)
|
||||
{
|
||||
Block[i-BaseAddr] = Matrix[i];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//store data to Matrix
|
||||
for(int i = BaseAddr;i<BaseAddr+RowOffset;i++)
|
||||
{
|
||||
Matrix[i] = Block[i-BaseAddr];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ColCopy(int* Matrix,int* Block,int idx,int direct)
|
||||
{
|
||||
int ColOffset = 512;
|
||||
int RowOffset = 4096;
|
||||
int BaseAddr = idx*ColOffset;
|
||||
|
||||
if(direct == 1)
|
||||
{
|
||||
for(int i = 0;i<14;i++){
|
||||
for(int j = 0;j<ColOffset;j++)
|
||||
{
|
||||
Block[j+i*ColOffset] = Matrix[BaseAddr+i*RowOffset+j];
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for(int i = 0;i<14;i++){
|
||||
for(int j = 0;j<ColOffset;j++)
|
||||
{
|
||||
Matrix[BaseAddr+i*RowOffset+j] = Block[j+i*ColOffset];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -5,21 +5,29 @@
|
||||
#include "ucp2_utils.h"
|
||||
#include <Transform.h>
|
||||
#include <stdlib.h>
|
||||
//_DM2 int InputData000[10028] = {0};
|
||||
#define IDE_TEST 1
|
||||
|
||||
__DM0 int InputData[] = {
|
||||
#include <Input_mod.dat>
|
||||
//#include <Input_mod.dat>
|
||||
#include <Input_0.dat>
|
||||
};
|
||||
__DM0 int PilotData[] = {
|
||||
//#include <Input_mod.dat>
|
||||
#include <Input_pilot.dat>
|
||||
};
|
||||
#ifdef IDE_TEST
|
||||
__DM4 int TransTemp[4096*14] = {0};
|
||||
__DM2 int OutData[4096*14]={};
|
||||
__DM2 int PilotTrans[1024]={};
|
||||
__DM3 int DeTrans[4096*14]={};
|
||||
#endif
|
||||
|
||||
__DM2 int PilotTrans[1024]={};
|
||||
__DM3 int PilotDeTrans[1024]={};
|
||||
|
||||
__DM4 int RowIn[4096*2] = {};
|
||||
__DM1 int RowOut[4096*2] = {};
|
||||
__DM2 int ColIn[14*512] = {};
|
||||
__DM1 int ColOut[14*512] = {};
|
||||
|
||||
//now for data transform:
|
||||
//inputdata size is 2*4096
|
||||
//tempdata size is 2*4096
|
||||
@ -52,6 +60,7 @@ __DM3 int DeTransConfig_8[] = {
|
||||
#include <DeTransformConfig_8.dat>
|
||||
};
|
||||
|
||||
|
||||
__DM3 v16s32 SVRReg = {
|
||||
0, 0, 0, 0,
|
||||
0x40, 0, 0, 0,
|
||||
@ -77,7 +86,7 @@ int main(void)
|
||||
}
|
||||
/*****************************************initial*****************************************/
|
||||
/*****************************************Transmit loop*****************************************/
|
||||
int Loop_Num = 4;
|
||||
int Loop_Num = 1;
|
||||
for(int iLoop = 0;iLoop < Loop_Num;iLoop++){
|
||||
printf("Loop[%0d] starting\n",iLoop);
|
||||
get_thita(current_state,thita);
|
||||
@ -86,61 +95,102 @@ int main(void)
|
||||
thita3 = thita + 2;
|
||||
|
||||
|
||||
//data test
|
||||
/******************forward tarnsform*****************************/
|
||||
//symbol transform, need to import data(14*512) 8 times
|
||||
printf("starting Data Transfrom\n");
|
||||
for(int iSym = 0;iSym < 8;iSym++){
|
||||
//*********Important:import data 'InputData' to DM at here
|
||||
//'InputData' size is 14*512 point equals to 14*512*32bit
|
||||
Transform((int)Config_2,MPU_ADDR(InputData),MPU_ADDR(TransTemp), 2, thita2, 1);
|
||||
|
||||
#ifdef IDE_TEST
|
||||
ColCopy(InputData,ColIn,iSym,1);
|
||||
#else
|
||||
//*********Important:import data 'ColIn' to DM at here
|
||||
//'ColIn' size is 14*512 point equals to 14*512*32bit
|
||||
//here need move data to DM data(ColIn)
|
||||
#endif
|
||||
Transform((int)Config_2,MPU_ADDR(ColIn),MPU_ADDR(ColOut), 2, thita2, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
#ifdef IDE_TEST
|
||||
ColCopy(TransTemp,ColOut,iSym,-1);
|
||||
#else
|
||||
//*********Important:transfer DM data 'ColOut' out at here
|
||||
//'ColOut' size is 14*512 point equals to 14*512*32bit
|
||||
//here need move DM data(ColOut) out
|
||||
#endif
|
||||
|
||||
//*********Important:transfer DM data 'TransTemp' out at here
|
||||
//'TransTemp' size is 14*512 point equals to 14*512*32bit
|
||||
}
|
||||
|
||||
//data transform
|
||||
for(int iBlk = 0; iBlk < 7; iBlk++){
|
||||
//*********Important:import data 'TransTemp' to DM at here
|
||||
#ifdef IDE_TEST
|
||||
RowCopy(TransTemp,RowIn,iBlk,1);
|
||||
#else
|
||||
//*********Important:import data 'RowIn' to DM at here
|
||||
//data block size is 2*4096 point equals to 2*4096*32bit
|
||||
Transform((int)Config_4,MPU_ADDR(TransTemp),MPU_ADDR(OutData), 4, thita3, 1);
|
||||
//here need move data to DM data(RowIn)
|
||||
#endif
|
||||
Transform((int)Config_4,MPU_ADDR(RowIn),MPU_ADDR(RowOut), 4, thita3, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_4);
|
||||
Transform4Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
#ifdef IDE_TEST
|
||||
RowCopy(OutData,RowOut,iBlk,-1);
|
||||
#else
|
||||
//*********Important:transfer data 'RowOut' to DM at here
|
||||
//'RowOut' size is 2*4096 point equals to 2*4096*32bit
|
||||
//here need move DM data(RowOut) out
|
||||
#endif
|
||||
|
||||
|
||||
//*********Important:import data 'OutData' to DM at here
|
||||
//'OutData' size is 2*4096 point equals to 2*4096*32bit
|
||||
}
|
||||
/******************forward tarnsform*****************************/
|
||||
|
||||
|
||||
/*********************detarnsform********************************/
|
||||
//data detrans
|
||||
for(int iBlk = 0;iBlk < 7;iBlk++){
|
||||
//*********Important:import data 'OutData' to DM at here
|
||||
//'OutData' size is 2*4096 point equals to 2*4096*32bit
|
||||
Transform((int)DeTransConfig_4,MPU_ADDR(OutData),MPU_ADDR(TransTemp), 4, thita3, -1);
|
||||
#ifdef IDE_TEST
|
||||
RowCopy(OutData,RowIn,iBlk,1);
|
||||
#else
|
||||
//*********Important:import data 'RowIn' to DM at here
|
||||
//'RowIn' size is 2*4096 point equals to 2*4096*32bit
|
||||
#endif
|
||||
|
||||
Transform((int)DeTransConfig_4,MPU_ADDR(RowIn),MPU_ADDR(RowOut), 4, thita3, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_4);
|
||||
Transform4Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
//*********Important:import data 'TransTemp' to DM at here
|
||||
//'TransTemp' size is 2*4096 point equals to 2*4096*32bit
|
||||
#ifdef IDE_TEST
|
||||
RowCopy(TransTemp,RowOut,iBlk,-1);
|
||||
#else
|
||||
//*********Important:transfer DM data 'RowOut' outside at here
|
||||
//'RowOut' size is 2*4096 point equals to 2*4096*32bit
|
||||
#endif
|
||||
|
||||
}
|
||||
//symbol detrans
|
||||
for(int iSym = 0;iSym < 8;iSym++){
|
||||
//*********Important:import data 'TransTemp' to DM at here
|
||||
//'TransTemp' size is 14*512 point equals to 14*512*32bit
|
||||
Transform((int)DeTransConfig_2,MPU_ADDR(TransTemp),MPU_ADDR(DeTrans), 2, thita2, -1);
|
||||
#ifdef IDE_TEST
|
||||
ColCopy(TransTemp,ColIn,iSym,1);
|
||||
#else
|
||||
//*********Important:import data 'ColIn' to DM at here
|
||||
//'ColIn' size is 14*512 point equals to 14*512*32bit
|
||||
#endif
|
||||
Transform((int)DeTransConfig_2,MPU_ADDR(ColIn),MPU_ADDR(ColOut), 2, thita2, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
//*********Important:transfer DM data 'DeTrans' out at here
|
||||
//'DeTrans' size is 14*512 point equals to 14*512*32bit
|
||||
#ifdef IDE_TEST
|
||||
ColCopy(DeTrans,ColOut,iSym,-1);
|
||||
#else
|
||||
//*********Important:transfer DM data 'ColOut' out at here
|
||||
//'ColOut' size is 14*512 point equals to 14*512*32bit
|
||||
#endif
|
||||
|
||||
|
||||
}
|
||||
|
||||
for(int i = 0;i<16; i++){
|
||||
@ -155,24 +205,17 @@ int main(void)
|
||||
|
||||
printf("starting Pilot Transfrom\n");
|
||||
//pilot size is 1*1024,do not need to divide to more blocks
|
||||
/***************************pilot transform******************************/
|
||||
Transform((int)Config_8,MPU_ADDR(PilotData),MPU_ADDR(PilotTrans), 8, thita1, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_8);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform8Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
/***************************pilot transform******************************/
|
||||
|
||||
Transform((int)DeTransConfig_8,MPU_ADDR(PilotTrans),MPU_ADDR(PilotDeTrans), 8, thita1, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_8);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform8Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
for(int i = 0;i<16; i++){
|
||||
@ -185,134 +228,6 @@ int main(void)
|
||||
|
||||
printf("Loop[%0d] finishing\n",iLoop);
|
||||
}
|
||||
/*****************************************Transmit loop*****************************************/
|
||||
/*
|
||||
//data test
|
||||
//symbol transform
|
||||
N = 2;
|
||||
Transform((int)Config_2,MPU_ADDR(InputData),MPU_ADDR(TransTemp), N, cs, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
//data transform
|
||||
N = 4;
|
||||
Transform((int)Config_4,MPU_ADDR(TransTemp),MPU_ADDR(OutData), N, cs, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_4);
|
||||
Transform4Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
//data detrans
|
||||
Transform((int)DeTransConfig_4,MPU_ADDR(OutData),MPU_ADDR(TransTemp), N, cs, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_4);
|
||||
Transform4Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
//symbol detrans
|
||||
N = 2;
|
||||
Transform((int)DeTransConfig_2,MPU_ADDR(TransTemp),MPU_ADDR(DeTrans), N, cs, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("SymTrans: Input[%0d]: %x, Detrans[%0d]: %x\n",i,InputData[i],i,DeTrans[i]);
|
||||
}
|
||||
|
||||
int offset = 14*4096-16;
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("Input[%0d]: %x,Detrans[%0d]: %x\n",offset+i,InputData[offset+i],offset+i,DeTrans[offset+i]);
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
//case 2
|
||||
N = 2;
|
||||
Transform((int)Config_2,MPU_ADDR(InputData),MPU_ADDR(OutData), N, cs, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform((int)DeTransConfig_2,MPU_ADDR(OutData),MPU_ADDR(DeTrans), N, cs, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_2);
|
||||
Transform2Asm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
|
||||
__ucps2_delay();
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("Input[%0d]: %x, Detrans[%0d]: %x\n",i*16,InputData[i*16],i*16,DeTrans[i*16]);
|
||||
}
|
||||
int offset = 14*4096-16;
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("Input[%0d]: %x,Detrans[%0d]: %x\n",offset+i,InputData[offset+i],offset+i,DeTrans[offset+i]);
|
||||
}
|
||||
|
||||
|
||||
//case 4
|
||||
N = 4;
|
||||
Transform((int)Config_4,MPU_ADDR(InputData),MPU_ADDR(OutData), N, cs, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_4);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform4Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
|
||||
Transform((int)DeTransConfig_4,MPU_ADDR(OutData),MPU_ADDR(DeTrans), N, cs, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_4);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform4Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("Input[%0d]: %x, Detrans[%0d]: %x\n",i*16,InputData[i*16],i*16,DeTrans[i*16]);
|
||||
}
|
||||
int offset = 14*4096-16*16;
|
||||
for(int i = 0;i<16; i++){
|
||||
printf("Input[%0d]: %x,Detrans[%0d]: %x\n",offset+i*16,InputData[offset+i*16],offset+i*16,DeTrans[offset+i*16]);
|
||||
}
|
||||
|
||||
|
||||
//case 8
|
||||
N = 8;
|
||||
Transform((int)Config_8,MPU_ADDR(PilotData),MPU_ADDR(PilotTrans), N, cs, 1);
|
||||
SVRReg[0] = MPU_ADDR(Config_8);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform8Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
|
||||
Transform((int)DeTransConfig_8,MPU_ADDR(PilotTrans),MPU_ADDR(PilotDeTrans), N, cs, -1);
|
||||
SVRReg[0] = MPU_ADDR(DeTransConfig_8);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
Transform8Asm(SVRReg);
|
||||
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
for(int i = 0;i<1024; i=i+16){
|
||||
printf("Input[%0d]: %x, Detrans[%0d]: %x\n",i,PilotData[i],i,PilotDeTrans[i]);
|
||||
}
|
||||
*/
|
||||
|
||||
return a;
|
||||
}
|
||||
|
||||
|
@ -5,9 +5,11 @@
|
||||
void AgcShiftForFftInt32(int ConfigAddr,int InAddr_1,int InAddr_2,int ReNum,int nSyms,
|
||||
int AgcAddr_1,int AgcAddr_2,int OutAddr_1,int OutAddr_2)
|
||||
{
|
||||
|
||||
for(int ii=0;ii<16;ii++){
|
||||
AgcAddr_1[ii] = 1;
|
||||
//TODO:待确认修改方式是否正确 20250528
|
||||
int ii;
|
||||
int* AgcAddr_1_ptr = (int*)AgcAddr_1;
|
||||
for(ii=0;ii<16;ii++){
|
||||
AgcAddr_1_ptr[ii] = 1;
|
||||
}
|
||||
int *Para = (int *)ConfigAddr;
|
||||
int temp0 = (ReNum+15)>>4;
|
||||
|
8
MicroCode/Sliding/.mapu
Normal file
8
MicroCode/Sliding/.mapu
Normal file
@ -0,0 +1,8 @@
|
||||
{
|
||||
"project": {
|
||||
"incList": [
|
||||
"../inc"
|
||||
],
|
||||
"libList": []
|
||||
}
|
||||
}
|
@ -1,38 +1,39 @@
|
||||
|
||||
//ShiftMode
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000007,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
|
||||
//InputA
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0x04000400,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//InputB
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -51,12 +52,12 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output
|
||||
//Maxdata
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -70,20 +71,37 @@
|
||||
0x00000000,
|
||||
|
||||
//KI0
|
||||
0x00000001,
|
||||
0x00000400,
|
||||
0x0000001f,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Index1
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
||||
0x01010000,
|
1055
MicroCode/Sliding/inc/Inputdata1.dat
Normal file
1055
MicroCode/Sliding/inc/Inputdata1.dat
Normal file
File diff suppressed because it is too large
Load Diff
1024
MicroCode/Sliding/inc/Inputdata2.dat
Normal file
1024
MicroCode/Sliding/inc/Inputdata2.dat
Normal file
File diff suppressed because it is too large
Load Diff
8
MicroCode/Sliding/inc/Sliding.h
Normal file
8
MicroCode/Sliding/inc/Sliding.h
Normal file
@ -0,0 +1,8 @@
|
||||
#ifndef SLIDING_H_
|
||||
#define SLIDING_H_
|
||||
#include "ucps2.h"
|
||||
|
||||
MPU_ENTRY void SlidingAsm(v16u32 src);
|
||||
void Sliding(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr);
|
||||
|
||||
#endif /* SLIDING_H_ */
|
61440
MicroCode/Sliding/inc/timedatasym.dat
Normal file
61440
MicroCode/Sliding/inc/timedatasym.dat
Normal file
File diff suppressed because it is too large
Load Diff
20
MicroCode/Sliding/makefile.init
Normal file
20
MicroCode/Sliding/makefile.init
Normal file
@ -0,0 +1,20 @@
|
||||
# set custom targets
|
||||
|
||||
# set toolchain home
|
||||
ifeq ($(strip $(MaPU_TC_HOME)),)
|
||||
MaPU_TC_HOME := /home/ide/IDE/MaPUIDE/toolchain
|
||||
endif
|
||||
|
||||
APP: all
|
||||
|
||||
LIB: libtest_sync.a
|
||||
|
||||
libtest_sync.a: $(OBJS)
|
||||
@echo 'Building target: $@'
|
||||
@echo 'Invoking: GNU archiver'
|
||||
ar rcs $@ $(OBJS)
|
||||
@echo 'Finished building target: $@'
|
||||
@echo ' '
|
||||
|
||||
|
||||
.PHONY: LIB APP
|
116
MicroCode/Sliding/src/mpu0/SlidingAsm.m0.asm
Normal file
116
MicroCode/Sliding/src/mpu0/SlidingAsm.m0.asm
Normal file
@ -0,0 +1,116 @@
|
||||
.section .text.m0, "ax"
|
||||
.file "SlidingAsm.m0.asm"
|
||||
// DO NOT MODIFY THE CONTENT ABOVE
|
||||
|
||||
.global SlidingAsm
|
||||
SlidingAsm:
|
||||
R1:M[0]->BIU1.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0)|| SHU0:VImm(0) -> SHU0.T4(Mode0);//ShiftMode0
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0);//Output
|
||||
BIU1:Load(T0)(A++) -> M[63](Mode0);//ki
|
||||
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//Index
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
R0:M[0] -> IMA0.T0(Mode0)||R1:M[4] -> IMA0.T1(Mode0);
|
||||
R0:M[0] -> IMA1.T0(Mode0)||R1:M[4] -> IMA1.T1(Mode0);
|
||||
R2:M[0] -> IMA2.T0(Mode0)||R3:M[4] -> IMA2.T1(Mode0);
|
||||
R3:M[0] -> IMA3.T0(Mode0)||R2:M[4] -> IMA3.T1(Mode0);
|
||||
R0:M[1] -> BIU0.T0(Mode0);
|
||||
R3:M[2] -> BIU3.T0(Mode0);
|
||||
R2:M[3] -> BIU2.T0(Mode0);//output1
|
||||
NOP;
|
||||
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
NOP;
|
||||
R5:PreConfig(M[63])(Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
IMA1:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA1.MR(Mode0);
|
||||
IMA2:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA2.MR(Mode0);
|
||||
IMA3:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA3.MR(Mode0);
|
||||
MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
|
||||
BIU3:Load(T0)(A++)-> SHU0.T1(Mode0)||BIU0:Load(T0)(A++)-> IMA0.T2(Mode0);
|
||||
BIU0:Load(T0)(A++)-> IMA1.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
SHU0:Index(T4,T1,T0) -> IMA0.T1(Mode0);
|
||||
SHU0:Index(T4,T1,T0) -> IMA1.T1(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
IMA1:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA1.MR(Mode0);
|
||||
ComplexMult_Loop:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:ReadMR(L)-> IMA2.T0(Mode0)||IMA1:ReadMR(L)-> IMA3.T0(Mode0);//real
|
||||
IMA0:ReadMR(H)-> IMA0.T0(Mode0)||IMA1:ReadMR(H)-> IMA1.T0(Mode0);//imag
|
||||
IMA0:ReadMR(O1)-> IMA2.T2(Mode0)||IMA1:ReadMR(O1)-> IMA3.T2(Mode0);//overflow real
|
||||
IMA0:ReadMR(O2)-> IMA0.T2(Mode0)||IMA1:ReadMR(O2)-> IMA1.T2(Mode0);//overflow imag
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T0>>10(W)(U)->T0||IMA1:T0>>10(W)(U)->T0||IMA2:T0>>10(W)(U)->T0||IMA3:T0>>10(W)(U)->T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T2>>16(W)(U)->T2||IMA1:T2>>16(W)(U)->T2||IMA2:T2>>16(W)(U)->T2||IMA3:T2>>16(W)(U)->T2;
|
||||
IMA0:Ttmp<<22(W)(T)->IMA0.T2||IMA1:Ttmp<<22(W)(T)->IMA1.T2||IMA2:Ttmp<<22(W)(T)->IMA2.T2||IMA3:Ttmp<<22(W)(T)->IMA3.T2;
|
||||
IMA0:T0+Ttmp(W)(U)->T1||IMA1:T0+Ttmp(W)(U)->T1||IMA2:T0+Ttmp(W)(U)->T1||IMA3:T0+Ttmp(W)(U)->T1;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:Abs(T1) (W) -> T1||IMA1:Abs(T1) (W) -> T1||IMA2:Abs(T1) (W) -> T1||IMA3:Abs(T1) (W) -> T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA2:T1->IMA0.T3||IMA3:T1->IMA1.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T1+T3(W)(U)->BIU2.T1;
|
||||
IMA1:T1+T3(W)(U)->BIU2.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:Store(T1,T0)(Mode0)(A++);
|
||||
BIU2:Store(T2,T0)(Mode0)(A++);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:Repeat @(10);
|
||||
MFetch:MPU.STOP;
|
||||
|
BIN
MicroCode/Sliding/src/spu/.main.s.c.swp
Normal file
BIN
MicroCode/Sliding/src/spu/.main.s.c.swp
Normal file
Binary file not shown.
10
MicroCode/Sliding/src/spu/Sliding.s.c
Normal file
10
MicroCode/Sliding/src/spu/Sliding.s.c
Normal file
@ -0,0 +1,10 @@
|
||||
#include <Sliding.h>
|
||||
|
||||
void Sliding(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr) {
|
||||
volatile unsigned int *Para = (volatile unsigned int *)ConfigAddr;
|
||||
|
||||
Para[16*1+0] = InAddr1;
|
||||
Para[16*1+1] = InAddr1;
|
||||
Para[16*2+0] = InAddr2;
|
||||
Para[16*3+0] = MaxAddr;
|
||||
}
|
55
MicroCode/Sliding/src/spu/main.s.c
Normal file
55
MicroCode/Sliding/src/spu/main.s.c
Normal file
@ -0,0 +1,55 @@
|
||||
|
||||
#ifndef REMOVE_MC_TEST
|
||||
|
||||
#include "ucps2.h"
|
||||
//#include "SyncVer.h"
|
||||
#include <Sliding.h>
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#define DATA_SIZE 62464
|
||||
#define CHUNK_SIZE 1024
|
||||
#define WINDOW_SIZE 32 // 理想的窗口大小(前16,后15,加当前位置)
|
||||
|
||||
|
||||
__DM1 int Input1[] = {
|
||||
#include <Inputdata1.dat>
|
||||
};
|
||||
__DM2 int Input2[] = {
|
||||
#include <Inputdata2.dat>
|
||||
};
|
||||
__DM3 int ConfigMatrix[] = {
|
||||
#include "ConfigSliding.dat"
|
||||
};
|
||||
__DM5 int MaxData[32];//bestposition maxsum
|
||||
|
||||
v16u32 KI = { 2, 4, 6 };
|
||||
__DM3 v16s32 SVRReg = {
|
||||
0, 0, 0, 0,
|
||||
0x40, 0, 0, 0,
|
||||
0xff00ff, 0, 0, 0x0000,
|
||||
0xffff, 0x6, 0, 0
|
||||
};
|
||||
int main(void) {
|
||||
int a;
|
||||
int is_synced = 0; // 同步状态标志
|
||||
int maxPosition = 0;
|
||||
int maxsum = 0;
|
||||
|
||||
// 初步同步:执行滑动相关性计算
|
||||
if (!is_synced) {
|
||||
uint32_t time0 = tick();
|
||||
Sliding((int)ConfigMatrix, MPU_ADDR(Input1), MPU_ADDR(Input2), MPU_ADDR(MaxData));
|
||||
SVRReg[0] = MPU_ADDR(ConfigMatrix);
|
||||
SlidingAsm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
int a = 0;
|
||||
for (int i = 0; i < 32; i++) {
|
||||
printf("MaxData[%d] = %#010x\n", i, MaxData[i]);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
@ -1,79 +1,25 @@
|
||||
|
||||
//ShiftMode
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
//InputA
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//InputB
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output1
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -86,8 +32,59 @@
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//InputB
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//InputA2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//InputB2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output2
|
||||
//Output2 useless
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -124,9 +121,9 @@
|
||||
0x00000000,
|
||||
|
||||
//KI0
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00000400,
|
||||
0x00007600,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -141,3 +138,38 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//index1
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//index2
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
@ -1,93 +1,22 @@
|
||||
|
||||
//ShiftMode
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
0x00000238,
|
||||
//InputA
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
//InputB
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
0x00000207,
|
||||
|
||||
//Output
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output1
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Output2
|
||||
//InputA2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -105,7 +34,43 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Maxdata
|
||||
//InputB2
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00020002,
|
||||
0xf000f000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Maxdata read
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000004,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x003fffff,
|
||||
0x0000000e,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//Maxdata write
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -126,7 +91,7 @@
|
||||
//KI0
|
||||
0x00000295,
|
||||
0x00000400,
|
||||
0x00007800,
|
||||
0x00007600,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -141,3 +106,38 @@
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//index1
|
||||
0x02434241,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
//index2
|
||||
0x02424140,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
31232
MicroCode/SlidingCorrelation/inc/Input1_part1.dat
Normal file
31232
MicroCode/SlidingCorrelation/inc/Input1_part1.dat
Normal file
File diff suppressed because it is too large
Load Diff
32256
MicroCode/SlidingCorrelation/inc/Input1_part2.dat
Normal file
32256
MicroCode/SlidingCorrelation/inc/Input1_part2.dat
Normal file
File diff suppressed because it is too large
Load Diff
31232
MicroCode/SlidingCorrelation/inc/Input2_part1.dat
Normal file
31232
MicroCode/SlidingCorrelation/inc/Input2_part1.dat
Normal file
File diff suppressed because it is too large
Load Diff
9453
MicroCode/SlidingCorrelation/inc/Input2_part2.dat
Normal file
9453
MicroCode/SlidingCorrelation/inc/Input2_part2.dat
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,6 +3,6 @@
|
||||
#include "ucps2.h"
|
||||
|
||||
MPU_ENTRY void SlidingCorrelationAsm(v16u32 src);
|
||||
void SlidingCorrelation(int ConfigAddr, int InAddr1, int InAddr2, int OutAddr, int MaxAddr);
|
||||
void SlidingCorrelation(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr);
|
||||
|
||||
#endif /* SLIDINGCORRELATION_H_ */
|
||||
|
@ -3,6 +3,6 @@
|
||||
#include "ucps2.h"
|
||||
|
||||
MPU_ENTRY void SlidingCorrelationSecondAsm(v16u32 src);
|
||||
void SlidingCorrelationSecond(int ConfigAddr, int InAddr1, int InAddr2, int OutAddr, int MaxAddr);
|
||||
void SlidingCorrelationSecond(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr);
|
||||
|
||||
#endif /* SLIDINGCORRELATION_H_ */
|
||||
|
61440
MicroCode/SlidingCorrelation/inc/timedatasym.dat
Normal file
61440
MicroCode/SlidingCorrelation/inc/timedatasym.dat
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,27 +1,24 @@
|
||||
.section .text.m0, "ax"
|
||||
.file "SlidingCorrelation.m0.asm"
|
||||
.file "SlidingCorrelationAsm.m0.asm"
|
||||
// DO NOT MODIFY THE CONTENT ABOVE
|
||||
|
||||
.global SlidingCorrelationAsm
|
||||
SlidingCorrelationAsm:
|
||||
|
||||
|
||||
R1:M[0]->BIU1.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0);//ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0);
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0);//Output store result
|
||||
BIU1:Load(T0)(A++) -> M[4](Mode0);//Output1 sum the first 1024 vector
|
||||
BIU1:Load(T0)(A++) -> M[5](Mode0);//Output2 slide window
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0);//InputA2
|
||||
BIU1:Load(T0)(A++) -> M[4](Mode0);//InputB2
|
||||
BIU1:Load(T0)(A++) -> M[5](Mode0);//useless
|
||||
BIU1:Load(T0)(A++) -> M[6](Mode0);//Maxdata
|
||||
BIU1:Load(T0)(A++) -> M[63](Mode0);//KI0
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//index1
|
||||
BIU1:Load(T0)(A++) -> SHU0.T4(Mode0);//index2
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -30,11 +27,20 @@
|
||||
R0:M[0] -> IMA0.T0(Mode0);
|
||||
R0:M[1] -> BIU0.T0(Mode0) || R1:M[0] -> IMA1.T0(Mode0);
|
||||
R3:M[2] -> BIU3.T0(Mode0) || R2:M[0] -> IMA2.T0(Mode0);
|
||||
R2:M[3] -> BIU2.T0(Mode0) || R3:M[0] -> IMA3.T0(Mode0);
|
||||
|
||||
R3:M[0] -> IMA3.T0(Mode0);
|
||||
R5:PreConfig(M[63])(Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[0-3](Mode0)||IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[4-7](Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||R2:M[6]->BIU2.T0(Mode0);
|
||||
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %Sum_1024 @(KI0 - 0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -44,18 +50,52 @@
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
NOP;
|
||||
IMA0: MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
//IMA0:SetMR(0)(H)(Mode0);
|
||||
Sum_1024:
|
||||
//IMA0: MR + 0*0(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.T3(Mode0);
|
||||
R0:M[3] -> BIU0.T0(Mode0);
|
||||
R3:M[4] -> BIU3.T0(Mode0);
|
||||
IMA0:ReadMR(L)->IMA2.T0;//real
|
||||
IMA0:ReadMR(O1)->IMA2.T2;//overflow real
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %SlidingCorrelation @(KI0 - 0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T2(Mode0); // load vector A and vector B
|
||||
BIU0:Load(T0)(A++) -> IMA1.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA1.T2(Mode0); // load vector A and vector B
|
||||
BIU0:Load(T0)(A++) -> IMA2.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA2.T2(Mode0); // load vector A and vector B
|
||||
IMA2:T0>>10(W)(U)->T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA2:T2>>16(W)(U)->T2;
|
||||
IMA2:Ttmp<<22(W)(T)->IMA2.T2;
|
||||
IMA2:T0+Ttmp(W)(U)->IMA1.T3;
|
||||
IMA3:V(1) -> IMA3.T1;
|
||||
IMA3:V(0) -> IMA3.T0;
|
||||
IMA1:V(0) -> IMA1.T0;
|
||||
/*IMA0:ReadMR(L)-> SHU0.T1(Mode0);
|
||||
IMA0:ReadMR(O1)-> SHU0.T2(Mode0);
|
||||
IMA0:ReadMR(O1)-> IMA2.T2(Mode0);
|
||||
R0:M[3] -> BIU0.T0(Mode0);
|
||||
R3:M[4] -> BIU3.T0(Mode0);
|
||||
IMA1:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA1.MR(Mode0);
|
||||
IMA3:V(1) -> IMA3.T1;
|
||||
IMA3:V(0) -> IMA3.T0;
|
||||
IMA1:V(0) -> IMA1.T0;
|
||||
SHU0:Index(T1,T0)(Mode0);
|
||||
SHU0:Index(T2,T0)->IMA2.T1(Mode0);
|
||||
IMA2:T2 >> 2 (W) (U) -> SHU0.T2;
|
||||
NOP;
|
||||
IMA2:T1 >> 2 (W) (U) -> SHU0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
SHU0:Index(T1,T4)(Mode0);
|
||||
SHU0:Index(T2,T4)->IMA1.T3(Mode0);*/
|
||||
MFetch:LPTO %Slide_Win @(KI2 - 0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T0(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T2(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -64,10 +104,40 @@ MFetch:LPTO %SlidingCorrelation @(KI0 - 0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
// 进行复数乘法
|
||||
IMA0: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T1(Mode0);
|
||||
IMA1: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T2(Mode0);
|
||||
IMA2: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T3(Mode0);
|
||||
NOP;
|
||||
IMA0:MR-T0*T1(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0)||IMA3:T0 + T1(S)(T) -> IMA3.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:MR+T2*T3(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:SetMR(0)(H);
|
||||
NOP;
|
||||
IMA0:ReadMR(L)-> IMA2.T0(Mode0)||IMA3:T0-> IMA1.T1;
|
||||
IMA0:ReadMR(O1)-> IMA2.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA2:T0>>10(W)(U)->T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA2:T2>>16(W)(U)->T2;
|
||||
IMA2:Ttmp<<22(W)(T)->IMA2.T2;
|
||||
IMA2:T0+Ttmp(W)(U)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:CompSel(T2, T3 , T2, T3) (W) -> IMA1.T3(Mode0);
|
||||
IMA1:CompSel(T2, T3 , T1, T0) (W) -> IMA1.T0(Mode0);
|
||||
Slide_Win:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:T0 -> BIU2.T1;
|
||||
IMA1:T3 -> BIU2.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -76,17 +146,19 @@ MFetch:LPTO %SlidingCorrelation @(KI0 - 0);
|
||||
BIU2:Store(T1,T0)(Mode0)(A++);
|
||||
BIU2:Store(T2,T0)(Mode0)(A++);
|
||||
BIU2:Store(T3,T0)(Mode0)(A++);
|
||||
SlidingCorrelation:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:ReadMR(L)-> BIU2.T1(Mode0);
|
||||
IMA0:ReadMR(O1)-> BIU2.T2(Mode0);
|
||||
NOP;
|
||||
R1:M[4] -> BIU1.T0(Mode0)||SHU0:VImm(1) -> SHU0.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:Store(T1,T0)(Mode0)(A++);
|
||||
BIU2:Store(T2,T0)(Mode0)(A++);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -94,139 +166,6 @@ SlidingCorrelation:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:VHigh(T3,0)->IMA0.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T3 >> 1(S)->IMA0.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %Sum_1024 @(KI1 - 1);
|
||||
BIU1:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:VHigh(T1,0)->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T1 >> 2(S)->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0: T1+T3(S)(T) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
Sum_1024:
|
||||
R3:M[5] -> BIU3.T1(Mode0);
|
||||
R3:M[6] -> BIU3.T0(Mode0);
|
||||
IMA0: T3 -> IMA1.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:V(1) -> IMA3.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:V(0) -> IMA3.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:V(0) -> IMA0.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:VHigh(T1,0)->IMA3.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %Slide_Win @(KI2 - 0);
|
||||
BIU3:Load(T1)(A++) -> IMA1.T1(Mode0);
|
||||
BIU3:Load(T1)(A++) -> IMA1.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:VHigh(T1,0)->IMA1.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:VHigh(T2,0)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:T1 >> 2(S)->IMA1.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:T2 >> 2(S)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3-T1(S)(T) -> IMA1.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3+T2(S)(T) -> IMA1.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3 -> IMA0.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3: T0 + T1(S)(T) -> IMA3.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:T0 ->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T2, T3) (S) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T1, T0) (S) -> IMA0.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
Slide_Win:
|
||||
IMA0:T0 -> BIU3.T1;
|
||||
IMA0:T3 -> BIU3.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU3:Store(T1,T0)(Mode0)(A++);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU3:Store(T2,T0)(Mode0)(A++);
|
||||
MFetch:REPEAT @(10);
|
||||
MFetch:MPU.STOP;
|
||||
|
||||
|
@ -1,27 +1,22 @@
|
||||
.section .text.m0, "ax"
|
||||
.file "SlidingCorrelationSecond.m0.asm"
|
||||
.file "SlidingCorrelationSecondAsm.m0.asm"
|
||||
// DO NOT MODIFY THE CONTENT ABOVE
|
||||
|
||||
.global SlidingCorrelationSecondAsm
|
||||
SlidingCorrelationSecondAsm:
|
||||
|
||||
|
||||
R1:M[0]->BIU1.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0);//ShiftMode
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0);//Output store result
|
||||
BIU1:Load(T0)(A++) -> M[4](Mode0);//Output1 sum the first 1024 vector
|
||||
BIU1:Load(T0)(A++) -> M[5](Mode0);//Output2 slide window
|
||||
BIU1:Load(T0)(A++) -> M[6](Mode0);//Maxdata
|
||||
BIU1:Load(T0)(A++) -> M[0](Mode0);
|
||||
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA2
|
||||
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB2
|
||||
BIU1:Load(T0)(A++) -> M[3](Mode0);//Maxdata read
|
||||
BIU1:Load(T0)(A++) -> M[4](Mode0);//Maxdata write
|
||||
BIU1:Load(T0)(A++) -> M[63](Mode0);//KI0
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//index1
|
||||
BIU1:Load(T0)(A++) -> SHU0.T4(Mode0);//index2
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -31,10 +26,16 @@
|
||||
R0:M[1] -> BIU0.T0(Mode0) || R1:M[0] -> IMA1.T0(Mode0);
|
||||
R3:M[2] -> BIU3.T0(Mode0) || R2:M[0] -> IMA2.T0(Mode0);
|
||||
R2:M[3] -> BIU2.T0(Mode0) || R3:M[0] -> IMA3.T0(Mode0);
|
||||
|
||||
R2:M[4] -> BIU2.T1(Mode0);
|
||||
R5:PreConfig(M[63])(Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[0-3](Mode0)||IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
R5:WriteConf(Mfetch)->KI[4-7](Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||R2:M[6]->BIU2.T0(Mode0);
|
||||
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA1.T3(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
BIU2:Load(T0)(A++) -> IMA0.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -44,150 +45,15 @@
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %SlidingCorrelation @(KI0 - 0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T2(Mode0); // load vector A and vector B
|
||||
BIU0:Load(T0)(A++) -> IMA1.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA1.T2(Mode0); // load vector A and vector B
|
||||
BIU0:Load(T0)(A++) -> IMA2.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA2.T2(Mode0); // load vector A and vector B
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
// 进行复数乘法
|
||||
IMA0: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T1(Mode0);
|
||||
IMA1: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T2(Mode0);
|
||||
IMA2: 0+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:Store(T1,T0)(Mode0)(A++);
|
||||
BIU2:Store(T2,T0)(Mode0)(A++);
|
||||
BIU2:Store(T3,T0)(Mode0)(A++);
|
||||
SlidingCorrelation:
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
R1:M[4] -> BIU1.T0(Mode0)||SHU0:VImm(1) -> SHU0.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU1:Load(T0)(A++) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:VHigh(T3,0)->IMA0.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T3 >> 1(S)->IMA0.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:LPTO %Sum_1024 @(KI1 - 1);
|
||||
BIU1:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:VHigh(T1,0)->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:T1 >> 2(S)->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0: T1+T3(S)(T) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
Sum_1024:
|
||||
R3:M[5] -> BIU3.T1(Mode0);
|
||||
R3:M[6] -> BIU3.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU3:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
BIU3:Load(T0)(A++) -> IMA0.T2(Mode0);
|
||||
IMA0: T3 -> IMA1.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:SetMR(T1)(O1) (Mode0);
|
||||
IMA0:SetMR(T2)(L) (Mode0);
|
||||
IMA3:V(1) -> IMA3.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:V(0) -> IMA3.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:V(0) -> IMA0.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:VHigh(T1,0)->IMA3.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T2, T3) (S) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T1, T0) (S) -> IMA0.T0(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:V(0) -> IMA1.T0;
|
||||
MFetch:LPTO %Slide_Win @(KI2 - 0);
|
||||
BIU3:Load(T1)(A++) -> IMA1.T1(Mode0);
|
||||
BIU3:Load(T1)(A++) -> IMA1.T2(Mode0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T0(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T1(Mode0);
|
||||
BIU0:Load(T0)(A++) -> IMA0.T2(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
@ -197,55 +63,50 @@ MFetch:LPTO %Slide_Win @(KI2 - 0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:VHigh(T1,0)->IMA1.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:VHigh(T2,0)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:T1 >> 2(S)->IMA1.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:T2 >> 2(S)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3-T1(S)(T) -> IMA1.T3(Mode0);
|
||||
IMA0:MR-T0*T1(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0)||IMA3:T0 + T1(S)(T) -> IMA3.T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3+T2(S)(T) -> IMA1.T3(Mode0);
|
||||
IMA0:MR+T2*T3(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1: T3 -> IMA0.T2(Mode0);
|
||||
IMA0:SetMR(0)(H);
|
||||
NOP;
|
||||
IMA0:ReadMR(L)-> IMA2.T0(Mode0)||IMA3:T0-> IMA1.T1;
|
||||
IMA0:ReadMR(O1)-> IMA2.T2(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3: T0 + T1(S)(T) -> IMA3.T0;
|
||||
NOP;
|
||||
IMA2:T0>>10(W)(U)->T0;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA3:T0 ->IMA0.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T2, T3) (S) -> IMA0.T3(Mode0);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA0:CompSel(T2, T3 , T1, T0) (S) -> IMA0.T0(Mode0);
|
||||
NOP;
|
||||
IMA2:T2>>16(W)(U)->T2;
|
||||
IMA2:Ttmp<<22(W)(T)->IMA2.T2;
|
||||
IMA2:T0+Ttmp(W)(U)->IMA1.T2;
|
||||
NOP;
|
||||
NOP;
|
||||
IMA1:CompSel(T2, T3 , T2, T3) (W) -> IMA1.T3(Mode0);
|
||||
IMA1:CompSel(T2, T3 , T1, T0) (W) -> IMA1.T0(Mode0);
|
||||
Slide_Win:
|
||||
//IMA1:T3 -> BIU3.T1;
|
||||
IMA0:T0 -> BIU3.T1;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU3:Store(T1,T0)(Mode0);
|
||||
|
||||
NOP;
|
||||
IMA1:T0 -> BIU2.T2;
|
||||
IMA1:T3 -> BIU2.T3;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
BIU2:Store(T2,T1)(Mode0)(A++);
|
||||
BIU2:Store(T3,T1)(Mode0)(A++);
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
NOP;
|
||||
MFetch:REPEAT @(10);
|
||||
MFetch:MPU.STOP;
|
||||
|
||||
|
BIN
MicroCode/SlidingCorrelation/src/spu/.main.s.c.swp
Normal file
BIN
MicroCode/SlidingCorrelation/src/spu/.main.s.c.swp
Normal file
Binary file not shown.
@ -1,14 +1,13 @@
|
||||
#include "SlidingCorrelation.h"
|
||||
|
||||
void SlidingCorrelation(int ConfigAddr, int InAddr1, int InAddr2, int OutAddr, int MaxAddr) {
|
||||
void SlidingCorrelation(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr) {
|
||||
volatile unsigned int *Para = (volatile unsigned int *)ConfigAddr;
|
||||
|
||||
Para[16*1+0] = InAddr1;
|
||||
Para[16*2+0] = InAddr2;
|
||||
Para[16*3+0] = OutAddr;
|
||||
Para[16*4+0] = OutAddr;//output1
|
||||
Para[16*5+0] = OutAddr;//output2
|
||||
Para[16*5+1] = OutAddr;
|
||||
Para[16*3+0] = InAddr1;
|
||||
Para[16*3+1] = InAddr1;
|
||||
Para[16*4+0] = InAddr2;
|
||||
Para[16*4+1] = InAddr2;
|
||||
Para[16*6+0] = MaxAddr;
|
||||
|
||||
}
|
||||
|
@ -1,14 +1,13 @@
|
||||
#include "SlidingCorrelationSecond.h"
|
||||
|
||||
void SlidingCorrelationSecond(int ConfigAddr, int InAddr1, int InAddr2, int OutAddr, int MaxAddr) {
|
||||
void SlidingCorrelationSecond(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr) {
|
||||
volatile unsigned int *Para = (volatile unsigned int *)ConfigAddr;
|
||||
|
||||
Para[16*1+0] = InAddr1;
|
||||
Para[16*1+1] = InAddr1;
|
||||
Para[16*2+0] = InAddr2;
|
||||
Para[16*3+0] = OutAddr;
|
||||
Para[16*4+0] = OutAddr;//output1
|
||||
Para[16*5+0] = OutAddr;//output2
|
||||
Para[16*5+1] = OutAddr;
|
||||
Para[16*6+0] = MaxAddr;
|
||||
Para[16*2+1] = InAddr2;
|
||||
Para[16*3+0] = MaxAddr;
|
||||
Para[16*4+0] = MaxAddr;
|
||||
|
||||
}
|
||||
|
@ -1,7 +1,7 @@
|
||||
#ifndef REMOVE_MC_TEST
|
||||
|
||||
#include "ucps2.h"
|
||||
#include "SyncVer.h"
|
||||
//#include "SyncVer.h"
|
||||
#include "SlidingCorrelation.h"
|
||||
#include "SlidingCorrelationSecond.h"
|
||||
#include <stdio.h>
|
||||
@ -13,33 +13,36 @@
|
||||
|
||||
|
||||
__DM1 int Input1_part1[] = {
|
||||
#include <Inputdata1_part1.dat>
|
||||
#include <Input1_part1.dat>
|
||||
};
|
||||
__DM1 int Input1_part2[] = {
|
||||
#include <Inputdata1_part2.dat>
|
||||
#include <Input1_part2.dat>
|
||||
};
|
||||
__DM2 int Input2_part1[] = {
|
||||
#include <Inputdata2_part1.dat>
|
||||
#include <Input2_part1.dat>
|
||||
};
|
||||
__DM2 int Input2_part2[] = {
|
||||
#include <Inputdata2_part2.dat>
|
||||
#include <Input2_part2.dat>
|
||||
};
|
||||
/*__DM1 int Input1_part1[] = {
|
||||
#include <timedatasym.dat>
|
||||
};
|
||||
__DM2 int Input2_part1[] = {
|
||||
#include <timedatasym.dat>
|
||||
};*/
|
||||
__DM3 int ConfigMatrix[] = {
|
||||
#include "ConfigSlidingCorrelation.dat"
|
||||
};
|
||||
__DM3 int ConfigMatrix2[] = {
|
||||
#include "ConfigSlidingCorrelationSecond.dat"
|
||||
};
|
||||
__DM3 int Config2[] = {
|
||||
#include "ConfigSyncVer.dat"
|
||||
};
|
||||
|
||||
__DM1 int slice1[1055]; // 用于存储Input1切片数据
|
||||
__DM2 int slice2[1055]; // 用于存储Input2切片数据
|
||||
__DM5 int MaxData[2];
|
||||
__DM5 int MaxData[4];//bestposition maxsum lastsum
|
||||
__DM5 int MaxData2[4];//bestposition maxsum
|
||||
__DM0 int result[2]; // 存储SyncVer微码模块的计算结果
|
||||
|
||||
__DM4 int OutputData[DATA_SIZE]; // 初步同步时的输出存储
|
||||
__DM4 int OutputData2[1055];
|
||||
v16u32 KI = { 2, 4, 6 };
|
||||
__DM3 v16s32 SVRReg = {
|
||||
@ -69,27 +72,48 @@ int main(void) {
|
||||
|
||||
// 初步同步:执行滑动相关性计算
|
||||
if (!is_synced) {
|
||||
SlidingCorrelation((int)ConfigMatrix, MPU_ADDR(Input1_part1), MPU_ADDR(Input2_part1), MPU_ADDR(OutputData),MPU_ADDR(MaxData));
|
||||
uint32_t time0 = tick();
|
||||
SlidingCorrelation((int)ConfigMatrix, MPU_ADDR(Input1_part1), MPU_ADDR(Input2_part1), MPU_ADDR(MaxData));
|
||||
SVRReg[0] = MPU_ADDR(ConfigMatrix);
|
||||
SlidingCorrelationAsm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
MaxData2[0] = MaxData[0];
|
||||
MaxData2[1] = MaxData[1];
|
||||
MaxData2[2] = MaxData[2];
|
||||
MaxData2[3] = MaxData[3];
|
||||
//second part
|
||||
SlidingCorrelationSecond((int)ConfigMatrix2, MPU_ADDR(Input1_part2), MPU_ADDR(Input2_part2), MPU_ADDR(OutputData),MPU_ADDR(MaxData));
|
||||
SlidingCorrelationSecond((int)ConfigMatrix2, MPU_ADDR(Input1_part2), MPU_ADDR(Input2_part2), MPU_ADDR(MaxData2));
|
||||
SVRReg[0] = MPU_ADDR(ConfigMatrix2);
|
||||
SlidingCorrelationSecondAsm(SVRReg);
|
||||
a = __ucps2_getStatB();
|
||||
__ucps2_delay();
|
||||
|
||||
maxPosition = MaxData[0];
|
||||
uint32_t time1 = tick();
|
||||
if(0==MaxData2[0])
|
||||
{
|
||||
if(MaxData[1]==MaxData2[1])
|
||||
{
|
||||
maxPosition = MaxData[0]&0x0000ffff;
|
||||
maxsum = MaxData[1];
|
||||
}
|
||||
else{
|
||||
printf("error");
|
||||
};
|
||||
}
|
||||
else
|
||||
{
|
||||
maxPosition = MaxData2[0]&0x0000ffff+DATA_SIZE/2-1;
|
||||
maxsum = MaxData2[1];
|
||||
};
|
||||
// 设置同步标志
|
||||
is_synced = 1;
|
||||
|
||||
printf("初步同步位置:%d\n", maxPosition);
|
||||
printf("maxsum:%d\n", maxsum);
|
||||
printf("time:%d\n", time1-time0);
|
||||
}
|
||||
|
||||
// 同步后,执行精确同步位置计算
|
||||
/*// 同步后,执行精确同步位置计算
|
||||
if (is_synced) {
|
||||
|
||||
// 从初步同步位置前16后15提取切片数据,总共1055个样点
|
||||
@ -109,7 +133,7 @@ int main(void) {
|
||||
int bestPosition =result[0];
|
||||
|
||||
printf("精确同步位置:%d,窗口内最大累加和:%d\n", bestPosition, maxWindowSum);
|
||||
}
|
||||
}*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
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Reference in New Issue
Block a user