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代码回退地址空间修改部分

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HUOHUO 2025-06-06 22:52:10 -07:00
parent 86e06ae39e
commit 6c9db56c25
9 changed files with 23 additions and 20 deletions
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22
APELib/Receiver_sync/src/receiver_Sync_Proc.s.c
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@ -234,7 +234,7 @@ void Receiver_Sync_Proc(
(uint64_t)DM_TO_CSU_ADDR(cur_in_addr_data), (uint64_t)DM_TO_CSU_ADDR(cur_in_addr_data),
(30720)<<2, (30720)<<2,
DMA_TAG_G2L, DMA_TAG_G2L,
0); 1);
} }
@ -249,10 +249,10 @@ void Receiver_Sync_Proc(
MPU_ADDR(data_out_addr), MPU_ADDR(data_out_addr),
30720, 30720,
16); 16);
if(0 == loop_idx) //流水第一次数据搬入完成后再开始第一次调用 // if(0 == loop_idx) //流水第一次数据搬入完成后再开始第一次调用
{ // {
ape_csu_task_lookup(DMA_TAG_G2L,1); ape_csu_task_lookup(DMA_TAG_G2L,1);
} // }
ape_csu_task_lookup(DMA_TAG_L2G,1); ape_csu_task_lookup(DMA_TAG_L2G,1);
if(loop_idx < 3) if(loop_idx < 3)
{ {
@ -260,7 +260,7 @@ void Receiver_Sync_Proc(
(uint64_t)DM_TO_CSU_ADDR(nxt_in_addr+16*4), (uint64_t)DM_TO_CSU_ADDR(nxt_in_addr+16*4),
(30720)<<2, (30720)<<2,
DMA_TAG_G2L, DMA_TAG_G2L,
0); 1);
} }
SVRReg[0] = MPU_ADDR(cfg_addr); SVRReg[0] = MPU_ADDR(cfg_addr);
Decimation_LTEAsm(SVRReg); Decimation_LTEAsm(SVRReg);
@ -272,7 +272,7 @@ void Receiver_Sync_Proc(
(uint64_t)(dec_base_out_addr + loop_idx*(30720*2)), (uint64_t)(dec_base_out_addr + loop_idx*(30720*2)),
(30720)<<1, (30720)<<1,
DMA_TAG_L2G, DMA_TAG_L2G,
0); 1);
} }
//最后一次数据需要保证搬移完成 //最后一次数据需要保证搬移完成
ape_csu_task_lookup(DMA_TAG_L2G, 1); ape_csu_task_lookup(DMA_TAG_L2G, 1);
@ -623,14 +623,15 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag(); data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag();
g_proc_id++; g_proc_id++;
LOG_ERROR_S("data1 %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset); LOG_ERROR_S("data1 %d 0x%08x %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset,
(data_send2symb_task[task_idx].data_section0_ptr + (data_send2symb_task[task_idx].data_section0_length<<2)), data_send2symb_task[task_idx].data_section1_length);
//为了适配SYMB接口，如果数据是两段，搬移成一块 //为了适配SYMB接口，如果数据是两段，搬移成一块
if(2 == data_send2symb_task[task_idx].num_data_section) if(2 == data_send2symb_task[task_idx].num_data_section)
{ {
ape_csu_task_lookup(DMA_TAG_G2G,1); ape_csu_task_lookup(DMA_TAG_G2G,1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(data_send2symb_task[task_idx].data_section1_ptr), ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(data_send2symb_task[task_idx].data_section1_ptr),
(uint64_t)(data_send2symb_task[task_idx].data_section0_ptr + data_send2symb_task[task_idx].data_section0_length), (uint64_t)(data_send2symb_task[task_idx].data_section0_ptr + (data_send2symb_task[task_idx].data_section0_length<<2)),
(data_send2symb_task[task_idx].data_section1_length)<<2, (data_send2symb_task[task_idx].data_section1_length)<<2,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);
@ -691,13 +692,14 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
data_send2symb_task[task_idx].transform_para_imag[2] = transform_get_thita3_imag(); data_send2symb_task[task_idx].transform_para_imag[2] = transform_get_thita3_imag();
data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag(); data_send2symb_task[task_idx].transform_para_imag[3] = transform_get_thita4_imag();
g_proc_id++; g_proc_id++;
LOG_ERROR_S("data2 %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset); LOG_ERROR_S("data2 %d 0x%08x %d 0x%08x %d\n", proc_head, data_send2symb_task[task_idx].data_section0_ptr, frame_head_offset,
(data_send2symb_task[task_idx].data_section0_ptr + (data_send2symb_task[task_idx].data_section0_length<<2)), data_send2symb_task[task_idx].data_section1_length);
//为了适配SYMB接口，如果数据是两段，搬移成一块 //为了适配SYMB接口，如果数据是两段，搬移成一块
if(2 == data_send2symb_task[task_idx].num_data_section) if(2 == data_send2symb_task[task_idx].num_data_section)
{ {
ape_csu_task_lookup(DMA_TAG_G2G,1); ape_csu_task_lookup(DMA_TAG_G2G,1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(data_send2symb_task[task_idx].data_section1_ptr), ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(data_send2symb_task[task_idx].data_section1_ptr),
(uint64_t)(data_send2symb_task[task_idx].data_section0_ptr + data_send2symb_task[task_idx].data_section0_length), (uint64_t)(data_send2symb_task[task_idx].data_section0_ptr + (data_send2symb_task[task_idx].data_section0_length<<2)),
(data_send2symb_task[task_idx].data_section1_length)<<2, (data_send2symb_task[task_idx].data_section1_length)<<2,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);

21
Common/inc/mem_def.h
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@ -79,7 +79,7 @@
/************************************SM4--1.5M***********************************************/ /************************************SM4--1.5M***********************************************/
/*
#define RECEIVER_BASE (0x71000000) //4k对齐 #define RECEIVER_BASE (0x71000000) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000 #define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000 #define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
@ -89,9 +89,9 @@
#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN) #define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN) #define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t) #define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
*/
/*
#define RECEIVER_BASE (SM4_BASE) //4k对齐 #define RECEIVER_BASE (SM4_BASE) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000 #define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000 #define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
@ -100,11 +100,11 @@
#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN) #define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN) #define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN) #define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
*/
/************************************SM5--1.5M***********************************************/ /************************************SM5--1.5M***********************************************/
#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (SM5_BASE) //#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (SM5_BASE)
//#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t) #define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
#ifdef CORE_ODD #ifdef CORE_ODD
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN) #define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN)
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN) #define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN)
@ -120,10 +120,10 @@
//接收端数据来源选择 //接收端数据来源选择
//---------------TX RX JESD地址接口--------------------------------------------------------- //---------------TX RX JESD地址接口---------------------------------------------------------
//#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000 #define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
//#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000 #define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (SM4_BASE) //0x1E0000 // #define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (SM4_BASE) //0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (SM4_BASE+0x78000) //0x1E0000 // #define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (SM4_BASE+0x78000) //0x1E0000
#ifdef TX_RX_LOOP #ifdef TX_RX_LOOP
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR) #define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR)
@ -141,6 +141,7 @@
#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理 #define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理
//---------------APE4 RECV START FIRSTSYNC FLAG--------------------------------------------- //---------------APE4 RECV START FIRSTSYNC FLAG---------------------------------------------
#define RECV_FIRST_SYNC_START_FLAG (0x82000000) //通过手动输入来开始接收端第一次同步 devmem 0x82000000 0xa5a55a5a 32 #define RECV_FIRST_SYNC_START_FLAG (0x82000000) //通过手动输入来开始接收端第一次同步 devmem 0x82000000 0xa5a55a5a 32
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (0x82001000) //LEN: sizeof(receiver_sync_status_t)
//---------------APE7 PCIE TO APE4 sync_proc //---------------APE7 PCIE TO APE4 sync_proc
#define TRANSFORM_REF_PARA_PCIE2SYNC_ADDR (0x83000000) #define TRANSFORM_REF_PARA_PCIE2SYNC_ADDR (0x83000000)

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