jinhong/YB_TX_RX_APE_PRJ
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添加Recv 245.76M数据抽取，抽取耗时约150us

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This commit is contained in:
HUOHUO 2025-06-03 10:21:20 -07:00
parent f4ba0777b3
commit 759292a816
29 changed files with 237723 additions and 45 deletions
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2
APE4/Makefile
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@ -1,6 +1,6 @@
############################ ############################
# mpu libs need to link to this APE, could be specified by user # mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=ByteCopy SyncVer Sliding MICRO_CODE_LIBS:=ByteCopy SyncVer Sliding Decimation_LTE
############################ ############################
# tool path, could be specified by user # tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin #UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

4
APE7/ApeTask/inc/jesd_csu_nr_fdd.h
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@ -33,8 +33,8 @@
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR 0x610E0000 // 0x1E0000 #define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR 0x610E0000 // 0x1E0000
#endif #endif
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR 0x6BC00000 // 0x9F00000 // 0x1E0000 #define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR 0x6BC00000 // 0x9F00000 // 0x1E0000
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR 0x6BDE0000 // 0xA380000 // 0x1E0000 #define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR 0x6BDE0000 // 0xA380000 // 0x1E0000
int32_t jesd_csu_init_nr_fdd(); int32_t jesd_csu_init_nr_fdd();

4
APELib/Receiver_symb/src/receiver_Symb_Init.s.c
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@ -104,12 +104,12 @@ void Receiver_Symb_Init()
// STORE_EX_W(param_ptr, timedata_ptr); // STORE_EX_W(param_ptr, timedata_ptr);
// STORE_EX_W((param_ptr+1), timedata_len); // STORE_EX_W((param_ptr+1), timedata_len);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr), ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr),
(uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0 (uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
timedata_len, timedata_len,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr), ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr),
(uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0 (uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
timedata_len, timedata_len,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);

1
APELib/Receiver_sync/inc/receiver_sync_func.h
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@ -32,6 +32,7 @@
#include "ByteCopy.h" #include "ByteCopy.h"
#include "SyncVer.h" #include "SyncVer.h"
#include "Sliding.h" #include "Sliding.h"
#include "Decimation_LTE.h"
//微码配置空间偏移结构体 //微码配置空间偏移结构体

2
APELib/Receiver_sync/inc/receiver_sync_macro.h
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@ -19,7 +19,7 @@
#define RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0080) #define RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0080)
#define RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH (0x00a0) #define RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH (0x00a0)
#define RECEIVER_SYNC_ConfigSliding_CFG5_LENGTH (0x0060) #define RECEIVER_SYNC_ConfigSliding_CFG5_LENGTH (0x0060)
#define RECEIVER_SYNC_ConfigDecimation_CFG6_LENGTH (0x0090)
//SPU查找表各字段长度定义,单位为word(4Byte) //SPU查找表各字段长度定义,单位为word(4Byte)

2
APELib/Receiver_sync/inc/receiver_sync_struct.h
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@ -26,6 +26,7 @@ typedef struct receiver_sync_table_param_s
uint32_t ConfigSlidingCorrelationSecond_CFG3_Offset; uint32_t ConfigSlidingCorrelationSecond_CFG3_Offset;
uint32_t ConfigSyncVer_CFG4_Offset; uint32_t ConfigSyncVer_CFG4_Offset;
uint32_t ConfigSliding_CFG5_Offset; uint32_t ConfigSliding_CFG5_Offset;
uint32_t ConfigDecimation_CFG6_Offset;
// 存储微码参数表的ddr基地址和长度 // 存储微码参数表的ddr基地址和长度
uint32_t receiver_sync_config0_ddr_ptr;//receiver DM0微码配置文件ddr地址 uint32_t receiver_sync_config0_ddr_ptr;//receiver DM0微码配置文件ddr地址
uint32_t receiver_sync_config0_length;//receiver DM0微码配置文件ddr长度 uint32_t receiver_sync_config0_length;//receiver DM0微码配置文件ddr长度
@ -42,6 +43,7 @@ typedef struct receiver_sync_table_param_s
// SPU LUT SM基地址和长度 // SPU LUT SM基地址和长度
uint32_t receiver_sync_pilot_ptr;//receiver DM0微码配置文件ddr地址 uint32_t receiver_sync_pilot_ptr;//receiver DM0微码配置文件ddr地址
uint32_t receiver_sync_pilot_length;//receiver DM0微码配置文件ddr长度 uint32_t receiver_sync_pilot_length;//receiver DM0微码配置文件ddr长度
uint32_t ConfigDecimation_LUT1_Offset;
}receiver_sync_table_param_t; }receiver_sync_table_param_t;

29
APELib/Receiver_sync/src/receiver_Sync_Init.s.c
View File

@ -29,8 +29,9 @@ void Receiver_Sync_Init()
g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelation_CFG2_Offset + RECEIVER_SYNC_ConfigSlidingCorrelation_CFG2_LENGTH; g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelation_CFG2_Offset + RECEIVER_SYNC_ConfigSlidingCorrelation_CFG2_LENGTH;
g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset + RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH; g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset = g_receiver_sync_table_param.ConfigSlidingCorrelationSecond_CFG3_Offset + RECEIVER_SYNC_ConfigSlidingCorrelationSecond_CFG3_LENGTH;
g_receiver_sync_table_param.ConfigSliding_CFG5_Offset = g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset + RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH; g_receiver_sync_table_param.ConfigSliding_CFG5_Offset = g_receiver_sync_table_param.ConfigSyncVer_CFG4_Offset + RECEIVER_SYNC_ConfigSyncVer_CFG4_LENGTH;
g_receiver_sync_table_param.ConfigDecimation_CFG6_Offset = g_receiver_sync_table_param.ConfigSliding_CFG5_Offset + RECEIVER_SYNC_ConfigSliding_CFG5_LENGTH;
//DM1 //DM1
g_receiver_sync_table_param.ConfigDecimation_LUT1_Offset = 0;
//DM2 //DM2
//DM3 //DM3
@ -53,12 +54,20 @@ void Receiver_Sync_Init()
if(0 != ret) if(0 != ret)
{ {
//LOG_ERROR_S("Receiver_Sync_cfg_dm0.dat not found!\n"); //LOG_ERROR_S("Receiver_Sync_cfg_dm0.dat not found!\n");
} }
ret = osp_get_cfgfile("Receiver_Sync_cfg_dm1.dat",
(uint32_t *)&(g_receiver_sync_table_param.receiver_sync_config1_ddr_ptr),
(int32_t *)&(g_receiver_sync_table_param.receiver_sync_config1_length));
TRACE(TRACE_RECV_INIT_ADDR, 6, 3);
if(0 != ret)
{
//LOG_ERROR_S("Receiver_Sync_cfg_dm1.dat not found!\n");
}
ret = osp_get_cfgfile("Recv_Pilot.dat", ret = osp_get_cfgfile("Recv_Pilot.dat",
(uint32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_ptr), (uint32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_ptr),
(int32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_length)); (int32_t *)&(g_receiver_sync_table_param.receiver_sync_pilot_length));
//LOG_ERROR_S("Recv_Pilot.dat %d %d %d\n", g_receiver_sync_table_param.receiver_sync_pilot_ptr, g_receiver_sync_table_param.receiver_sync_pilot_length, ret); //LOG_ERROR_S("Recv_Pilot.dat %d %d %d\n", g_receiver_sync_table_param.receiver_sync_pilot_ptr, g_receiver_sync_table_param.receiver_sync_pilot_length, ret);
TRACE(TRACE_RECV_INIT_ADDR, 6, 3); TRACE(TRACE_RECV_INIT_ADDR, 6, 4);
if(0 != ret) if(0 != ret)
{ {
//LOG_ERROR_S("Recv_Pilot.dat not found!\n"); //LOG_ERROR_S("Recv_Pilot.dat not found!\n");
@ -81,7 +90,7 @@ void Receiver_Sync_Init()
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status, SYNC_IDLE); STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status, SYNC_IDLE);
STORE_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset, 0); STORE_EX_W(&g_receiver_sync_status_SM_ptr->frame_head_offset, 0);
TRACE(TRACE_RECV_INIT_ADDR, 6, 4); TRACE(TRACE_RECV_INIT_ADDR, 6, 5);
g_receiver_sync_cylic_buffer.buffer_head = 0; g_receiver_sync_cylic_buffer.buffer_head = 0;
g_receiver_sync_cylic_buffer.buffer_tail = 0; g_receiver_sync_cylic_buffer.buffer_tail = 0;
g_receiver_sync_cylic_buffer.buffer_min = 0; g_receiver_sync_cylic_buffer.buffer_min = 0;
@ -115,12 +124,12 @@ void Receiver_Sync_Init()
// LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr,dbg_len); // LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr,dbg_len);
// ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr), // ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
// (uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0 // (uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
// dbg_len, // dbg_len,
// DMA_TAG_G2G, // DMA_TAG_G2G,
// 1); // 1);
// ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr), // ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr),
// (uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0 // (uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
// dbg_len, // dbg_len,
// DMA_TAG_G2G, // DMA_TAG_G2G,
// 1); // 1);
@ -139,7 +148,7 @@ else
//LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr0,dbg_len0); //LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr0,dbg_len0);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr0), ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr0),
(uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0 (uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
dbg_len0, dbg_len0,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);
@ -159,7 +168,7 @@ else
LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr1,dbg_len1); LOG_ERROR_S("INIT DBG DDR 0x%08x %d\n",dbg_addr1,dbg_len1);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr1), ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(dbg_addr1),
(uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0 (uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR,//第一次固定搬移到dm0
dbg_len1, dbg_len1,
DMA_TAG_G2G, DMA_TAG_G2G,
1); 1);
@ -167,8 +176,8 @@ else
} }
#endif #endif
TRACE(TRACE_RECV_INIT_ADDR, 6, 5);
transform_para_init(0, 0, 0);
TRACE(TRACE_RECV_INIT_ADDR, 6, 6); TRACE(TRACE_RECV_INIT_ADDR, 6, 6);
transform_para_init(0, 0, 0);
TRACE(TRACE_RECV_INIT_ADDR, 6, 7);
} }

125
APELib/Receiver_sync/src/receiver_Sync_Proc.s.c
View File

@ -105,7 +105,17 @@ void Receiver_Sync_Memory_Alloc( )
dfree_unit(receiver_sync_malloc_dm0_ptr, APE_DM0); dfree_unit(receiver_sync_malloc_dm0_ptr, APE_DM0);
return; return;
} }
//DM1第一段,堆空间 ape_csu_task_lookup(DMA_TAG_G2L, 1);
//DM1第一段，微码相关空间
receiver_sync_config_dm1_ptr = (uint32_t)receiver_sync_malloc_dm1_ptr;
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)g_receiver_sync_table_param.receiver_sync_config1_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_config_dm1_ptr),
g_receiver_sync_table_param.receiver_sync_config1_length,
DMA_TAG_G2L,
0);
//DM1第二段,堆空间
receiver_sync_temp_dm1_ptr = (int32_t *)ADDR_ALIGN(receiver_sync_malloc_dm1_ptr + \ receiver_sync_temp_dm1_ptr = (int32_t *)ADDR_ALIGN(receiver_sync_malloc_dm1_ptr + \
(g_receiver_sync_table_param.receiver_sync_config1_length>>2), 12); //起始地址4k对齐 (g_receiver_sync_table_param.receiver_sync_config1_length>>2), 12); //起始地址4k对齐
@ -125,8 +135,8 @@ void Receiver_Sync_Memory_Alloc( )
receiver_sync_temp_dm2_ptr = (int32_t *)ADDR_ALIGN(receiver_sync_malloc_dm2_ptr + \ receiver_sync_temp_dm2_ptr = (int32_t *)ADDR_ALIGN(receiver_sync_malloc_dm2_ptr + \
(g_receiver_sync_table_param.receiver_sync_config2_length>>2), 2); //起始地址4byte对齐 (g_receiver_sync_table_param.receiver_sync_config2_length>>2), 2); //起始地址4byte对齐
ape_csu_task_lookup(DMA_TAG_G2L, 1); ape_csu_task_lookup(DMA_TAG_G2L, 1);
//debug //debug
last_mem_dm[0] = receiver_sync_malloc_dm0_ptr + ((dm0_space - 1024)>>2) -1; last_mem_dm[0] = receiver_sync_malloc_dm0_ptr + ((dm0_space - 1024)>>2) -1;
@ -181,6 +191,97 @@ void Receiver_Sync_Proc(
uint32_t cur_sfn = get_rx_nr_sfn(); uint32_t cur_sfn = get_rx_nr_sfn();
uint32_t cur_slot = get_rx_nr_slot(); uint32_t cur_slot = get_rx_nr_slot();
//Proc的DM空间申请
Receiver_Sync_Memory_Alloc();
//不论状态机如何，先处理数据抽取-------------------------------
uint32_t dec_time0, dec_time1;
dec_time0 = Time_offset(0);
uint32_t dec_base_in_addr, dec_base_out_addr;
uint32_t loop_idx;
if( 1 == (cur_slot & 0x01) )
{
dec_base_in_addr = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
dec_base_out_addr = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
}
else
{
dec_base_in_addr = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
dec_base_out_addr = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
}
//分四次处理，一次处理30720(sample)*4(byte)数据，两组地址pingpang
uint32_t data_in_addr0 = receiver_sync_temp_dm0_ptr;
uint32_t data_in_addr1 = receiver_sync_temp_dm2_ptr;
uint32_t data_out_addr = receiver_sync_temp_dm3_ptr;
uint32_t cur_in_addr, nxt_in_addr, cur_in_addr_padding0, cur_in_addr_padding1, cur_in_addr_data;
uint32_t dec_lut_addr = (int32_t *)receiver_sync_config_dm1_ptr + g_receiver_sync_table_param.ConfigDecimation_LUT1_Offset;
cfg_addr = (int32_t *)receiver_sync_config_dm0_ptr + g_receiver_sync_table_param.ConfigDecimation_CFG6_Offset;
for(loop_idx = 0; loop_idx < 4; loop_idx++)
{
cur_in_addr = ( 0 == (loop_idx & 0x01) ) ? data_in_addr0 : data_in_addr1;
nxt_in_addr = ( 1 == (loop_idx & 0x01) ) ? data_in_addr0 : data_in_addr1;
cur_in_addr_padding0 = cur_in_addr;
cur_in_addr_data = cur_in_addr + 16*4;
cur_in_addr_padding1 = cur_in_addr_data + (30720<<2);
if(0 == loop_idx) //流水第一次数据搬入
{
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(dec_base_in_addr + loop_idx*30720*4),
(uint64_t)DM_TO_CSU_ADDR(cur_in_addr_data),
(30720)<<2,
DMA_TAG_G2L,
0);
}
memset((void*)cur_in_addr_padding0, 0, 16*4);
memset((void*)cur_in_addr_padding1, 0, 14*4);
Decimation_LTE((int*)cfg_addr,
MPU_ADDR(cur_in_addr_padding0),
MPU_ADDR(cur_in_addr_data),
MPU_ADDR(cur_in_addr_padding1),
MPU_ADDR(dec_lut_addr),
MPU_ADDR(data_out_addr),
30720,
16);
if(0 == loop_idx) //流水第一次数据搬入完成后再开始第一次调用
{
ape_csu_task_lookup(DMA_TAG_G2L,1);
}
ape_csu_task_lookup(DMA_TAG_L2G,1);
if(loop_idx < 3)
{
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(dec_base_in_addr + (loop_idx+1)*30720*4),
(uint64_t)DM_TO_CSU_ADDR(nxt_in_addr),
(30720)<<2,
DMA_TAG_G2L,
0);
}
SVRReg[0] = MPU_ADDR(cfg_addr);
Decimation_LTEAsm(SVRReg);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(data_out_addr),
(uint64_t)(dec_base_out_addr + loop_idx*(30720*4/2)),
(30720)<<2>>1,
DMA_TAG_L2G,
0);
}
//最后一次数据需要保证搬移完成
ape_csu_task_lookup(DMA_TAG_L2G, 1);
dec_time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYNC_ADDR, 4, dec_time1-dec_time0 );
//-------------------END 数据抽取-----------------------------
volatile sync_status = LOAD_EX_W(&(g_receiver_sync_status_SM_ptr->sync_status)); volatile sync_status = LOAD_EX_W(&(g_receiver_sync_status_SM_ptr->sync_status));
TRACE(TRACE_RECEIVER_SYNC_ADDR, 12, sync_status); TRACE(TRACE_RECEIVER_SYNC_ADDR, 12, sync_status);
@ -256,6 +357,7 @@ void Receiver_Sync_Proc(
return; return;
} }
Receiver_Sync_Memory_Free();
TRACE(TRACE_RECEIVER_SYNC_ADDR, 3, 8); TRACE(TRACE_RECEIVER_SYNC_ADDR, 3, 8);
return; return;
} }
@ -279,27 +381,24 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
uint32_t src_addr1; uint32_t src_addr1;
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 1); TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 1);
//Proc的DM空间申请
Receiver_Sync_Memory_Alloc();
TRACE(TRACE_RECEIVER_SYNC_FINE_ADDR, 3, 2);
dbg_time0 = Time_offset(2); dbg_time0 = Time_offset(2);
//搬移1055sample数据供定时同步,奇数slot处理偶buffer数据，反之 //搬移1055sample数据供定时同步,奇数slot处理偶buffer数据，反之
#ifndef RECV_DBG_DATA_TEST #ifndef RECV_DBG_DATA_TEST
if( 1 == (slot & 0x01) ) if( 1 == (slot & 0x01) )
{ {
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
} }
else else
{ {
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
} }
#else #else
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
#endif #endif
ape_csu_task_lookup(DMA_TAG_G2L, 1); ape_csu_task_lookup(DMA_TAG_G2L, 1);
@ -665,7 +764,7 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot, uint32_t proc_type)
ape_csu_task_lookup(DMA_TAG_G2G, 1); ape_csu_task_lookup(DMA_TAG_G2G, 1);
Receiver_Sync_Memory_Free();
RUN_CNT(TRACE_RECEIVER_SYNC_FINE_ADDR, 1); RUN_CNT(TRACE_RECEIVER_SYNC_FINE_ADDR, 1);
TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 2, Time_offset(2) ); TRACE_MAX(TRACE_RECEIVER_SYNC_FINE_ADDR, 2, Time_offset(2) );

12
APELib/Receiver_sync_first/src/receiver_Sync_First_Proc.s.c
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@ -191,17 +191,17 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
#ifndef RECV_DBG_DATA_TEST #ifndef RECV_DBG_DATA_TEST
if( 1 == (slot & 0x01) ) if( 1 == (slot & 0x01) )
{ {
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
} }
else else
{ {
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
} }
#else #else
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR; src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR; src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
#endif #endif
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0), ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0),

4
APELib/TestTask/src/Frame_test.s.c
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@ -42,8 +42,8 @@ void Test_Task()
*(output_data_ptr + idx) = cur_sfn * 100000 + cur_slot * 100 + idx; *(output_data_ptr + idx) = cur_sfn * 100000 + cur_slot * 100 + idx;
} }
uint32_t output_data_ptr_ddr_even = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;// 最终输出数据地址(ddr) uint32_t output_data_ptr_ddr_even = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;// 最终输出数据地址(ddr)
uint32_t output_data_ptr_ddr_odd = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR ;// 最终输出数据地址(ddr) uint32_t output_data_ptr_ddr_odd = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR ;// 最终输出数据地址(ddr)
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr), // ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr),
// output_data_ptr_ddr_even, // output_data_ptr_ddr_even,
// temp_len_32, // temp_len_32,

15
Common/inc/mem_def.h
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@ -104,17 +104,18 @@
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000 #define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000 #define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000)
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000)
#ifdef TX_RX_LOOP #ifdef TX_RX_LOOP
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR) #define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR) //TODO:需要修改成TX的61440对应buffer
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR) #define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR) //TODO:需要修改成TX的61440对应buffer
#elif !defined(TX_RX_LOOP) && !defined(RECV_DBG_DATA_TEST) #elif !defined(TX_RX_LOOP) && !defined(RECV_DBG_DATA_TEST)
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000) //!!!DDR_PHY_BASE 0x1E0000 #define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (0x70000000) //!!!DDR_PHY_BASE 0x1E0000
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000) // 0x1E0000 #define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (0x70200000) // 0x1E0000
#else #else
//---------------RECV测试用DDR空间-------------------------------------- //---------------RECV测试用DDR空间--------------------------------------
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x88800000) //61440*4 #define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (0x88800000) //61440*4
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x8883c000) // #define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (0x8883c000) //
#endif #endif
#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR (0x6BFC0000) // 61440*4 用于暂存数据供first_sync处理 #define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR (0x6BFC0000) // 61440*4 用于暂存数据供first_sync处理
#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理 #define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理

146
Config/Receiver_Sync_cfg_dm0.dat
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@ -589,4 +589,148 @@
0x01010000, 0x01010000,
0x01010000, 0x01010000,
0x01010000, 0x01010000,
0x01010000, 0x01010000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000200,
0x00000000,
0x00000000,
0x000a000a,
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,
0x00400006,
0x00000000,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,
0x00400006,
0x00000000,
0x00000000,
0x01010000,
0x03030202,
0x05050404,
0x07070606,
0x09090808,
0x0b0b0a0a,
0x0d0d0c0c,
0x0f0f0e0e,
0x11111010,
0x13131212,
0x15151414,
0x17171616,
0x19191818,
0x1b1b1a1a,
0x1d1d1c1c,
0x1f1f1e1e,
0x01010000,
0x05050404,
0x09090808,
0x0d0d0c0c,
0x11111010,
0x15151414,
0x19191818,
0x1d1d1c1c,
0x21212020,
0x25252424,
0x29292828,
0x2d2d2c2c,
0x31313030,
0x35353434,
0x39393838,
0x3d3d3c3c,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,
0x01000006,
0xffffffff,
0x00ffffff,

17
Config/Receiver_Sync_cfg_dm1.dat Normal file
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@ -0,0 +1,17 @@
0x7fff7fff,
0xfffafffa,
0x00280028,
0xff5fff5f,
0x01dd01dd,
0xfb62fb62,
0x0a440a44,
0xe8f2e8f2,
0x50065006,
0x50065006,
0xe8f2e8f2,
0x0a440a44,
0xfb62fb62,
0x01dd01dd,
0xff5fff5f,
0x00280028,
0xfffafffa,

8
MicroCode/Decimation_LTE/.mapu Normal file
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@ -0,0 +1,8 @@
{
"project": {
"incList": [
"../inc"
],
"libList": []
}
}

161
MicroCode/Decimation_LTE/inc/Configdecimation_LTE.dat Normal file
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@ -0,0 +1,161 @@
//m[0] ki
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//m[1] input
0x00000000,//0
0x00000000,
0x00000000,
0x00000000,
0x00000040,//4
0x00000200,
0x00000000,
0x00000000,
0x000a000a,//8
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff,//KBNumber
0x00400006,
0x00000000,//KM
0x00000000,
//m[2] lutaddr
0x00000000,//0
0x00000000,
0x00000000,
0x00000000,
0x00000040,//4
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//8
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,//KBNumber
0x00400006,
0x00000000,//KM
0x00000000,
//m[3] latch
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
0x00110110,
0x00000000,
//m[4] output
0x00000000,//0
0x00000000,
0x00000000,
0x00000000,
0x00000040,//4
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//8
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,//KBNumber
0x00400006,
0x00000000,//KM
0x00000000,
//m[5] SHU0.T5
0x01010000,
0x03030202,
0x05050404,
0x07070606,
0x09090808,
0x0b0b0a0a,
0x0d0d0c0c,
0x0f0f0e0e,
0x11111010,
0x13131212,
0x15151414,
0x17171616,
0x19191818,
0x1b1b1a1a,
0x1d1d1c1c,
0x1f1f1e1e,
//m[6] SHU0.T6
0x01010000,
0x05050404,
0x09090808,
0x0d0d0c0c,
0x11111010,
0x15151414,
0x19191818,
0x1d1d1c1c,
0x21212020,
0x25252424,
0x29292828,
0x2d2d2c2c,
0x31313030,
0x35353434,
0x39393838,
0x3d3d3c3c,
//m[7] Add0_top
0x00000000,//0
0x00000000,
0x00000000,
0x00000000,
0x00000040,//4
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//8
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,//KBNumber
0x00400006,
0x00000000,//KM
0x00000000,
//m[8] Add0_tail
0x00000000,//0
0x00000000,
0x00000000,
0x00000000,
0x00000040,//4
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//8
0xffffffff,
0xffffffff,
0x00000000,
0xffffffff,//KBNumber
0x01000006,
0xffffffff,//KM
0x00ffffff,

19
MicroCode/Decimation_LTE/inc/Decimation_LTE.h Normal file
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@ -0,0 +1,19 @@
#ifndef Decimation_LTE_H_
#define Decimation_LTE_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void Decimation_LTEAsm(v16u32 src);
int Decimation_LTE(
int *ConfigBaseAddr,
int add0_Addr0,
int InputAddr,
int add0_Addr1,
int coef_Addr,
int OutputAddr,
int data_length,
int shiftnum
);
#endif /* Decimation_LTE_H_ */

1
MicroCode/Decimation_LTE/inc/Decimation_LTE.inc Normal file
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@ -0,0 +1 @@
.section .text.m0, "ax"

61440
MicroCode/Decimation_LTE/inc/Test_input.dat Normal file
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File diff suppressed because it is too large Load Diff

16
MicroCode/Decimation_LTE/inc/hbfir1_fixed.txt Normal file
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@ -0,0 +1,16 @@
0x0000fffa,
0x00000028,
0x0000ff5f,
0x000001dd,
0x0000fb62,
0x00000a44,
0x0000e8f2,
0x7fff5006,
0x00005006,
0x0000e8f2,
0x00000a44,
0x0000fb62,
0x000001dd,
0x0000ff5f,
0x00000028,
0x0000fffa,

17
MicroCode/Decimation_LTE/inc/lut_coef.dat Normal file
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@ -0,0 +1,17 @@
0x7fff7fff,// 16
0xfffafffa,// 1
0x00280028,// 3
0xff5fff5f,// 5
0x01dd01dd,// 7
0xfb62fb62,// 9
0x0a440a44,// 11
0xe8f2e8f2,// 13
0x50065006,// 15
0x50065006,// 17
0xe8f2e8f2,// 19
0x0a440a44,// 21
0xfb62fb62,// 23
0x01dd01dd,// 25
0xff5fff5f,// 27
0x00280028,// 29
0xfffafffa,// 31

61440
MicroCode/Decimation_LTE/inc/signal_input_ant0.dat Normal file
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File diff suppressed because it is too large Load Diff

61440
MicroCode/Decimation_LTE/inc/signal_input_ant1.dat Normal file
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File diff suppressed because it is too large Load Diff

52656
MicroCode/Decimation_LTE/inc/signal_input_ant2.dat Normal file
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File diff suppressed because it is too large Load Diff

21
MicroCode/Decimation_LTE/inc/ucp2.h Normal file
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@ -0,0 +1,21 @@
#ifndef UCP2_H_
#define UCP2_H_
typedef int v16s32 __attribute__((__vector_size__(64)));
typedef int v16u32 __attribute__((__vector_size__(64)));
#define _DM0 __attribute__((section(".DM0")))
#define _DM1 __attribute__((section(".DM1")))
#define _DM2 __attribute__((section(".DM2")))
#define _DM3 __attribute__((section(".DM3")))
#define _DM4 __attribute__((section(".DM4")))
#define _DM5 __attribute__((section(".DM5")))
#define _DM6 __attribute__((section(".DM6")))
#define _DM7 __attribute__((section(".DM7")))
#define MPU_ADDR(addr) ((unsigned int)(addr) - 0x200000)
#define MPU_ENTRY __attribute__((mpu_entry))
#define MPU_FUNC __attribute__((mpu_func))
#endif /* UCP2_H_ */

9
MicroCode/Decimation_LTE/inc/ucp2_utils.h Normal file
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@ -0,0 +1,9 @@
#ifndef UCP2_UTILS_H_
#define UCP2_UTILS_H_
void write_to_dm0(char* src, unsigned int size);
void print_string(char* string);
void print_char(unsigned char src);
void print_int(unsigned int src);
#endif /* UCP2_UTILS_H_ */

20
MicroCode/Decimation_LTE/makefile.init Normal file
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@ -0,0 +1,20 @@
# set custom targets
# set toolchain home
ifeq ($(strip $(MaPU_TC_HOME)),)
MaPU_TC_HOME := /public/kangle/MaPUIDE/toolchain
endif
APP: all
LIB: libaadecimation_LTE.a
libaadecimation_LTE.a: $(OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GNU archiver'
ar rcs $@ $(OBJS)
@echo 'Finished building target: $@'
@echo ' '
.PHONY: LIB APP

78
MicroCode/Decimation_LTE/src/mpu0/Decimation_LTE.m0.asm Normal file
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@ -0,0 +1,78 @@
.section .text.m0, "ax"
.ifdef enable_dynamic_mim
.include "Decimation_LTE.inc"
.endif
.file "Decimation_LTE.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global Decimation_LTEAsm
Decimation_LTEAsm:
R1:M[0]->BIU1.T0;
IMA1:V(0x0202)->IMA1.T5;
IMA1:Vhigh(Ttmp,0x0303)->SHU0.T1;// 03030202
IMA1:V(0)->M[97] || IMA2:V(0)->IMA2.T5;
BIU1:Load(T0)(A++) -> M[0] || IMA2:Vhigh(Ttmp,0x0101)->SHU0.T3;
BIU1:Load(T0)(A++) -> M[1];
BIU1:Load(T0)(A++) -> M[2] || R0:M[97] -> IMA0.T2 || R1:M[97] -> IMA1.T2 || R2:M[97] -> IMA2.T2 || R3:M[97] -> IMA3.T2;// 0
BIU1:Load(T0)(A++) -> M[3] || SHU0:T3|T3->SHU0.T5;//01010000
BIU1:Load(T0)(A++) -> M[4];
BIU1:Load(T0)(A++) -> M[5];
BIU1:Load(T0)(A++) -> M[6];
BIU1:Load(T0)(A++) -> M[7];
BIU1:Load(T0)(A++) -> M[8];
R5:PreConfig(M[0]);
R5:WriteConf (Mfetch)->KI[0-15];
R0:M[1] -> BIU0.T2 ||R2:M[2] -> BIU2.T1;
R1:PreConfig(M[3]) ||R3:PreConfig(M[3]) ||R0:M[0] -> SHU0.T0;
R1:WriteConf->MC.RALL(I)||R3:WriteConf->MC.RALL(I)||R2:M[4] -> BIU2.T2; // coef
R1:WriteConf->MC.WALL(I)||R3:WriteConf->MC.WALL(I);
SHU0:Index(T0,T0,T1)->M[63];
R0:M[63] -> IMA0.T5 || R1:M[63] -> IMA1.T5 || R2:M[63] -> IMA2.T5 || R3:M[63] -> IMA3.T5;// 000000FF
R3:M[7] -> BIU3.T1;
R3:M[8] -> BIU3.T2;
IMA0: SetShiftMode (T5) -> SHIFTMODE0 || IMA1: SetShiftMode (T5) -> SHIFTMODE0 || IMA2: SetShiftMode (T5) -> SHIFTMODE0 || IMA3: SetShiftMode (T5) -> SHIFTMODE0;
BIU2:Load(T1)(A++) -> SHU0.T0;
BIU2:Load(T1)(A++) -> SHU0.T1;
MFetch:REPEAT @(8);
SHU0:Index(T1,T0,T5)(T7=T5+V(2))-> M[I++,A++]; // 01010000
SHU0:Index(T1,T0,T7)(T7=T7+V(2))-> M[I++,A++] || MFetch:REPEAT @(16);
R0:M[5] -> SHU0.T5 || R1:M[5] -> SHU1.T5 || R2:M[5] -> SHU2.T5 || R3:M[5] -> SHU3.T5; //010100000~1f1f1e1e
R0:M[6] -> SHU0.T6 || R1:M[6] -> SHU1.T6 || R2:M[6] -> SHU2.T6 || R3:M[6] -> SHU3.T6; //010100000~3d3d3c3c
R3:M[97] -> BIU3.T0; // add_0_top
R3:M[97] -> BIU3.T0; // add_0_tail
MFetch:REPEAT @(2);
BIU3:Store(T0,T1);
BIU3:Store(T0,T2);
MFetch:REPEAT @(4);
BIU0:wait 0 || SHU0:wait 12 || R0:wait 13 || IMA0:wait 15 || SHU1:wait 14 || R1:wait 15 || IMA1:wait 17 || SHU2:wait 16 || R2:wait 17 || IMA2:wait 19 || SHU3:wait 18 || R3:wait 19 || IMA3:wait 21 || BIU2:wait 37;
MFetch:Lpto %decimation_cyc @(KI0);
BIU0:load(T2)(A++)->SHU0.T0 || SHU0:Index(T2,T1,T6)(T7=T6+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:0 +T2*T2(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T3,T6)(T7=T6+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:0 +T2*T2(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T1,T6)(T7=T6+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:0 +T2*T2(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T3,T6)(T7=T6+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:0 +T2*T2(Shiftmode0)(S)(SSS)->IMA3.MR||BIU2:Store(T0,T2)(A++)(Mask);
BIU0:load(T2)(A++)->SHU0.T1 || SHU0:Index(T1,T0,T7)->SHU0.T4 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T3,T2,T7)->SHU1.T4 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T1,T0,T7)->SHU2.T4 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T3,T2,T7)->SHU3.T4 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
BIU0:load(T2)(A++)->SHU[0,1].T2 || SHU0:Index(T3,T2,T7)->SHU0.T2 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T1,T0,T7)->SHU1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T3,T2,T7)->SHU2.T2 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T1,T0,T7)->SHU3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR||BIU2:Store(T0,T2)(A++)(Mask);
BIU0:load(T2)(A++)->SHU[0,1].T3 || SHU0:Index(T2,T4,T5)(T7=T5+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T5)(T7=T5+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T5)(T7=T5+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T5)(T7=T5+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
BIU0:load(T2)(A++)->SHU[1,2].T0 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR||BIU2:Store(T0,T2)(A++)(Mask);
BIU0:load(T2)(A++)->SHU[1,2].T1 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
BIU0:load(T2)(A++)->SHU[2,3].T2 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR||BIU2:Store(T0,T2)(A++)(Mask);
BIU0:load(T2)(A++)->SHU[2,3].T3 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
BIU0:load(T2)(A++)->SHU3.T0 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
BIU0:load(T2)(A++)->SHU3.T1 || SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA0.MR || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA1.MR || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA2.MR || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->IMA3.MR;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || IMA0:MR+T0*T1(Shiftmode0)(S)(SSS)->BIU2.T0 || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || IMA1:MR+T0*T1(Shiftmode0)(S)(SSS)->BIU2.T0 || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || IMA2:MR+T0*T1(Shiftmode0)(S)(SSS)->BIU2.T0 || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0 || IMA3:MR+T0*T1(Shiftmode0)(S)(SSS)->BIU2.T0;
SHU0:Index(T2,T4,T7)(T7=T7+V(2))->IMA0.T0 || SHU1:Index(T0,T4,T7)(T7=T7+V(2))->IMA1.T0 || SHU2:Index(T2,T4,T7)(T7=T7+V(2))->IMA2.T0 || SHU3:Index(T0,T4,T7)(T7=T7+V(2))->IMA3.T0;
decimation_cyc:
BIU0:wait 0 || SHU0:wait 0 || R0:wait 0 || IMA0:wait 0 || SHU1:wait 0 || R1:wait 0 || IMA1:wait 0 || SHU2:wait 0 || R2:wait 0 || IMA2:wait 0 || SHU3:wait 0 || R3:wait 0 || IMA3:wait 0 || BIU2:wait 0;
MFetch:Repeat @(45);
MFetch:MPU.STOP;

28
MicroCode/Decimation_LTE/src/spu/Decimation_LTE.s.c Normal file
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void Decimation_LTE(
int *ConfigBaseAddr,
int add0_Addr0,
int InputAddr,
int add0_Addr1,
int coef_Addr,
int OutputAddr,
int data_length,
int shiftnum
)
{
int *Para = ConfigBaseAddr;
int Cycle = ((data_length>>1)+63)>>6;
Para[0] = Cycle;
Para[1] = ((15-shiftnum)&0xff); //DeOfdm:16, Son:15
Para[1 * 16] = add0_Addr0;
Para[1 * 16 + 1] = add0_Addr0;
Para[2 * 16] = coef_Addr;
Para[4 * 16] = OutputAddr;
Para[4 * 16+12] = data_length<<1;
Para[7 * 16] = add0_Addr0;
Para[8 * 16] = add0_Addr1;
}

51
MicroCode/Decimation_LTE/src/spu/main.s.c Normal file
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#ifndef REMOVE_MC_TEST
#include "ucps2.h"
#include "ucpm2.h"
#include <Decimation_LTE.h>
__DM1 int Add0_addr0[16] = {0};
__DM1 int InputData[] = {
#include <signal_input_ant2.dat>
};
__DM1 int Add0_addr1[14] = {0};
__DM0 int coef_addr[] = {
#include <lut_coef.dat>
};
__DM2 int OutputData[33000]={0};
__DM3 int Config[] = {
#include <Configdecimation_LTE.dat>
};
__DM3 v16s32 SVRReg = {
0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0
};
int main(void)
{
volatile int a ;
int data_length=17536+16;
int shiftnum=16; // DeOfdm: 16, Son: 15
Decimation_LTE((int*)Config,MPU_ADDR(Add0_addr0),MPU_ADDR(InputData),MPU_ADDR(Add0_addr1),MPU_ADDR(coef_addr),MPU_ADDR(OutputData),data_length,shiftnum);
SVRReg[0] = MPU_ADDR(Config);
Decimation_LTEAsm(SVRReg);
a=__ucps2_getStatB();
__ucps2_delay();
}
#endif //DEBUG_MC