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1.更新信道估计模块，2.新增APE3，CORE_ODD区分symb地址相关处理

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HUOHUO 2025-04-21 09:26:00 -07:00
parent 02ccf4995a
commit 78c92355a8
30 changed files with 899 additions and 262 deletions
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1
.gitignore vendored
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@ -11,6 +11,7 @@ Debug/
/.metadata/
/APE0/Transmitter/**
/APE0/TestTask/**
/APE3/Receiver_symb/**
/APE4/Receiver_sync/**
/APE4/TestTask/**
/APE5/Receiver_symb/**

7
.vscode/settings.json vendored
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@ -30,6 +30,11 @@
"transmitter_func.h": "c",
"freoffestimpl.h": "c",
"freoffcompimpl.h": "c",
"freoffcomp.h": "c"
"freoffcomp.h": "c",
"channelequimpl.h": "c",
"fft4096int32.h": "c",
"channelestimpl.h": "c",
"ucps2.h": "c",
"channelest.h": "c"
}
}

36
APE3/ApeCommon/inc/ape_common.h Normal file
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@ -0,0 +1,36 @@
/******************************************************************
* @file ape_common.h
* @brief: [file description]
* @author: xuekun.zhang
* @Date 2022年1月11日
* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
* Change_date Owner Change_content
* 2022年1月11日 xuekun.zhang create file
*****************************************************************/
#ifndef APE_COMMON_H
#define APE_COMMON_H
/**************************include******************************/
#include "type_define.h"
#define APE_DM0 DM7
#define APE_DM1 DM6
#define APE_DM2 DM5
#define APE_DM3 DM4
#define __APE_DM0 __DM7
#define __APE_DM1 __DM6
#define __APE_DM2 __DM5
#define __APE_DM3 __DM4
#define DM_TO_CSU_ADDR(addr) ((uint32_t)(addr))
#define IM_TO_CSU_ADDR(addr) (((uint32_t)(addr)) + 0x200000)
#define DMA_TAG_G2L 16
#define DMA_TAG_L2G 17
#define DMA_TAG_G2G 18
#define DMA_TAG_CHAIN 19
extern __APE_DM3 v16s32 SVRReg;
#endif

32
APE3/ApeCommon/src/ape_common.s.c Normal file
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@ -0,0 +1,32 @@
/******************************************************************
* @file ape_common.c
* @brief: [file description]
* @author: xuekun.zhang
* @Date 2022年1月11日
* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
* Change_date Owner Change_content
* 2022年1月11日 xuekun.zhang create file
*****************************************************************/
/**************************include******************************/
#include <ape_common.h>
#include "log_interface.h"
/**************************function******************************/
//微码配置寄存器
__APE_DM3 v16s32 SVRReg = {
0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0
};
//uint32_t g_dma_tag_g2l = DMA_TAG_G2L;
uint32_t g_dma_tag_l2g = DMA_TAG_L2G;
////自定义空间的log头定义
__APE_DM3 uint32_t g_ape_log_header[(LOG_TOTAL_HDR_SIZE + 3)>>2];
//静态申请log空间
__APE_DM3 uint32_t g_ape_log_static_buf[LOG_DM_BUF_NUM * LOG_MAX_LEN_WORD];//log 宏定义修改，原宏名表达不准确

103
APE3/ApeTask/src/Fucp_Ape3_Init.s.c Normal file
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@ -0,0 +1,103 @@
#ifndef IDE_TEST
/******************************************************************
* @file Ucp_Ape1_Init.s.c
* @brief: [file description]
* @author: guicheng.liu
* @Date 2022年1月25日
* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
* Change_date Owner Change_content
* 2022年1月25日 guicheng.liu create file
*****************************************************************/
/**************************include******************************/
#include <type_define.h>
#include "receiver_symb_func.h"
#include "ape_common.h"
#include "task_define.h"
#include "log_interface.h"
#include "trace.h"
/**************************function******************************/
/*!
* @brief: 在Phy init的时候注册物理层管理任务
* @author: guicheng.liu
* @Date: 2022年2月28日
*/
/* 收到消息后创建任务 */
void ape3_event_task(uint32_t addr, uint32_t size)
{
return;
}
/* 收到消息后删除任务 */
void ape3_event_task_del(uint32_t addr, uint32_t size)
{
uint32_t ape_id = get_core_id();
//osp_del_task_all(NR_SCS_30K);
return;
}
/*!
* @brief: 在Phy init的时候注册物理层管理任务
* @author: guicheng.liu
* @Date: 2022年2月28日
*/
void Phy_Task_Ape3_Reg()
{
// osp_task_info_ex ape3_event_task_info = {50, "ape3_event_task1", 50, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape3_event_task};
// osp_task_info_ex ape3_event_task_info_del = {51, "ape3_event_task_del1", 51, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape3_event_task_del};
osp_task_info_ex mgr_task = {PHY_TASK_RECIEVER_SYMB, "Receiver_Symb", PHY_TASK_PRI_RECEIVER_SYMB, 4096, OSP_EVENT_TYPE, 0x000, 0x000, 0, (OSP_TASKINIT_FUNC)Receiver_Symb_Init, (OSP_TASKENTRY_FUNC)Receiver_Symb_Task};
// osp_task_create(&ape3_event_task_info);
// osp_task_create(&ape3_event_task_info_del);
osp_task_create(&mgr_task);
LOG_INFO_S("APE3 finish task create!\n");
return ;
}
///*!
//* @brief: Phy初始化函数, 每个APE上都需要有一个名字相同的函数
//* @author: guicheng.liu
//* @Date: 2022年1月25日
//*/
void phy_init()
{
//初始化函数里面尽量不要输出log，因为可能初始化时msg_transfer_open还未完成
log_level_e log_level = INFO;
log_pool_init();
set_log_level(log_level);
//memset(&g_phy_cell_cfg, 0, sizeof(phy_cell_cfg_t));
Phy_Task_Ape3_Reg();
}
///*!
//* @brief: 给osp调用，勿删
//* @author: guicheng.liu
//* @Date: 2022年11月3日
//*/
//void soc_drv_init()
//{
//}
//
///*!
//* @brief: 给osp调用，勿删
//* @author: guicheng.liu
//* @Date: 2022年11月3日
//*/
//void tod_int_init()
//{
//}
#endif

144
APE3/Makefile Normal file
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@ -0,0 +1,144 @@
############################
# mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=Block_Transform Channel_Est Channel_Equ Fre_est Fre_comp
############################
# tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin
#GDB_PATH=/opt/sdk/ucp2.0_sdk/simulator/ucp2-gdb
#SIM_PATH=/opt/sdk/ucp2.0_sdk/simulator/UCP_Simulator_V2.0
#OPENOCD_GDB_PATH=/opt/sdk/ucp_sdk/apc_tools_ima/bin/gdb-ucps-openocd
#LPATH1=/opt/sdk/ucp2.0_sdk/lib/ucps2/lib
#LPATH2=/opt/sdk/ucp2.0_sdk/lib/clang/12.0.0/lib/ucps2
UCP_HOME=${MaPU_TC_HOME}/bin/ucp2
GDB_PATH=${MaPU_TC_HOME}/bin/ucp2/ucp2-gdb
SIM_PATH=${MaPU_TC_HOME}/bin/ucp2/ucp2-simulator
OPENOCD_GDB_PATH=${MaPU_TC_HOME}/ucps-openocd/ucps-openocd-gdb
LPATH1=${MaPU_TC_HOME}/lib/ucp2/release
LPATH2=${MaPU_TC_HOME}/lib/ucp2/release
#############################
export UCP_HOME
############################
# varaibles for project construction using new ucp toolchain
# DO NOT MODIFY
SPU_MAIN_C_FILE:=$(shell find . -name "app.s.c")
SPU_C_FILES:=$(shell find . -name "*.s.c")
SPU_C_OBJECT_FILES:=$(subst .c,.c.o,${SPU_C_FILES})
SPU_ASM_FILES:=$(shell find . -name "*.s.asm")
SPU_ASM_OBJECT_FILES:=$(subst .asm,.asmb.o,${SPU_ASM_FILES})
MPU_ASM_FILES:=$(shell find . -name "*.m.asm" -or -name "*.m0.asm" -or -name "*.m1.asm")
MPU_ASM_OBJECT_FILES:=$(subst .asm,.asmb.o,${MPU_ASM_FILES})
##INC_DIRS+=$(shell find ${MaPU_TC_HOME}/include/ucp2 -type d)
INC_DIRS+=$(shell find ../${MICRO_CODE_DIR} -name inc -type d)
INC_DIRS+=$(shell find ../${COMMON_LIB_DIRS} -name inc -type d)
INC_DIRS+= ../Interface
INC_DIRS+= ../Inc
INC_DIRS+=$(shell find ./ -name inc -type d)
override INC_DIRS_OPTION:=$(patsubst %,-I%,${INC_DIRS})
override WORK_DIR:=$(abspath $(lastword $(MAKEFILE_LIST)))
override PROJECT_NAME:=$(notdir $(patsubst %/,%,$(dir $(WORK_DIR))))
ifeq (${mpu}, dyn)
LD_SCRIPT=$(shell realpath ${PWD}/Common/Scripts/ape3-Cache128-noMPUC-dynamic.ld)
else
LD_SCRIPT=$(shell realpath ${PWD}/Common/Scripts/ape3-Cache128-noMPUC.ld)
endif
EXE_FILE_NAME=${PROJECT_NAME}.out
#LINK_L_OPTION:=$(patsubst %,-L../%,${COMMON_LIB_DIRS})
LINK_L_OPTION=-L../Lib
LINK_l_OPTION:=$(patsubst %,-l%,${COMMON_LIB_DIRS})
APE_LINK_L_OPTION=-L../Lib
APE_LINK_l_OPTION:=$(patsubst %,-l%,${PROJECT_NAME})
ifneq (${MICRO_CODE_LIBS}, )
LINK_MPU_L_OPTION=-L../Lib/MicroLib
LINK_MPU_l_OPTION:=$(patsubst %,-l%,${MICRO_CODE_LIBS})
else
LINK_MPU_L_OPTION:=
LINK_MPU_l_OPTION:=
endif
LINK_PLATFORM_L_OPTION=-L../Lib/OspLib
#LINK_PLATFORM_l_OPTION:=-lape
ifeq (${tb}, PDSCH)
LINK_PLATFORM_l_OPTION:=
else ifeq (${tb}, DL)
LINK_PLATFORM_l_OPTION:=
else
LINK_PLATFORM_l_OPTION:=-lape_spu
endif
# this flag could be specified by user, default to build debug info
debug:=0
export debug
ifeq (${debug},1)
ASM_DEBUG_FLAGS:=-g
C_DEBUG_FLAGS:=-O0 -g
else ifeq (${debug},3)
ASM_DEBUG_FLAGS:=
C_DEBUG_FLAGS:=-O3
else
ASM_DEBUG_FLAGS:=
C_DEBUG_FLAGS:=-O2
endif
############################
all:
@for dir in ${COMMON_LIB_DIRS}; do \
make LIB -C $${dir} ; \
done
%.s.c.o: %.s.c
@${UCP_HOME}/clang --target=ucps2 -c ${INC_DIRS_OPTION} $^ -o $@ ${C_DEBUG_FLAGS} ${TEST_OPTION} ${PRJ_OPTION} ${MIM_DYNAMIC_OPTION} ${DIAG_STACK_OPTION}
%.s.asmb.o: %.s.asm
@${UCP_HOME}/llvm-mc -arch=ucps2 -filetype=obj $^ -o $@ ${ASM_DEBUG_FLAGS}
${EXE_FILE_NAME}:
${UCP_HOME}/ld.lld -m ucps2 -o $@ $(LPATH1)/crt0.o \
$(LPATH1)/crtend.o \
${APE_LINK_L_OPTION} ${APE_LINK_l_OPTION} \
${LINK_L_OPTION} ${LINK_l_OPTION} \
${LINK_MPU_L_OPTION} ${LINK_MPU_l_OPTION} \
${LINK_PLATFORM_L_OPTION} ${LINK_PLATFORM_l_OPTION} \
-L$(LPATH2) \
-L$(LPATH1) -lm -lc -lgloss \
-lclang_rt.builtins-ucps2 -T ${LD_SCRIPT}
APP: ${EXE_FILE_NAME}
lib%.a: ${SPU_C_OBJECT_FILES} ${SPU_ASM_OBJECT_FILES} ${MPU_ASM_OBJECT_FILES}
ar rcs -o $@ ${SPU_C_OBJECT_FILES} ${SPU_ASM_OBJECT_FILES} ${MPU_ASM_OBJECT_FILES} && chmod +x $@
LIB: lib${PROJECT_NAME}.a
Dis: APP
${UCP_HOME}/llvm-objdump -d --start-address=0x40000 --line-numbers --source ${EXE_FILE_NAME} > app.s.dis;
#${UCP_HOME}/llvm-objdump -arch-name=ucpm2 -no-show-raw-insn -no-leading-addr -d ${EXE_FILE_NAME} -start-address=0x40000 -stop-address=0x60000 > app.m.dis;
# direct simulaton without gui
DSim: APP
@${SIM_PATH} -m=printChar -elf-file=${EXE_FILE_NAME} -ores -allcf && \
echo "software simulation finished"
DSimGDB: APP
@${SIM_PATH} -m=gdb -elf-file=${EXE_FILE_NAME} -allcf -exec-path=./ -port=1234&& \
echo "software simulation finished"
GDB: APP
@${OPENOCD_GDB_PATH} ./${EXE_FILE_NAME}&& \
echo "software GDB finished"
clean:
@for dir in ${COMMON_LIB_DIRS}; do \
if [ -e $${dir} ]; then \
make clean -C $${dir} ; \
fi;\
done
@rm -rf *.lof *.out *.map *.mmap *.sct *.tab *.s *.dis *~ *.def *.xml
@rm -rf *.daidir work *.lib++ *~ *.rc csrc *.key filelist.f simv*
@rm -rf DVEfiles vc_hdrs.h urgReport *.rc *.vpd *.log
@rm -rf *.sym *.data *.bak slot-*.txt PC_Line*.txt codes.txt UCPMDis.txt *.saif
@rm -rf Simulator_*.dat saif.cmds Run_Cycle.dat *.elf ucps_pc_code.txt Receiver_symb
@rm -rf Executed_Pipeline.csv
@find . -name "*.o" -exec rm -f {} \;
@find . -name "*.a" -exec rm -f {} \;
.PRECIOUS: %.s.c.o
.PHONY: APP clean all

0
APE3/MpuAsmInc/.gitkeep Normal file
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2
APELib/Receiver_symb/inc/ChannelEstImpl.h
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@ -5,6 +5,6 @@
#include <ChannelEst.h>
#include "stdio.h"
void ChannelEstImpl(v16u32 * SVRReg,int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr);
void ChannelEstImpl(int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr);
#endif //DEBUG_MC

4
APELib/Receiver_symb/inc/channelEquImpl.h
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@ -10,15 +10,17 @@
#include "AddCP.h"
#include "ape_common.h"
#include "type_define.h"
#include "ByteCopy.h"
#include "common.h"
void ChannelEquImpl(
v16u32 * SVRReg,
int *CfgFft4096,
int *CfgEQ21Part1,
int *ConfigBaseAddr3,
int *CfgIFFT4096,
int *ConfigDataTurn,
int *ConfigAddCp,
int *CfgByteCopy,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,

21
APELib/Receiver_symb/inc/receiver_symb_macro.h
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@ -14,10 +14,12 @@
//DO NOT MODIFY
//=======================================================================
//微码配置空间长度定义，单位为word(4Byte)
#define RECEIVER_SYMB_FreOffEst_CFG1_LENGTH (0x0090)
#define RECEIVER_SYMB_FreOffComp_CFG2_LENGTH (0x0040)
#define RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH (0x0070)
#define RECEIVER_SYMB_ChannelEst_CFG4_LENGTH (0x0050)
#define RECEIVER_SYMB_ChannelEst_CFG4_LENGTH (0x0070)
#define RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH (0x0350)
#define RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH (0x00E0)
#define RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH (0x00C0)
@ -28,9 +30,19 @@
#define RECEIVER_SYMB_DeTransform2_CFG8_LENGTH (0x0060)
#define RECEIVER_SYMB_DeTransform4_CFG9_LENGTH (0x0080)
#define RECEIVER_SYMB_ByteSet_CFG10_LENGTH (0x0040)
#define RECEIVER_SYMB_ByteCopy_CFG10_LENGTH (0x0030)
#define RECEIVER_SYMB_FREOFF_CFG_LENGTH (RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH )
#define RECEIVER_SYMB_CHANNELEST_CFG_LENGTH (RECEIVER_SYMB_ChannelEst_CFG4_LENGTH)
#define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH )
#define RECEIVER_SYMB_DeTransformer_CFG_LENGTH (RECEIVER_SYMB_DeTransform2_CFG8_LENGTH + RECEIVER_SYMB_DeTransform4_CFG9_LENGTH)
#define RECEIVER_SYMB_COMMEN_CFG_LENGTH (RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH + RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH + RECEIVER_SYMB_DeTransformer_CFG_LENGTH)
//SPU查找表各字段长度定义,单位为word(4Byte)
@ -47,6 +59,13 @@
//SPU查找表各字段长度定义,单位为word(4Byte)
//=======================================================================

21
APELib/Receiver_symb/src/ChannelEstImpl.s.c
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@ -2,8 +2,11 @@
#include <ChannelEst.h>
#include "ucps2.h"
#include "ucpm2.h"
#include "common.h"
#include "ape_common.h"
#include "drv_ape.h"
void ChannelEstImpl(v16u32 * SVRReg,int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr)
void ChannelEstImpl(int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr)
{
for(int i=0;i<32;i++){
@ -11,18 +14,12 @@ void ChannelEstImpl(v16u32 * SVRReg,int *ConfigAddr, int *InAddr1, int *InAddr2,
InAddr2[i+1024] = InAddr2[i];
}
volatile int a;
ChannelEst(ConfigAddr, MPU_ADDR(InAddr1),MPU_ADDR(InAddr2),MPU_ADDR(OutAddr));
SVRReg[0][0] = MPU_ADDR(ConfigAddr);
channelEstAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
for(int i=32;i<4096;i++){
OutAddr[i] = 0;
}
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
SVRReg[0] = MPU_ADDR(ConfigAddr);
channelEstAsm(SVRReg);
return;
}

123
APELib/Receiver_symb/src/channelEquImpl.s.c
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@ -3,15 +3,18 @@
#include "ucpm2.h"
#include <channelEquImpl.h>
#ifdef IDE_TEST
#include <Test_Func.h>
#endif
void ChannelEquImpl(
v16u32 * SVRReg,
int *CfgFft4096,
int *CfgEQ21Part1,
int *ConfigBaseAddr3,
int *CfgIFFT4096,
int *ConfigDataTurn,
int *ConfigAddCp,
int *CfgByteCopy,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,
@ -53,7 +56,8 @@ void ChannelEquImpl(
(uint64_t)DM_TO_CSU_ADDR(channelEst_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
1);
Fft4096Int32(
(int)CfgFft4096,
@ -68,34 +72,28 @@ void ChannelEquImpl(
MPU_ADDR(Scalep),
MPU_ADDR(Scale0)
);
SVRReg[0][0] = MPU_ADDR(CfgFft4096);
Fft4096Int32Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
SVRReg[0] = MPU_ADDR(CfgFft4096);
Fft4096Int32Asm(SVRReg);
WAIT_MPU_STOP;
/*****************************************channelEqu*****************************************/
// for(int m=0;m<4096;m++){
// *(Fft_est_dm3_ptr + 4096 + m) = Fft_est_dm3_ptr[m];
// }
for(int j=0;j<numSym;j++){
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*j + 68) ,
if(j==0){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*j + 68) ,
(uint64_t)DM_TO_CSU_ADDR(InData_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
1);
}
// FFT of Data
Fft4096Int32(
(int)CfgFft4096,
@ -110,27 +108,24 @@ void ChannelEquImpl(
MPU_ADDR(Scalep),
MPU_ADDR(Scale0)
);
SVRReg[0][0] = MPU_ADDR(CfgFft4096);
Fft4096Int32Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
SVRReg[0] = MPU_ADDR((int)CfgFft4096);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
Fft4096Int32Asm(SVRReg);
WAIT_MPU_STOP;
// 构造第二根天线数据，与第一根相同
for(int m=0;m<4096;m++){
*(Fft_outputdata_dm3_ptr + 4096 + m) = Fft_outputdata_dm3_ptr[m];
}
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
ByteCopy((int)CfgByteCopy, MPU_ADDR(InData_dm0_ptr),MPU_ADDR(Fft_outputdata_dm3_ptr + 4096),16384);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
int *Equ_Output = InData_dm0_ptr + 0x1000; //LENGTH 0x2000 (the second ant occupied additional space 0x1000)
int *InOut2_dm1_ptr = tmp0; //LENGTH 0x1000
int *InOut3_dm0_ptr = InData_dm0_ptr + 0x3000; //LENGTH 0x2000
int *InOut1_dm1_ptr = tmp0 + 0x1000; //LENGTH 0x1000
WAIT_MPU_STOP;
EQ21Part1(
@ -145,17 +140,21 @@ void ChannelEquImpl(
MPU_ADDR(InOut2_dm1_ptr), //dm1
MPU_ADDR(InOut3_dm0_ptr) //dm0
);
SVRReg[0][0] = MPU_ADDR(CfgEQ21Part1);
EQ21Part1Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
SVRReg[0] = MPU_ADDR(CfgEQ21Part1);
EQ21Part1Asm(SVRReg);
if(j<numSym-1){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*(j+1) + 68) ,
(uint64_t)DM_TO_CSU_ADDR(InData_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
}
WAIT_MPU_STOP;
int *Equ_Output_2 = available_ptr_dm2; //第一根天线均衡输出
int *Equ_Output_21 = available_ptr_dm2 + 0x2000; //第二根天线均衡输出
EQ1Part2(
ConfigBaseAddr3,
NRE,
@ -167,27 +166,11 @@ void ChannelEquImpl(
MPU_ADDR(Equ_Output_2),
MPU_ADDR(Equ_Output_21)
);
SVRReg[0][0] = MPU_ADDR(ConfigBaseAddr3);
EQ1Part2Asm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
// for (size_t i = 0; i < 4096; i++) {
// int32_t num = Equ_Output_2[i];
//
// int16_t real = (int16_t)(num & 0xFFFF);
// int16_t imag = (int16_t)(num >> 16);
// real /= 8;
// imag /= 8;
//
// *(Equ_Output + i) = ((int32_t)imag << 16) | ((uint16_t)real);
// }
SVRReg[0]= MPU_ADDR(ConfigBaseAddr3);
EQ1Part2Asm(SVRReg);
WAIT_MPU_STOP;
int *Temp1 = Fft_outputdata_dm3_ptr; // 缓存
IFFT4096DataTurn(
(int)ConfigDataTurn,
1,
@ -198,20 +181,13 @@ void ChannelEquImpl(
MPU_ADDR(Temp1) //dm3 无效
);
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
SVRReg[0][0] = MPU_ADDR(ConfigDataTurn);
IFFT4096DataTurnAsm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
SVRReg[0]= MPU_ADDR(ConfigDataTurn);
IFFT4096DataTurnAsm(SVRReg);
WAIT_MPU_STOP;
int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
IFFT4096(
(int)CfgIFFT4096,
1,
@ -222,15 +198,13 @@ void ChannelEquImpl(
MPU_ADDR(CalAddr0), //DM2
MPU_ADDR(CalAddr1), //DM3
MPU_ADDR(CalAddr2)); //DM1
SVRReg[0][0] = MPU_ADDR(CfgIFFT4096);
IFFT4096Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
SVRReg[0] = MPU_ADDR(CfgIFFT4096);
IFFT4096Asm(SVRReg);
WAIT_MPU_STOP;
int CPLength0 = 352;
int CPLength1 = 288;
AddCP(
(int) ConfigAddCp,
2,
@ -244,12 +218,12 @@ void ChannelEquImpl(
MPU_ADDR(Lut_phase) //
);
SVRReg[0][0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
SVRReg[0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(SVRReg);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR((Equ_Output_2+CPLength0)),
(uint64_t)res_ptr,
@ -258,6 +232,7 @@ void ChannelEquImpl(
1);
res_ptr = res_ptr + 16384;
}
}

29
APELib/Receiver_symb/src/channelEqu_proc.s.c
View File

@ -1,6 +1,6 @@
#include "receiver_symb_func.h"
#include "ByteSet.h"
void ChannelEqu_Proc(
uint32_t* param_data_ptr,
@ -14,23 +14,24 @@ void ChannelEqu_Proc(
//局部变量定义
int32_t *cfg_addr = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH;
int32_t *lut_addr = receiver_symb_config_dm2_ptr + RECEIVER_SYMB_PilotOrig_LUT1_LENGTH;
uint32_t *ConfigByteSet = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH;
// Temporary input for test
uint32_t * InputNoise = ((((uint32_t)&temp_dm3_ptr[0] + 4096*2 + 4095)>>12)<<12);
for(int i=0;i<4096;i++){
InputNoise[i] = 0;
}
uint32_t res_ptr = CHANNELEQU_DATA_DDR_PTR; //Store result of Equ
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
// Temporary input for test
uint32_t * InputNoise = ((((uint32_t)&temp_dm3_ptr[0] + 4095)>>12)<<12);
ByteSet(ConfigByteSet,0,MPU_ADDR(InputNoise),16384);
SVRReg[0] = MPU_ADDR(ConfigByteSet);
ByteSetAsm(SVRReg);
WAIT_MPU_STOP;
// available address space for channelEqu
uint32_t * available_ptr_dm0 = temp_dm0_ptr;
uint32_t * available_ptr_dm1 = temp_dm1_ptr + 0x1000;
uint32_t * available_ptr_dm1 = temp_dm1_ptr;
uint32_t * available_ptr_dm2 = temp_dm2_ptr;
uint32_t * available_ptr_dm3 = InputNoise + 0x1000;
@ -42,6 +43,8 @@ void ChannelEqu_Proc(
uint32_t *CfgIFFT4096 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH;
uint32_t *CfgIFFT4096TURN = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH;
uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH;
uint32_t *CfgByteCopy= receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH;
// LUT
uint32_t *Lut_W4096 = lut_addr;
uint32_t *Lut_EqFactor0 = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH;
@ -53,7 +56,7 @@ void ChannelEqu_Proc(
// channelEst and data
uint32_t *InputCHEst_ddr_ptr = (uint32_t *)CHANNELEST_DATA_DDR_PTR;
uint32_t *InputData_ddr_ptr = (uint32_t *)COMPENSATED_DATA_DDR_PTR;
ChannelEquImpl(SVRReg,CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,
ChannelEquImpl(CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,CfgByteCopy,
available_ptr_dm0,
available_ptr_dm1,
available_ptr_dm2 ,

43
APELib/Receiver_symb/src/channelEst_Proc.s.c
View File

@ -1,6 +1,6 @@
#include "receiver_symb_func.h"
#include "ByteSet.h"
void ChannelEst_Proc(
uint32_t *param_ptr,
@ -17,16 +17,22 @@ void ChannelEst_Proc(
uint32_t res_ptr = CHANNELEST_DATA_DDR_PTR;
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
// Get Configuration and LUT
uint32_t *ConfigAddr_channelEst = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH;
uint32_t *Pilot_orig_LUT = receiver_symb_config_dm2_ptr;
uint32_t *InputPilotAddr = (uint32_t *)time_data_dm0_ptr;
uint32_t *channelEstOutAddr = (uint32_t *)(temp_dm1_ptr);
uint32_t *ConfigByteSet = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH;
ByteSet(ConfigByteSet,0,MPU_ADDR(channelEstOutAddr),32768);
SVRReg[0] = MPU_ADDR(ConfigByteSet);
ByteSetAsm(SVRReg);
int numSub = 2;
int sliceIndex[2] = {1024,31268}; // position of pilot
for(int subIndex=0;subIndex<numSub;subIndex++){
time_data_ddr_ptr = COMPENSATED_DATA_DDR_PTR + sliceIndex[subIndex];
time_data_ddr_ptr = COMPENSATED_DATA_DDR_PTR + sliceIndex[subIndex]*4;
time_data_length = 1024;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
@ -35,25 +41,16 @@ void ChannelEst_Proc(
DMA_TAG_G2L,
0);
// Get Configuration and LUT
uint32_t *ConfigAddr_channelEst = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH;
uint32_t *Pilot_orig_LUT = receiver_symb_config_dm2_ptr;
uint32_t *InputPilotAddr = (uint32_t *)time_data_dm0_ptr;
uint32_t *channelEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0080);
ChannelEstImpl(SVRReg,ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr);
ChannelEstImpl(ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr + subIndex*4096);
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)channelEstOutAddr),
(uint64_t)res_ptr,
4096*4 ,
DMA_TAG_L2G,
1);
res_ptr += 0x4000;
}
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)channelEstOutAddr),
(uint64_t)res_ptr,
4096*2*4 ,
DMA_TAG_L2G,
1);
}

42
APELib/Receiver_symb/src/freOffCompImpl.s.c
View File

@ -13,62 +13,48 @@ void freOffCompImpl(int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOut
volatile int a = 1;
int count = 7680;
int count = 120;
freEstOutAddr[0] = freEstOutAddr[0]>>10;
int increment = freEstOutAddr[0];
int increment = freEstOutAddr[0]*128;
uint32_t time0, time1;
for(int i=0;i<1;i++)
for(int i=0;i<4;i++)
{
int res_ptr_offset = i*count;
int res_ptr_offset = i*count*128;
int *input_data_ptr = ava_ptr_dm3;
int *fre_comp_exp_ptr = ava_ptr_dm2;
int *output_data_ptr = ava_ptr_dm3;
time0 = Time_offset(0);
int time_data_length = count;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)data_ptr_ddr,
(uint64_t)DM_TO_CSU_ADDR(input_data_ptr),
time_data_length*4,
DMA_TAG_G2L,
1);
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 9, time1-time0);
time0 =time1;
int time_data_length = count*128;
cordicSC(ConfigAddr_cordic,MPU_ADDR(freEstOutAddr),MPU_ADDR(fre_comp_exp_ptr),increment,count);
WAIT_MPU_STOP;
SVRReg[0] = MPU_ADDR(ConfigAddr_cordic);
cordicSCAsm(SVRReg);
WAIT_MPU_STOP;
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 10, time1-time0);
time0 =time1;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)data_ptr_ddr,
(uint64_t)DM_TO_CSU_ADDR(input_data_ptr),
time_data_length*4,
DMA_TAG_G2L,
1);
WAIT_MPU_STOP;
freOffComp(ConfigAddr_comp,MPU_ADDR(input_data_ptr),MPU_ADDR(fre_comp_exp_ptr),MPU_ADDR(output_data_ptr));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
WAIT_MPU_STOP;
SVRReg[0] = MPU_ADDR(ConfigAddr_comp);
freOffCompAsm(SVRReg);
WAIT_MPU_STOP;
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 11, time1-time0);
time0 =time1;
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr),
(uint64_t)(res_ptr_ddr + res_ptr_offset),
time_data_length*4 ,
DMA_TAG_L2G,
1);
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 12, time1-time0);
time0 =time1;
}

2
APELib/Receiver_symb/src/transform_Proc.s.c
View File

@ -85,7 +85,7 @@ void Transform_Proc(
ape_csu_task_lookup(DMA_TAG_L2G, 1);
}
}
// printf("DataTranssss");
return ;
}

7
APELib/Receiver_sync/src/receiver_Sync_Proc.s.c
View File

@ -442,12 +442,15 @@ void Receiver_Fine_Sync_Proc(uint32_t sfn, uint32_t slot)
DMA_TAG_G2G,
1);
}
//发核间消息给SYMB_TASK
//发核间消息给SYMB_TASK, slot号为偶数APE5处理，奇数APE3处理
uint32_t symb_proc_core_sel = (0 == (slot & 0x1)) ? APE5_CORE_ID : APE3_CORE_ID;
phy_et_msg_send((uint32_t)(&data_send2symb_task[task_idx]),
sizeof(receiver_sync2symb_t),
UCP4008_KERNEL_INTER,
get_core_id(),
APE5_CORE_ID,
symb_proc_core_sel,
PHY_TASK_PRI_RECEIVER_SYNC,
PHY_TASK_PRI_RECEIVER_SYMB);
g_proc_id++;

39
Common/inc/mem_def.h
View File

@ -60,10 +60,31 @@
/************************************SM4--1.5M***********************************************/
//TODO:地址规划
#define RECEIVER_SYMB_OUT (SM4_BASE)
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000) //equ output
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#define RECEIVER_SYMB_OUT_ODD (RECEIVER_SYMB_OUT + 0x3c000)
//TODO:定义ODD地址
#ifdef CORE_ODD
// CORE_ODD 的地址
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000 + 0x8000)
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
#else
// 非CORE_ODD 的地址
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000)
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#endif
// #define RECEIVER_SYMB_OUT (SM4_BASE)
// #define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
// #define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
// #define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000) //equ output
// #define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
/************************************SM5--1.5M***********************************************/
#define RECEIVER_BASE (SM5_BASE) //4k对齐
@ -102,10 +123,16 @@
#define TRACE_RECV_INIT_ADDR (TRACE_RECEIVER_ADDR) //0x88700000
#define TRACE_SLOTIND_ADDR (TRACE_RECV_INIT_ADDR + TRACE_GRP_LEN) //0x88700200
#define TRACE_RECEIVER_SYNC_ADDR (TRACE_SLOTIND_ADDR + TRACE_GRP_LEN) // 0x88700400
#ifdef CORE_ODD
#define TRACE_RECEIVER_SYMB_ADDR (TRACE_RECEIVER_SYNC_ADDR + TRACE_GRP_LEN)// 0x88700600
#define TRACE_RECEIVER_BIT_ADDR (TRACE_RECEIVER_SYMB_ADDR + TRACE_GRP_LEN)// 0x88700800
#else
#define TRACE_RECEIVER_SYMB_ADDR (TRACE_RECEIVER_SYNC_ADDR + 2*TRACE_GRP_LEN)// 0x88700800
#endif
#define TRACE_RECEIVER_BIT_ADDR (TRACE_RECEIVER_SYNC_ADDR + 3*TRACE_GRP_LEN)// 0x88700800
#define TRACE_TESTTASK_ADDR (TRACE_RECEIVER_BIT_ADDR + TRACE_GRP_LEN) // 0x88700a00
#define TRACE_RECEIVER_SYNC_FIRST_ADDR (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700c00
#define TRACE_RECEIVER_SYNC_FIRST_ADDR (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700c00
#define TRACE_RECEIVER_SYNC_FINE_ADDR (TRACE_RECEIVER_SYNC_FIRST_ADDR + TRACE_GRP_LEN) // 0x88700e00
#define TRACE_PCIE_ADDR (TRACE_RECEIVER_SYNC_FINE_ADDR + TRACE_GRP_LEN) //0x88701000

165
Config/Receiver_Symb_cfg_dm0.dat
View File

@ -178,7 +178,7 @@
0x00000000,
0x00000000,
0x00000000,
0x00000008,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
@ -306,7 +306,7 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
@ -338,12 +338,12 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0x00020002,
0x04000400,
0x00200020,
0x00000000,
0x00000000,
0x003fffff,
@ -354,12 +354,12 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000040,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0x04000400,
0x00200020,
0x00000000,
0x00000000,
0x003fffff,
@ -370,11 +370,11 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0x00000020,
0x00000002,
0x00000000,
0x00000000,
0x00000000,
@ -383,7 +383,7 @@
0x00000000,
0x00000000,
0x00000400,
0x00000020,
0x00000001,
0x00000000,
0x00000000,
0x00000000,
@ -398,6 +398,38 @@
0x00000000,
0x00000000,
0x00000000,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x00000000,
0x00000000,
0x00000000,
@ -3166,6 +3198,115 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0x00000000,
0x00000000,
0x00ffffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x00ffffff,
0x0000000e,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x004000ce,
0x00000000,
0x00000000,

27
Makefile
View File

@ -2,8 +2,8 @@
COMMON_LIB_DIRS=Common
#PLATFORM_LIB_DIRS=Driver Rtos osp
MICRO_CODE_DIR=MicroCode
APE_DIRS=APE0 APE4 APE5 APE6 APE7
APE_ALL_DIRS=APE0 APE4 APE5 APE6 APE7 ECS
APE_DIRS=APE0 APE3 APE4 APE5 APE6 APE7
APE_ALL_DIRS=APE0 APE3 APE4 APE5 APE6 APE7 ECS
# should we remove individual microcode test module from compile
REMOVE_MC_TEST:=1
@ -68,11 +68,10 @@ endif
export REMOVE_MC_TEST_OPTION
tb:=
ifeq (${tb}, PDSCH)
#TEST_OPTION:=-DNOOSP
#TEST_OPTION+=-DNR4T
#TEST_OPTION+=-DDL_CHIP_TEST
#TEST_OPTION+=-DCLOSEDLLOG
ifeq (${tb}, SECOND)
TEST_OPTION:=
TEST_OPTION+=-DCORE_ODD
#TEST_OPTION+=-DCLOSEDLLOG
else
TEST_OPTION:=
#TEST_OPTION+=-DCLOSEDLLOG
@ -147,6 +146,18 @@ APE0:
make APP -C APE0
cp ./APE0/APE0.out ./
APE3:
rm ./MicroCode/MpuAsmInc -rf
cp ./APE3/MpuAsmInc ./MicroCode/ -rf
make UMLIBS
cp ./APELib/MicroLib/*.a ./Lib/MicroLib/
make UCLIBS
cp -rf APELib/Receiver_symb APE3
make LIB -C APE3 || exit $$?; \
cp APE3/*.a ./Lib; \
make APP -C APE3
cp ./APE3/APE3.out ./
APE4:
rm ./MicroCode/MpuAsmInc -rf
cp ./APE4/MpuAsmInc ./MicroCode/ -rf
@ -249,4 +260,4 @@ clean:
#@find . -name "*.a" -exec rm -f {} \;
.PRECIOUS: %.s.c.o %.s.asmb.o %.m.asmb.o %.m0.asmb.o %.m1.asmb.o
.PHONY: APP clean all APE0 APE4 APE5 APE6 APE7
.PHONY: APP clean all APE0 APE3 APE4 APE5 APE6 APE7

8
MicroCode/ByteSet/inc/ByteSet.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef BYTESET_H_
#define BYTESET_H_
#include "ucps2.h"
MPU_ENTRY void ByteSetAsm(v16u32 src);
void ByteSet(int ConfigAddr, int InputValue, int OutAddr, int Bytelen);
#endif /*BYTESET_H_ */

74
MicroCode/ByteSet/inc/ConfigByteSet.dat Normal file
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@ -0,0 +1,74 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//in 1
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//out 2
0x00000000,//1
0x00000000,
0x00000000,
0x00000000,
0x00000040,//1
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//1
0xffffffff,
0x00000000,
0x00000000,
0x00ffffff,//KBNumber
0x00400006,
0x00000000,//KM
0x00000000,
//3 shu
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

34
MicroCode/ByteSet/src/mpu0/ByteCSetAsm.m0.asm Normal file
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@ -0,0 +1,34 @@
.section .text.m0, "ax"
.file "ByteSetAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global ByteSetAsm
ByteSetAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0];
BIU1:Load(T0)(A++) -> M[1];
BIU1:Load(T0)(A++) -> M[2];
BIU1:Load(T0)(A++) -> M[3];
NOP;
NOP;
NOP;
NOP;
NOP;
R5:PreConfig(M[0]);
R1:M[1]->SHU1.T0 || R5:WriteConf(Mfetch)->KI[0-3];
R2:M[2]->BIU2.T1;
R1:M[3]->SHU1.T5;
NOP;
NOP;
SHU1:Index(T0,T5)->BIU2.T0;
NOP;
NOP;
BIU2:Store(T0,T1)(A++)(Mask)||MFetch:Repeat @(KI0);
MFetch:REPEAT @(5);
MFetch:MPU.STOP;

27
MicroCode/ByteSet/src/spu/ByteSet.s.c Normal file
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@ -0,0 +1,27 @@
#include <ByteSet.h>
void ByteSet(int ConfigAddr, int InputValue, int OutAddr, int Bytelen)
{
unsigned int *Para = (unsigned int *)ConfigAddr;
// for(int i=0;i<64;i++){Para[i]=0;}
Para[0] = (Bytelen+63)>>6;
Para[1*16] = InputValue;
Para[2*16] = OutAddr;
Para[2*16+12] = Bytelen;
// Para[2*16+4] = 64;
// Para[2*16+8] = 0xffffffff;
// Para[2*16+9] = 0xffffffff;
// Para[2*16+12] = 0x00ffffff;
// Para[2*16+13] = 0x00400006;
}

40
MicroCode/ByteSet/src/spu/main.s.c Normal file
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@ -0,0 +1,40 @@
#ifndef REMOVE_MC_TEST
#include "ucp2.h"
#include <ByteSet.h>
_DM3 int ConfigByteSet[] = {
#include "ConfigByteSet.dat"
};
_DM1 int OutputData[4096];
v16u32 KI = { 2,4,6};
_DM3 v16s32 SVRReg = {
0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0
};
int main(void)
{
volatile int a ;
int Bytelen = 63;
int InputValue = 24;
ByteSet((int)ConfigByteSet,InputValue,MPU_ADDR(OutputData),Bytelen);
SVRReg[0] = MPU_ADDR(ConfigByteSet);
ByteSetAsm(SVRReg);
a=__ucps2_getStatB();
__ucps2_delay();
}
#endif //DEBUG_MC

80
MicroCode/Channel_Est/src/mpu0/channelEstAsm.m0.asm
View File

@ -11,11 +11,13 @@
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0);
BIU1:Load(T0)(A++) -> M[0](Mode0)|| SHU0:VImm(0) -> SHU0.T4(Mode0);//ShiftMode0
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
BIU1:Load(T0)(A++) -> M[3](Mode0);//Output
BIU1:Load(T0)(A++) -> M[63](Mode0);//ki
BIU1:Load(T0)(A++) -> M[4](Mode0);//ShiftMode1
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//Index
NOP;
NOP;
NOP;
@ -23,31 +25,17 @@
NOP;
NOP;
NOP;
R0:M[0] -> IMA0.T0(Mode0);
R0:M[0] -> IMA1.T0(Mode0);
R3:M[1] -> BIU3.T1(Mode0);
R3:M[2] -> BIU3.T2(Mode0) || R2:M[0] -> IMA2.T0(Mode0);
NOP;
NOP;
R0:M[0] -> IMA0.T0(Mode0)||R1:M[4] -> IMA0.T1(Mode0);
R0:M[0] -> IMA1.T0(Mode0)||R1:M[4] -> IMA1.T1(Mode0);
R2:M[0] -> IMA2.T0(Mode0)||R3:M[4] -> IMA2.T1(Mode0);
R3:M[0] -> IMA3.T0(Mode0)||R2:M[4] -> IMA3.T1(Mode0);
R0:M[1] -> BIU0.T0(Mode0);
R3:M[2] -> BIU3.T0(Mode0);
R2:M[3] -> BIU2.T0(Mode0);//output1
R1:M[4] -> BIU1.T0(Mode0);//output2
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R5:PreConfig(M[63])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
@ -59,17 +47,16 @@
NOP;
NOP;
NOP;
MFetch:LPTO %Double @(KI1 - 0);
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
IMA1:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA1.MR(Mode0);
IMA2:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA2.MR(Mode0);
IMA3:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA3.MR(Mode0);
MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
BIU3:Load(T1)(A++)-> IMA0.T1(Mode0); // 向量A元素
BIU3:Load(T2)(A++)-> IMA0.T2(Mode0); // 向量B元素
BIU0:Load(T0)(A++)-> SHU0.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA0.T2(Mode0);
BIU0:Load(T0)(A++)-> SHU0.T2(Mode0)||BIU3:Load(T0)(A++)-> IMA1.T2(Mode0);
/*BIU0:Load(T0)(A++)-> IMA2.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA2.T2(Mode0);
BIU0:Load(T0)(A++)-> IMA3.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA3.T2(Mode0);*/
NOP;
NOP;
NOP;
@ -80,34 +67,29 @@ MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
NOP;
NOP;
NOP;
SHU0:Index(T4,T1,T0) -> IMA0.T1(Mode0);
SHU0:Index(T4,T2,T0) -> IMA1.T1(Mode0);
NOP;
NOP;
// 进行复数乘法
IMA0: MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
//IMA1: T2 + T3(S)(T) -> IMA1.T3(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
IMA0:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
IMA1:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA1.MR(Mode0);
/*IMA2:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA2.MR(Mode0);
IMA3:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA3.MR(Mode0);*/
ComplexMult_Loop:
IMA0: MR + 0*0(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T1(Mode0);
NOP;
NOP;
NOP;
IMA0:MR+0*0(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T1(Mode0);
IMA1:MR+0*0(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T2(Mode0);
NOP;
NOP;
NOP;
NOP;
BIU2:Store(T1,T0)(Mode0)(A++);
BIU2:Store(T2,T0)(Mode0)(A++);
NOP;
NOP;
NOP;
Double:
MFetch:Repeat @(10);
MFetch:MPU.STOP;

15
MicroCode/Fre_comp/src/mpu0/cordicSCAsm.m0.asm
View File

@ -45,7 +45,6 @@ cordicSCAsm:
MFetch: Lpto %ENDCORDIC @(KI1);
IMA0: T3 + T4(W)(U)(T) -> IMA1.T0;NOP;NOP;
// IMA1: T0 + T0(W)(U)(T) -> IMA1.T0;NOP;
IMA1: T0 -> IMA0.T3; NOP;
IMA1: T0 + T3(W)(U)(T) -> IMA1.T4;NOP;
@ -80,18 +79,26 @@ cordicSCAsm:
END_ITERATIONS_16:
IMA3: 0 - T0(W) -> IMA3.T0;
IMA0: T3 -> BIU0.T2;
IMA3: CPRS(T0)(CprsMode1) -> IMA2.T0;
IMA3: CPRS(T1)(CprsMode1) -> IMA2.T1;
NOP;NOP;
IMA2: T0 << 16(W)(U) -> IMA2.T0 || IMA3: V(0) -> IMA3.T0;
BIU0: Store(T2,T0);
IMA2: T0 + T1(W) -> BIU2.T0 || IMA3: V(1024) -> IMA3.T1;
NOP;NOP;
IMA3: VHigh(T1,0) -> IMA3.T1;
BIU2: Store(T0,T1)(A++);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
BIU2: Store(T0,T1)(A++); MFetch: REPEAT @(4);
ENDCORDIC:

31
MicroCode/Fre_comp/src/mpu0/freOffCompAsm.m0.asm
View File

@ -14,7 +14,7 @@ freOffCompAsm:
BIU1: Load(T0)(A++) -> M[2]; // fre_offfset_est
BIU1: Load(T0)(A++) -> M[3]; // outputAddr
IMA0: V(512) -> IMA0.T0(Mode0);NOP;
IMA0: V(517) -> IMA0.T0(Mode0);NOP;
IMA0: VHigh(T0,0) -> IMA0.T0(Mode0);NOP;
IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0);NOP;
@ -25,33 +25,16 @@ freOffCompAsm:
R5: M[2] -> BIU1.T1(Mode0);
R3: M[3] -> BIU3.T3(Mode0);
NOP;NOP;NOP;
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
MFetch: REPEAT @(10);
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 10 || IMA1: Wait 10 || BIU3: Wait 15;
MFetch: Lpto %ENDFRECOMP @(KI0);
IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS) -> IMA0.MR;
MFetch: REPEAT @(15);
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
BIU0: Load(T0)(A++) -> IMA0.T3(Mode0) || BIU1: Load(T1)(A++) -> IMA0.T2(Mode0) || IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS)(T) -> BIU3.T1(Mode0) || BIU3: Store(T1,T3)(A++)(Mode0);
IMA0: ReadMR(L) -> IMA1.T0; // real
IMA0: ReadMR(H) -> IMA2.T0; // imag
MFetch: REPEAT @(4);
IMA1: T0 >> 10(W) -> IMA0.T1 || IMA2: T0 >> 10(W) -> IMA2.T1;
MFetch: REPEAT @(2);
IMA0: CPRS(T1)(CprsMode1) -> IMA2.T2 || IMA2: CPRS(T1)(CprsMode1) -> IMA2.T3;
MFetch: REPEAT @(4);
IMA2: T3 << 16(W)(U) -> IMA2.T3;
NOP;NOP;
IMA2: T2 + T3(W) -> BIU3.T1;
NOP;NOP;
BIU3: Store(T1,T3)(A++);
ENDFRECOMP:
MFetch: REPEAT @(10);
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || BIU3: Wait 0;
MFetch: REPEAT @(15);
MFetch:MPU.STOP;

2
MicroCode/Fre_comp/src/spu/freOffComp.s.c
View File

@ -7,7 +7,7 @@ void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int OutputAddr
int *Para = ConfigBaseAddr;
Para[16*0+0] = 480;
Para[16*0+0] = 960;
//input Signal
Para[16*1+0] = InputAddr0;
Para[16*1+1] = InputAddr0;

2
compile.sh
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@ -1,3 +1,3 @@
set -x
make clean && make APE0 && make APE4 && make APE5 && make APE6 && make APE7
make clean && make APE0 && make APE3 tb=SECOND && make APE4 && make APE5 && make APE6 && make APE7