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1.byteCopy正常版本 2.添加CLOSE_APE3，方便Recv_symb调试，默认关闭 3.合入25_05_29为止的recv_symb的修改

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HUOHUO 2025-05-29 09:52:16 -07:00
parent afb5f87459
commit b3e0f33d1b
34 changed files with 8668 additions and 306275 deletions
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2
APE3/Makefile
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@ -1,6 +1,6 @@
############################ ############################
# mpu libs need to link to this APE, could be specified by user # mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp AgcShiftMultiSym
############################ ############################
# tool path, could be specified by user # tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin #UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

2
APE5/Makefile
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@ -1,6 +1,6 @@
############################ ############################
# mpu libs need to link to this APE, could be specified by user # mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp AgcShiftMultiSym
############################ ############################
# tool path, could be specified by user # tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin #UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

2
APELib/Receiver_symb/inc/channelEquImpl.h
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@ -23,6 +23,7 @@ void ChannelEquImpl(
int *ConfigAddCp, int *ConfigAddCp,
int *CfgByteCopy, int *CfgByteCopy,
int *CfgAgcShift, int *CfgAgcShift,
int *CfgAgcMultiSym,
int *available_ptr_dm0, int *available_ptr_dm0,
int *available_ptr_dm1, int *available_ptr_dm1,
int *available_ptr_dm2, int *available_ptr_dm2,
@ -37,6 +38,7 @@ void ChannelEquImpl(
int *CalAddr2, int *CalAddr2,
int *Lut_phase, int *Lut_phase,
int *AgcFactor, int *AgcFactor,
int *Lut_agcMultiSymFactor,
int res_ptr int res_ptr
); );

2
APELib/Receiver_symb/inc/receiver_symb_func.h
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@ -27,7 +27,7 @@
#include "Transform.h" #include "Transform.h"
#include "interface_rec_symb2_rec_bit.h" #include "interface_rec_symb2_rec_bit.h"
//include mpu header files //include mpu header files
#include "ByteCopy.h"

7
APELib/Receiver_symb/inc/receiver_symb_macro.h
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@ -37,11 +37,12 @@
#define RECEIVER_SYMB_ByteSet_CFG10_LENGTH (0x0040) #define RECEIVER_SYMB_ByteSet_CFG10_LENGTH (0x0040)
#define RECEIVER_SYMB_ByteCopy_CFG10_LENGTH (0x0030) #define RECEIVER_SYMB_ByteCopy_CFG10_LENGTH (0x0030)
#define RECEIVER_SYMB_FREOFF_CFG_LENGTH (RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH ) #define RECEIVER_SYMB_FREOFF_CFG_LENGTH (RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH )//0x140
#define RECEIVER_SYMB_CHANNELEST_CFG_LENGTH (RECEIVER_SYMB_ChannelEst_CFG4_LENGTH) #define RECEIVER_SYMB_CHANNELEST_CFG_LENGTH (RECEIVER_SYMB_ChannelEst_CFG4_LENGTH)//0x70
#define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH ) #define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH )
//A60
#define RECEIVER_SYMB_DeTransformer_CFG_LENGTH (RECEIVER_SYMB_DeTransform2_CFG8_LENGTH + RECEIVER_SYMB_DeTransform4_CFG9_LENGTH + RECEIVER_SYMB_Transform8_CFG10_LENGTH) #define RECEIVER_SYMB_DeTransformer_CFG_LENGTH (RECEIVER_SYMB_DeTransform2_CFG8_LENGTH + RECEIVER_SYMB_DeTransform4_CFG9_LENGTH + RECEIVER_SYMB_Transform8_CFG10_LENGTH)
//1A0
#define RECEIVER_SYMB_COMMEN_CFG_LENGTH (RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH + RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH + RECEIVER_SYMB_DeTransformer_CFG_LENGTH) #define RECEIVER_SYMB_COMMEN_CFG_LENGTH (RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH + RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH + RECEIVER_SYMB_DeTransformer_CFG_LENGTH)

45
APELib/Receiver_symb/src/channelEquImpl.s.c
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@ -3,6 +3,8 @@
#include "ucpm2.h" #include "ucpm2.h"
#include <channelEquImpl.h> #include <channelEquImpl.h>
#include "trace.h" #include "trace.h"
#include "AgcShiftMultiSym.h"
#include "log_interface.h"
#ifdef IDE_TEST #ifdef IDE_TEST
@ -18,6 +20,7 @@ void ChannelEquImpl(
int *ConfigAddCp, int *ConfigAddCp,
int *CfgByteCopy, int *CfgByteCopy,
int *CfgAgcShift, int *CfgAgcShift,
int *CfgAgcMultiSym,
int *available_ptr_dm0, int *available_ptr_dm0,
int *available_ptr_dm1, int *available_ptr_dm1,
int *available_ptr_dm2, int *available_ptr_dm2,
@ -32,6 +35,7 @@ void ChannelEquImpl(
int *CalAddr2, int *CalAddr2,
int *Lut_phase, int *Lut_phase,
int *AgcFactor, int *AgcFactor,
int *Lut_agcMultiSymFactor,
int res_ptr int res_ptr
){ ){
@ -43,8 +47,16 @@ void ChannelEquImpl(
int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0}; int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
int NumCB = 2; int NumCB = 2;
int16_t baseScale = 2;
for(int ii=0;ii<16;ii++){
AgcFactor[ii] = 3;
}
for(int i=0;i<NumCB;i++){ for(int i=0;i<NumCB;i++){
int16_t pre_scale = 0;
int *Scalep = available_ptr_dm0; int *Scalep = available_ptr_dm0;
int *Scale0 = available_ptr_dm0 + 0x0040; int *Scale0 = available_ptr_dm0 + 0x0040;
int *Scales = available_ptr_dm0 + 0x0080; int *Scales = available_ptr_dm0 + 0x0080;
@ -55,8 +67,6 @@ void ChannelEquImpl(
/*****************************************FFT of channelEst*****************************************/ /*****************************************FFT of channelEst*****************************************/
ape_csu_task_lookup(DMA_TAG_G2L, 1); ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer( ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)(InChannelEst_ddr_ptr + 4096*i) , (uint64_t)(InChannelEst_ddr_ptr + 4096*i) ,
@ -81,8 +91,6 @@ void ChannelEquImpl(
AgcShiftForFftInt32Asm(SVRReg); AgcShiftForFftInt32Asm(SVRReg);
WAIT_MPU_STOP; WAIT_MPU_STOP;
Fft4096Int32( Fft4096Int32(
(int)CfgFft4096, (int)CfgFft4096,
1, 1,
@ -101,12 +109,14 @@ void ChannelEquImpl(
WAIT_MPU_STOP; WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer( /*ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr), (uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
(uint64_t)0x84c00000, (uint64_t)0x84c00000,
4096*4 , 4096*4 ,
DMA_TAG_L2G, DMA_TAG_L2G,
1); 1);
*/
//构造第二根天线 //构造第二根天线
ByteCopy((int)CfgByteCopy, MPU_ADDR(channelEst_dm0_ptr),MPU_ADDR(Fft_est_dm3_ptr + 4096),16384); ByteCopy((int)CfgByteCopy, MPU_ADDR(channelEst_dm0_ptr),MPU_ADDR(Fft_est_dm3_ptr + 4096),16384);
@ -130,8 +140,8 @@ void ChannelEquImpl(
DMA_TAG_G2L, DMA_TAG_G2L,
1); 1);
WAIT_MPU_STOP; WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
for(int j=0;j<numSym;j++){ for(int j=0;j<numSym;j++){
AgcShiftForFftInt32( AgcShiftForFftInt32(
@ -174,13 +184,23 @@ void ChannelEquImpl(
Fft4096Int32Asm(SVRReg); Fft4096Int32Asm(SVRReg);
WAIT_MPU_STOP; WAIT_MPU_STOP;
/* -------------- 拉齐信道估计FFT ------------*/
int16_t shiftScale = Scalep[0] & (0xFFFF) - baseScale;
if(shiftScale!=pre_scale){
Lut_agcMultiSymFactor[0] = shiftScale - pre_scale;
pre_scale = (int16_t)Lut_agcMultiSymFactor[0] + pre_scale;
ape_csu_dma_1D_L2G_ch0ch1_transfer( //tmp0暂存移位后FFT结果
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr), AgcShiftMultiSym((int)CfgAgcMultiSym, MPU_ADDR(Fft_est_dm3_ptr), 8192,1, MPU_ADDR(tmp0),MPU_ADDR(Lut_agcMultiSymFactor));
(uint64_t)0x84d00000, SVRReg[0] = MPU_ADDR(CfgAgcMultiSym);
4096*4 , AgcShiftMultiSymAsm(SVRReg);
DMA_TAG_L2G, WAIT_MPU_STOP;
1);
ByteCopy((int)CfgByteCopy, MPU_ADDR(tmp0),MPU_ADDR(Fft_est_dm3_ptr),16384*2);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
WAIT_MPU_STOP;
}
// 构造第二根天线数据，与第一根相同 // 构造第二根天线数据，与第一根相同
@ -298,6 +318,7 @@ void ChannelEquImpl(
SVRReg[0] = MPU_ADDR(ConfigAddCp); SVRReg[0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(SVRReg); AddCPAsm(SVRReg);
WAIT_MPU_STOP; WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2)); TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1)); TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2)); TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));

9
APELib/Receiver_symb/src/channelEqu_proc.s.c
View File

@ -46,7 +46,10 @@ void ChannelEqu_Proc(
uint32_t *CfgAgcShift = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH; uint32_t *CfgAgcShift = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH;
uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH; uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH;
uint32_t *CfgByteCopy= receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH; uint32_t *CfgByteCopy = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH;
uint32_t *CfgAgcMultiSym = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH + RECEIVER_SYMB_ByteCopy_CFG10_LENGTH;
// LUT // LUT
uint32_t *Lut_W4096 = lut_addr; uint32_t *Lut_W4096 = lut_addr;
uint32_t *Lut_EqFactor0 = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH; uint32_t *Lut_EqFactor0 = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH;
@ -55,12 +58,13 @@ void ChannelEqu_Proc(
uint32_t *Lut_Zero = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH; //useless uint32_t *Lut_Zero = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH; //useless
uint32_t *Lut_phase = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH ; uint32_t *Lut_phase = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH ;
uint32_t *Lut_agcFactor = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH + RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH; uint32_t *Lut_agcFactor = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH + RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH;
uint32_t *Lut_agcMultiSymFactor = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH + RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH + RECEIVER_SYMB_AgcShiftFft_LUT7_LENGTH;
// channelEst and data // channelEst and data
uint32_t *InputCHEst_ddr_ptr = (uint32_t *)CHANNELEST_DATA_DDR_PTR; uint32_t *InputCHEst_ddr_ptr = (uint32_t *)CHANNELEST_DATA_DDR_PTR;
uint32_t *InputData_ddr_ptr = (uint32_t *)(COMPENSATED_DATA_DDR_PTR + 2048*4); //去除导频 uint32_t *InputData_ddr_ptr = (uint32_t *)(COMPENSATED_DATA_DDR_PTR + 2048*4); //去除导频
ChannelEquImpl(CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,CfgByteCopy,CfgAgcShift, ChannelEquImpl(CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,CfgByteCopy,CfgAgcShift,CfgAgcMultiSym,
available_ptr_dm0, available_ptr_dm0,
available_ptr_dm1, available_ptr_dm1,
available_ptr_dm2 , available_ptr_dm2 ,
@ -75,6 +79,7 @@ void ChannelEqu_Proc(
Lut_EqFactor, Lut_EqFactor,
Lut_phase, Lut_phase,
Lut_agcFactor, Lut_agcFactor,
Lut_agcMultiSymFactor,
res_ptr res_ptr
); );

12
APELib/Receiver_symb/src/channelEst_Proc.s.c
View File

@ -54,9 +54,11 @@ void ChannelEst_Proc(
// 新增了Pilot正变换 // 新增了Pilot正变换
double thita[6]; //double thita[6];
double *db_imag = proc_info->transform_para_real; // double *db_imag = proc_info->transform_para_real;
double *db_real = proc_info->transform_para_imag; // double *db_real = proc_info->transform_para_imag;
double db_real[4] = {-0.3827, 0.8660, -0.7071, 0.5};
double db_imag[4] = {0.9239, 0.5, -0.7071, 0.8660};
uint32_t *PilotTrans = temp_dm3_ptr; uint32_t *PilotTrans = temp_dm3_ptr;
Transform((int)cfg_transform8,MPU_ADDR(Pilot_orig_LUT),MPU_ADDR(PilotTrans), 8, db_real, db_imag, 1); Transform((int)cfg_transform8,MPU_ADDR(Pilot_orig_LUT),MPU_ADDR(PilotTrans), 8, db_real, db_imag, 1);
@ -64,9 +66,9 @@ void ChannelEst_Proc(
Transform8Asm(SVRReg); Transform8Asm(SVRReg);
WAIT_MPU_STOP; WAIT_MPU_STOP;
// TODO 此处应使用PilotTrans替换Pilot_orig_LUT // TODO 暂用Pilot_orig_LUT， 此处应使用PilotTrans替换Pilot_orig_LUT 20250529
ChannelEstImpl(ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr + subIndex*4096); ChannelEstImpl(ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr + subIndex*4096);
WAIT_MPU_STOP; //WAIT_MPU_STOP;
} }

52
APELib/Receiver_symb/src/freoff_Proc.s.c
View File

@ -1,6 +1,7 @@
#include "receiver_symb_func.h" #include "receiver_symb_func.h"
#include "ape_common.h" #include "ape_common.h"
#include "log_interface.h"
void FreOff_Proc( void FreOff_Proc(
@ -34,21 +35,28 @@ void FreOff_Proc(
uint32_t *ConfigAddr_est = receiver_symb_config_dm0_ptr; uint32_t *ConfigAddr_est = receiver_symb_config_dm0_ptr;
uint32_t *ConfigAddr_comp = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH; uint32_t *ConfigAddr_comp = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH;
uint32_t *ConfigAddr_cordic = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH; uint32_t *ConfigAddr_cordic = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH;
uint32_t *CfgByteCopy= receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH;
// Get CP and Pilot // Get CP and Pilot
uint32_t *InputCPAddr = (uint32_t *)time_data_dm3_ptr; uint32_t *InputCPAddr = (uint32_t *)time_data_dm3_ptr;
uint32_t *InputPilotAddr = InputCPAddr + 1024; uint32_t *InputPilotAddr = temp_dm2_ptr;
//uint32_t *InputPilotAddr = InputCPAddr + 1024;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 15, *InputCPAddr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 16, *InputPilotAddr);
uint32_t *freEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0020); uint32_t *freEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0020);
time0 = Time_offset(0);
//20250509
ByteCopy((int)CfgByteCopy, MPU_ADDR(InputCPAddr + 1024),MPU_ADDR(InputPilotAddr),1024*4);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
WAIT_MPU_STOP;
time0 = Time_offset(0);
//20250509
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)receiver_symb_config_dm0_ptr), ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)receiver_symb_config_dm0_ptr),
(uint64_t)0x84c00000, (uint64_t)0x84c00000,
144*4, 144*4,
@ -62,6 +70,10 @@ void FreOff_Proc(
time1 = Time_offset(0); time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 9, time1-time0); TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 9, time1-time0);
time0 = time1; time0 = time1;
// Low-pass Filter // Low-pass Filter
if(storedfreoffestvalue > 600000){ if(storedfreoffestvalue > 600000){
storedfreoffestvalue = freEstOutAddr[0]; storedfreoffestvalue = freEstOutAddr[0];
@ -69,15 +81,10 @@ void FreOff_Proc(
else{ else{
storedfreoffestvalue = 0.7*storedfreoffestvalue + 0.3*freEstOutAddr[0]; storedfreoffestvalue = 0.7*storedfreoffestvalue + 0.3*freEstOutAddr[0];
} }
TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, freEstOutAddr[0]); TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, freEstOutAddr[0]);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, 0xa0870); TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, 0xa0870);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, freEstOutAddr[1]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, freEstOutAddr[2]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, freEstOutAddr[3]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, freEstOutAddr[4]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, freEstOutAddr[5]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, freEstOutAddr[6]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 23, freEstOutAddr[7]);
freEstOutAddr[0] = storedfreoffestvalue; freEstOutAddr[0] = storedfreoffestvalue;
// Frequency Offset Compensate // Frequency Offset Compensate
@ -98,16 +105,3 @@ void FreOff_Proc(
} }
// //计算结果搬移到SM
//
// temp_u32 = (uint32_t)(((time_data_length +7)>>3)<<3);//计算byte数
// WAIT_MPU_STOP;
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
// (uint64_t)res_ptr,
// temp_u32,
// DMA_TAG_L2G,
// 1);
//
// return;
//}

15
APELib/Receiver_symb/src/receiver_Symb_Proc.s.c
View File

@ -24,6 +24,7 @@ void Receiver_Symb_Proc(
int32_t *temp_dm3_ptr int32_t *temp_dm3_ptr
) )
{ {
//局部变量定义 //局部变量定义
int32_t *cfg_addr; int32_t *cfg_addr;
uint32_t time_data_length; uint32_t time_data_length;
@ -35,6 +36,7 @@ void Receiver_Symb_Proc(
uint32_t time_data_dm0_ptr = ((((uint32_t)&temp_dm0_ptr[0] + 4095)>>12)<<12); uint32_t time_data_dm0_ptr = ((((uint32_t)&temp_dm0_ptr[0] + 4095)>>12)<<12);
uint32_t time0, time1; uint32_t time0, time1;
//data读入 //data读入
//获取源数据地址 //获取源数据地址
receiver_sync2symb_t* para_dm_ptr = param_ptr; receiver_sync2symb_t* para_dm_ptr = param_ptr;
@ -84,18 +86,19 @@ void Receiver_Symb_Proc(
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 5, time1 -time0); TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 5, time1 -time0);
time0 = time1; time0 = time1;
ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr,temp_dm2_ptr,temp_dm3_ptr);
// ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr,temp_dm2_ptr,temp_dm3_ptr); TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 4);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 4); time1 = Time_offset(0);
// time1 = Time_offset(0); TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 6, time1 -time0);
// TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 6, time1 -time0); time0 = time1;
// time0 = time1;
ChannelEqu_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr); ChannelEqu_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 5); TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 5);
time1 = Time_offset(0); time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 7, time1 -time0); TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 7, time1 -time0);
time0 = time1; time0 = time1;
// __ucps2_synch(0); // __ucps2_synch(0);
// __ucps2_synch(0); // __ucps2_synch(0);
// __ucps2_synch(0); // __ucps2_synch(0);

7
APELib/Receiver_symb/src/receiver_Symb_Task.s.c
View File

@ -22,6 +22,13 @@
*/ */
void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len) void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
{ {
#ifdef CLOSE_APE3
//先调一个核
uint32_t core_id = get_core_id();
if(3 == core_id)
return ;
#endif
uint16_t start_slot = TIME_SLOT(); uint16_t start_slot = TIME_SLOT();
g_time_start[0] = TIME_NS(); g_time_start[0] = TIME_NS();
RUN_CNT(TRACE_RECEIVER_SYMB_ADDR, 0); RUN_CNT(TRACE_RECEIVER_SYMB_ADDR, 0);

12
APELib/Receiver_symb/src/transform_Proc.s.c
View File

@ -27,11 +27,15 @@ void Transform_Proc(
volatile int a; volatile int a;
/*****************************************initial*****************************************/ /*****************************************initial*****************************************/
double thita[6]; double thita[6];
double *db_imag = proc_info->transform_para_real; // double *db_imag = proc_info->transform_para_real;
double *db_real = proc_info->transform_para_imag; // double *db_real = proc_info->transform_para_imag;
double db_real[4] = {-0.3827, 0.8660, -0.7071, 0.5};
double db_imag[4] = {0.9239, 0.5, -0.7071, 0.8660};
for(int iBlk = 0;iBlk < 7;iBlk++){ for(int iBlk = 0;iBlk < 7;iBlk++){
ape_csu_task_lookup(DMA_TAG_G2L, 1); ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer( ape_csu_dma_1D_G2L_ch2ch3_transfer(
@ -76,8 +80,8 @@ void Transform_Proc(
uint32_t loop_idx; uint32_t loop_idx;
for (loop_idx = 0; loop_idx < 4; loop_idx++) for (loop_idx = 0; loop_idx < 4; loop_idx++)
{ {
db_real_tmp[loop_idx] = *(db_real + loop_idx) * 1.375; db_real_tmp[loop_idx] = *(db_real + loop_idx) * 1.42;
db_imag_tmp[loop_idx] = *(db_imag + loop_idx) * 1.375; db_imag_tmp[loop_idx] = *(db_imag + loop_idx) * 1.42;
} }
Transform((int)Cfg_DeTransform2,MPU_ADDR(InputAddr_Trans),MPU_ADDR(TransTemp), 2, &db_real_tmp[0], &db_imag_tmp[0], -1); Transform((int)Cfg_DeTransform2,MPU_ADDR(InputAddr_Trans),MPU_ADDR(TransTemp), 2, &db_real_tmp[0], &db_imag_tmp[0], -1);
SVRReg[0] = MPU_ADDR(Cfg_DeTransform2); SVRReg[0] = MPU_ADDR(Cfg_DeTransform2);

8
Common/inc/test_macro.h
View File

@ -8,20 +8,22 @@
//#define RECV_SYMB_DBG_DATA_TEST //#define RECV_SYMB_DBG_DATA_TEST
/*RX数据输入直接从TX Buffer读入，数据环回开关*/ /*RX数据输入直接从TX Buffer读入，数据环回开关*/
//#define TX_RX_LOOP #define TX_RX_LOOP
/*Transmit加载Trans.dat作为输入数据*/ /*Transmit加载Trans.dat作为输入数据*/
//#define TRANS_DBG_DATA_TEST #define TRANS_DBG_DATA_TEST
/*二选一或者都不打开,都不打开数据源是ARM，否则需要配合TRANS_DBG_DATA_TEST打开使用*/ /*二选一或者都不打开,都不打开数据源是ARM，否则需要配合TRANS_DBG_DATA_TEST打开使用*/
/*Transmit m序列自行递推，*/ /*Transmit m序列自行递推，*/
//#define TRANS_SRC_AUTO_GEN //#define TRANS_SRC_AUTO_GEN
/*Transmit m序列固定为起始值*/ /*Transmit m序列固定为起始值*/
//#define TRANS_SRC_AUTO_GEN_DBG #define TRANS_SRC_AUTO_GEN_DBG
/*状态机跳过RK3588计算*/ /*状态机跳过RK3588计算*/
#define CLOSE_AI_PROCECING #define CLOSE_AI_PROCECING
/*核3暂时不工作，方便直接绝对地址打点*/
// #define CLOSE_APE3
#endif /*_TEST_MACRO_H_*/ #endif /*_TEST_MACRO_H_*/

62464
Config/Receiver_Sync_test.dat
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File diff suppressed because it is too large Load Diff

61440
Config/even.dat
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File diff suppressed because it is too large Load Diff

61440
Config/frame_0x610e0000_245760.dat
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File diff suppressed because it is too large Load Diff

2048
Config/odd.dat
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File diff suppressed because it is too large Load Diff

57344
Config/timedata.dat
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File diff suppressed because it is too large Load Diff

61440
Config/timedatasym.dat
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File diff suppressed because it is too large Load Diff

32
MicroCode/AgcShiftMultiSym/inc/AgcFactor.dat Normal file
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@ -0,0 +1,32 @@
0x00000004,
0x00000008,
0xfffffff7,
0x00000007,
0xffffffff,
0x00000002,
0xfffffffe,
0x00000006,
0x00000001,
0x00000002,
0x00000006,
0x00000005,
0x00000008,
0x00000002,
0x00000001,
0x00000003,
0x00000001,
0x00000007,
0x00000005,
0x00000007,
0x00000008,
0x00000009,
0x00000000,
0xffffffff,
0x00000002,
0x00000001,
0x00000000,
0x00000001,
0x00000002,
0x00000006,
0x00000005,
0x00000008,

7
MicroCode/AgcShiftMultiSym/inc/AgcShiftMultiSym.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef AgcShiftMultiSym_H_
#define AgcShiftMultiSym_H_
#include "ucps2.h"
MPU_ENTRY void AgcShiftMultiSymAsm(v16u32 src);
void AgcShiftMultiSym(int ConfigAddr, int InAddr,int ReNum,int Symbol_Ante_Num, int OutAddr,int AgcAddr);
#endif

127
MicroCode/AgcShiftMultiSym/inc/ConfigAgcShiftMultiSym.dat Normal file
View File

@ -0,0 +1,127 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//1
0x00000000,//1
0x00000000,
0x00000000,
0x00000000,
0x00000004,//1
0x00000000,
0x00000000,
0x00000000,
0xffffffff,//1
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,//KBNumber
0x00400306,
0x00000000,//KM
0x00000000,
//2 INPUT
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00000006,
0x00000000,
0x00000000,
//3 output
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00400006,
0x00000000,
0x00000000,
//4 agcfactor 16
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//5 agcfactor 32
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//6 agcfactor 48
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

8193
MicroCode/AgcShiftMultiSym/inc/TestAgcInput.dat Normal file
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File diff suppressed because it is too large Load Diff

37
MicroCode/AgcShiftMultiSym/src/mpu0/AgcShiftMultiSymAsm.m0.asm Normal file
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@ -0,0 +1,37 @@
.section .text.m0, "ax"
.file "AgcShiftMultiSymAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global AgcShiftMultiSymAsm
AgcShiftMultiSymAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0];
BIU1:Load(T0)(A++) -> BIU1.T1;
BIU1:Load(T0)(A++) -> M[2];
BIU1:Load(T0)(A++) -> M[3];
BIU1:Load(T0)(A++) -> M[4];
BIU1:Load(T0)(A++) -> M[5];
NOP;
NOP;
NOP;
R5:PreConfig(M[0]);
R5:WriteConf(Mfetch)->KI[0-3];
R0:M[2] -> BIU0.T2;
R2:M[3] -> BIU2.T1;
NOP;
NOP;
NOP;
NOP;
NOP;
MFetch:LPTO %Symbol @(KI0);
BIU1:Load(T1)(A++) -> IMA2.T4;
BIU0:Wait 0 || IMA2: Wait 10 || BIU2:Wait 13 ;
BIU0:Load(T2)(A++) -> IMA2.T0 || IMA2: T0 << T4(S) -> BIU2.T0 || BIU2:Store(T0,T1)(A++)(Mask) || MFetch:REPEAT @(KI1);
Symbol:
MFetch:Repeat @(20);
MFetch:MPU.STOP;

25
MicroCode/AgcShiftMultiSym/src/spu/AgcShiftMultiSym.s.c Normal file
View File

@ -0,0 +1,25 @@
void AgcShiftMultiSym(int ConfigAddr, int InAddr,int ReNum,int Symbol_Ante_Num, int OutAddr,int AgcAddr)
{
unsigned int *Para = (unsigned int *)ConfigAddr;
int temp0 = (ReNum+15)>>4;
int i;
Para[0] = Symbol_Ante_Num;
Para[1] = temp0;
Para[1*16] = AgcAddr;
Para[2*16] = InAddr;
Para[2*16+1] = InAddr;
Para[2*16+5] = ReNum << 2;
Para[2*16+8] = (temp0<<16)+temp0;
Para[3*16] = OutAddr;
Para[3*16+1] = OutAddr;
Para[3*16+5] = ReNum << 2;
Para[3*16+8] = (temp0<<16)+temp0;
Para[3*16+12] = ((temp0*(Symbol_Ante_Num-1) << 4)+ReNum) << 2;
}

47
MicroCode/AgcShiftMultiSym/src/spu/main.s.c Normal file
View File

@ -0,0 +1,47 @@
#ifndef REMOVE_MC_TEST
#include "ucps2.h"
#include "ucpm2.h"
#include <AgcShiftMultiSym.h>
__DM3 int ConfigAgcShiftMultiSym[] = {
#include <ConfigAgcShiftMultiSym.dat>
};
__DM1 int AgcFactorAddr[] = {
#include <AgcFactor.dat>
};
__DM0 int InputData[] = {
#include "TestAgcInput.dat"
};;
__DM2 int OutputData[5000];
v16u32 KI = { 2,4,6};
__DM3 v16s32 SVRReg = {
0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0
};
int main(void)
{
volatile int a ;
int ReNum = 48;
int Symbol_Ante_Num =32;
// int AgcFactor[48]={4,8,-9,7,-1,2,-2,6,1,2,6,5,8,2,1,3,1,7,5,7,8,9,0,-1,2,1,0,1,2,6,5,8,2,0,0,-9,7,-1,2,0,0,0,0,1,2,6,5,8};
AgcShiftMultiSym((int)ConfigAgcShiftMultiSym, MPU_ADDR(InputData), ReNum,Symbol_Ante_Num, MPU_ADDR(OutputData),MPU_ADDR(AgcFactorAddr));
SVRReg[0] = MPU_ADDR(ConfigAgcShiftMultiSym);
AgcShiftMultiSymAsm(SVRReg);
a=__ucps2_getStatB();
__ucps2_delay();
return a;
}
#endif //DEBUG_MC

6
MicroCode/Channel_Equ/src/spu/AgcShiftForFftInt32.s.c
View File

@ -5,12 +5,6 @@
void AgcShiftForFftInt32(int ConfigAddr,int InAddr_1,int InAddr_2,int ReNum,int nSyms, void AgcShiftForFftInt32(int ConfigAddr,int InAddr_1,int InAddr_2,int ReNum,int nSyms,
int AgcAddr_1,int AgcAddr_2,int OutAddr_1,int OutAddr_2) int AgcAddr_1,int AgcAddr_2,int OutAddr_1,int OutAddr_2)
{ {
//TODO:待确认修改方式是否正确 20250528
int ii;
int* AgcAddr_1_ptr = (int*)AgcAddr_1;
for(ii=0;ii<16;ii++){
AgcAddr_1_ptr[ii] = 1;
}
int *Para = (int *)ConfigAddr; int *Para = (int *)ConfigAddr;
int temp0 = (ReNum+15)>>4; int temp0 = (ReNum+15)>>4;
int i; int i;

4
MicroCode/Fre_comp/inc/freOffComp.h
View File

@ -1,11 +1,11 @@
#if 1
#ifndef FREOFFCOMP_H_ #ifndef FREOFFCOMP_H_
#define FREOFFCOMP_H_ #define FREOFFCOMP_H_
#include "ucps2.h" #include "ucps2.h"
#include "ucpm2.h" #include "ucpm2.h"
MPU_ENTRY void freOffCompAsm(v16u32 src); MPU_ENTRY void freOffCompAsm(v16u32 src);
MPU_ENTRY void freOffCompAsm1(v16u32 src);
void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1, int OutputAddr0); void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1, int OutputAddr0);
#endif
#endif /* FREQOFFSETEST_H_ */ #endif /* FREQOFFSETEST_H_ */

19
MicroCode/Fre_comp/src/mpu0/cordicSCAsm.m0.asm
View File

@ -28,7 +28,7 @@ cordicSCAsm:
R1: M[4] -> SHU0.T7(Mode0); R1: M[4] -> SHU0.T7(Mode0);
R2: M[6] -> BIU2.T1(Mode0); R2: M[6] -> BIU2.T1(Mode0);
R5: M[20] -> IMA0.T4(Mode0); R5: M[20] -> IMA0.T4(Mode0);
MFetch: REPEAT @(10);
IMA1: V(0) -> IMA1.T0 || IMA2: V(0) -> IMA2.T0; IMA1: V(0) -> IMA1.T0 || IMA2: V(0) -> IMA2.T0;
IMA3: V(0) -> IMA3.T0; // y0 IMA3: V(0) -> IMA3.T0; // y0
IMA1: VHigh(T0,0x8000) -> IMA1.T3 || IMA2: VHigh(T0,0x4000) -> IMA1.T1; IMA1: VHigh(T0,0x8000) -> IMA1.T3 || IMA2: VHigh(T0,0x4000) -> IMA1.T1;
@ -40,28 +40,31 @@ cordicSCAsm:
BIU0: Load(T0) -> IMA1.T0; BIU0: Load(T0) -> IMA1.T0;
MFetch: REPEAT @(10); MFetch: REPEAT @(10);
IMA1: T0 -> IMA0.T3; IMA1: T0 -> IMA0.T3;NOP;
NOP; NOP;
NOP; NOP;
MFetch: REPEAT @(4); MFetch: REPEAT @(10);
MFetch: Lpto %ENDCORDIC @(KI1); MFetch: Lpto %ENDCORDIC @(KI1);
IMA0: T3 + T4(W)(U)(T) -> IMA1.T0; IMA0: T3 + T4(W)(U)(T) -> IMA1.T0;
NOP; NOP;
NOP; NOP;
IMA1: T0 -> IMA0.T3; NOP; IMA1: T0 -> IMA0.T3; NOP;
IMA1: T0 + T3(W)(U)(T) -> IMA1.T4;NOP; IMA1: T0 + T3(W)(U)(T) -> IMA1.T4;NOP;
IMA1: T0 - T3(W)(U)(T) -> IMA1.T5;NOP; IMA1: T0 - T3(W)(U)(T) -> IMA1.T5;NOP;
IMA1: CompSel(T0,T1,T5,T0)(W) -> IMA1.T0;NOP; IMA1: CompSel(T0,T1,T5,T0)(W) -> IMA1.T0;
IMA1: CompSel(T0,T2,T0,T4)(W) -> IMA1.T0;NOP; NOP;
IMA1: CompSel(T0,T2,T0,T4)(W) -> IMA1.T0;
NOP;
IMA1: T0 -> IMA0.T1; IMA1: T0 -> IMA0.T1;
SHU1: VImm(0) -> SHU1.T0; SHU1: VImm(0) -> SHU1.T0;
Mfetch: Lpto %END_ITERATIONS_16 @(KI2); Mfetch: Lpto %END_ITERATIONS_16 @(KI2);
IMA0: T1 >> 8(W) -> IMA0.T2;NOP; IMA0: T1 >> 8(W) -> IMA0.T2;
NOP;
IMA0: T2 -> M[19]; IMA0: T2 -> M[19];
NOP;
R5: PreConfig(M[19][0]); R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0); R5: WriteConf(Mfetch) -> KI[3](Mode0);
SHU1: T0 | T0 -> IMA3.T4 || SHU0: Index(T1,T7)(T7 = T7 + V(4)) -> IMA0.T0; SHU1: T0 | T0 -> IMA3.T4 || SHU0: Index(T1,T7)(T7 = T7 + V(4)) -> IMA0.T0;
@ -89,11 +92,9 @@ cordicSCAsm:
IMA3: CPRS(T0)(CprsMode1) -> IMA2.T0; IMA3: CPRS(T0)(CprsMode1) -> IMA2.T0;
NOP; NOP;
NOP; NOP;
NOP;
IMA3: CPRS(T1)(CprsMode1) -> IMA2.T1; IMA3: CPRS(T1)(CprsMode1) -> IMA2.T1;
NOP; NOP;
NOP; NOP;
NOP;
IMA2: T0 << 16(W)(U) -> IMA2.T0 || IMA3: V(0) -> IMA3.T0; IMA2: T0 << 16(W)(U) -> IMA2.T0 || IMA3: V(0) -> IMA3.T0;
BIU0: Store(T2,T0); BIU0: Store(T2,T0);

37
MicroCode/Fre_comp/src/mpu0/freOffCompAsm.m0.asm
View File

@ -14,7 +14,7 @@ freOffCompAsm:
BIU1: Load(T0)(A++) -> M[2]; // fre_offfset_est BIU1: Load(T0)(A++) -> M[2]; // fre_offfset_est
BIU1: Load(T0)(A++) -> M[3]; // outputAddr BIU1: Load(T0)(A++) -> M[3]; // outputAddr
IMA0: V(517) -> IMA0.T0(Mode0);NOP; IMA0: V(512) -> IMA0.T0(Mode0);NOP;
IMA0: VHigh(T0,0) -> IMA0.T0(Mode0);NOP; IMA0: VHigh(T0,0) -> IMA0.T0(Mode0);NOP;
IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0);NOP; IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0);NOP;
@ -25,16 +25,41 @@ freOffCompAsm:
R5: M[2] -> BIU1.T1(Mode0); R5: M[2] -> BIU1.T1(Mode0);
R3: M[3] -> BIU3.T3(Mode0); R3: M[3] -> BIU3.T3(Mode0);
NOP;NOP;NOP; NOP;NOP;NOP;
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
MFetch: REPEAT @(10); MFetch: REPEAT @(10);
//IMA1: T3 >> 2(S) -> IMA0.T3(Mode0) || IMA2: T2 >> 2(S) -> IMA0.T2(Mode0);
NOP;
NOP;
NOP;
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 10 || IMA1: Wait 10 || BIU3: Wait 15;
MFetch: Lpto %ENDFRECOMP @(KI0); MFetch: Lpto %ENDFRECOMP @(KI0);
BIU0: Load(T0)(A++) -> IMA0.T3(Mode0) || BIU1: Load(T1)(A++) -> IMA0.T2(Mode0) || IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS)(T) -> BIU3.T1(Mode0) || BIU3: Store(T1,T3)(A++)(Mode0); IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS) -> IMA0.MR;
MFetch: REPEAT @(15);
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
IMA0: ReadMR(L) -> IMA1.T0; // real
IMA0: ReadMR(H) -> IMA2.T0; // imag
MFetch: REPEAT @(4);
IMA1: T0 >> 10(W) -> IMA0.T1 || IMA2: T0 >> 10(W) -> IMA2.T1;
MFetch: REPEAT @(2);
IMA0: CPRS(T1)(CprsMode1) -> IMA2.T2 || IMA2: CPRS(T1)(CprsMode1) -> IMA2.T3;
MFetch: REPEAT @(4);
//IMA0: T2>>4(S) -> IMA0.T2(Mode0);
IMA2: T3 << 16(W)(U) -> IMA2.T3;
NOP;NOP;
IMA2: T2 + T3(W) -> BIU3.T1;
//IMA0: T3>>4(S) -> IMA0.T3(Mode0);
NOP;NOP;
BIU3: Store(T1,T3)(A++);
ENDFRECOMP: ENDFRECOMP:
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || BIU3: Wait 0;
MFetch: REPEAT @(15); MFetch: REPEAT @(10);
MFetch:MPU.STOP; MFetch:MPU.STOP;

40
MicroCode/Fre_comp/src/mpu0/freOffCompAsm1.m0.asm Normal file
View File

@ -0,0 +1,40 @@
.section .text.m0, "ax"
.file "freOffCompAsm1.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global freOffCompAsm1
freOffCompAsm1:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
NOP;
BIU1: Load(T0)(A++) -> M[20];
BIU1: Load(T0)(A++) -> M[1]; // input signal
BIU1: Load(T0)(A++) -> M[2]; // fre_offfset_est
BIU1: Load(T0)(A++) -> M[3]; // outputAddr
IMA0: V(512) -> IMA0.T0(Mode0);NOP;
IMA0: VHigh(T0,0) -> IMA0.T0(Mode0);NOP;
IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0);NOP;
R5: PreConfig(M[20]);
R5: WriteConf(Mfetch) -> KI[0-15](Mode0);
R4: M[1] -> BIU0.T0(Mode0);
R5: M[2] -> BIU1.T1(Mode0);
R3: M[3] -> BIU3.T3(Mode0);
NOP;NOP;NOP;
MFetch: REPEAT @(10);
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 10 || IMA1: Wait 10 || BIU3: Wait 15;
MFetch: Lpto %ENDFRECOMP @(KI0);
BIU0: Load(T0)(A++) -> IMA0.T3(Mode0) || BIU1: Load(T1)(A++) -> IMA0.T2(Mode0) || IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS)(T) -> BIU3.T1(Mode0) || BIU3: Store(T1,T3)(A++)(Mode0);
ENDFRECOMP:
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || BIU3: Wait 0;
MFetch: REPEAT @(15);
MFetch:MPU.STOP;

1
MicroCode/Fre_comp/src/spu/freOffComp.s.c
View File

@ -6,6 +6,7 @@
void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int OutputAddr0){ void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int OutputAddr0){
int *Para = ConfigBaseAddr; int *Para = ConfigBaseAddr;
//Para[11] = 0xfff00000;
Para[16*0+0] = 960; Para[16*0+0] = 960;
//input Signal //input Signal

4
MicroCode/Fre_est/src/mpu0/freOffEstAsm.m0.asm
View File

@ -35,7 +35,7 @@ freOffEstAsm:
NOP; NOP;
Mfetch: Lpto %MFA @(KI0); Mfetch: Lpto %MFA @(KI0);
BIU0: Wait 0 || BIU1: Wait 0 || IMA1: Wait 11 || IMA2: Wait 11 || IMA0: Wait 13 ; BIU0: Wait 0 || BIU1: Wait 0 || IMA1: Wait 11 || IMA2: Wait 11 || IMA0: Wait 13 ;
BIU0: Load(T0)(A++) -> IMA1.T0(Mode0) || BIU1: Load(T1)(A++) -> IMA2.T1(Mode0) || IMA1: T0>>4(S) -> IMA0.T0(Mode0) || IMA2: T1>>4(S) -> IMA0.T1(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0); BIU0: Load(T0)(A++) -> IMA1.T0(Mode0) || BIU1: Load(T1)(A++) -> IMA2.T1(Mode0) || IMA1: T0>>2(S) -> IMA0.T0(Mode0) || IMA2: T1>>2(S) -> IMA0.T1(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0);
MFA: MFA:
@ -70,7 +70,7 @@ freOffEstAsm:
Mfetch: Lpto %ENDCORDIC @(KI1); Mfetch: Lpto %ENDCORDIC @(KI1);
IMA3: T0>>8(W) -> M[19]; IMA3: T0 >> 8(W) -> M[19];
NOP; NOP;
R5: PreConfig(M[19][0]); R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0); R5: WriteConf(Mfetch) -> KI[3](Mode0);

1
MicroCode/Fre_est/src/spu/freOffEst.s.c
View File

@ -20,7 +20,6 @@ void freOffEst(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int freEstOutAd
//Output //Output
Para[16*5+0] = freEstOutAddr; Para[16*5+0] = freEstOutAddr;
Para[16*5+4] = 4;
return; return;