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fre_est_mico

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apple 2025-06-14 20:19:30 +08:00
parent 55f091b222
commit bfb1ec312d
1 changed files with 17 additions and 8 deletions
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25
MicroCode/Fre_est/src/mpu0/freOffEstAsm.m0.asm
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@ -34,8 +34,8 @@ freOffEstAsm:
NOP; NOP;
NOP; NOP;
Mfetch: Lpto %MFA @(KI0); Mfetch: Lpto %MFA @(KI0);
BIU0: Wait 0 || BIU1: Wait 0 || IMA1: Wait 11 || IMA2: Wait 11 || IMA0: Wait 13 ; BIU0: Wait 0 || BIU1: Wait 0 || IMA1: Wait 10 || IMA2: Wait 10 || IMA0: Wait 12 ;
BIU0: Load(T0)(A++) -> IMA1.T0(Mode0) || BIU1: Load(T1)(A++) -> IMA2.T1(Mode0) || IMA1: T0>>2(S) -> IMA0.T0(Mode0) || IMA2: T1>>2(S) -> IMA0.T1(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0); BIU0: Load(T0)(A++) -> IMA1.T0(Mode0) || BIU1: Load(T1)(A++) -> IMA2.T1(Mode0) || IMA1: T0>>1(S) -> IMA0.T0(Mode0) || IMA2: T1>>1(S) -> IMA0.T1(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0);
MFA: MFA:
@ -45,10 +45,14 @@ freOffEstAsm:
IMA0: ReadMR(L) -> IMA0.T0; // real IMA0: ReadMR(L) -> IMA0.T0; // real
IMA0: ReadMR(H) -> IMA1.T0; // imag IMA0: ReadMR(H) -> IMA1.T0; // imag
NOP;NOP;NOP;NOP; NOP;NOP;NOP;NOP;
IMA0: T0 >> 12(W) -> IMA0.T0 || IMA1: T0 >> 12(W) -> IMA1.T0; IMA0: T0 >> 13(W) -> IMA0.T0 || IMA1: T0 >> 13(W) -> IMA1.T0;
NOP;NOP; NOP;NOP;
IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2; IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2;
NOP;
NOP;
NOP;
NOP;
IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2; IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2;
SHU1: VImm(0) -> SHU1.T0; SHU1: VImm(0) -> SHU1.T0;
IMA0: V(0) -> IMA0.T1; IMA0: V(0) -> IMA0.T1;
@ -56,7 +60,8 @@ freOffEstAsm:
SHU0: Index(T2,T6) -> IMA3.T1; SHU0: Index(T2,T6) -> IMA3.T1;
SHU1: Index(T2,T6) -> IMA3.T0; SHU1: Index(T2,T6) -> IMA3.T0;
NOP;NOP; NOP;
NOP;
IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0; IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0;
IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1; IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1;
@ -67,10 +72,8 @@ freOffEstAsm:
MFetch: REPEAT @(5); MFetch: REPEAT @(5);
//CORDIC ATAN2 //CORDIC ATAN2
Mfetch: Lpto %ENDCORDIC @(KI1); Mfetch: Lpto %ENDCORDIC @(KI1);
IMA3: T0 >> 8(W) -> M[19]; IMA3: T0>>8(W) -> M[19];
NOP; NOP;
R5: PreConfig(M[19][0]); R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0); R5: WriteConf(Mfetch) -> KI[3](Mode0);
@ -79,6 +82,12 @@ freOffEstAsm:
IMA3: T1 >> T4(W) -> IMA3.T2; IMA3: T1 >> T4(W) -> IMA3.T2;
IMA3: T0 >> T4(W) -> IMA3.T3; IMA3: T0 >> T4(W) -> IMA3.T3;
NOP; NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
MFetch: IF(KI3>=KI11) JUMP %IFFI; MFetch: IF(KI3>=KI11) JUMP %IFFI;
@ -99,7 +108,7 @@ ENDCORDIC:
IMA0: T1 -> BIU2.T0(Mode0); IMA0: T1 -> BIU2.T0(Mode0);
NOP;NOP;NOP;NOP; NOP;NOP;NOP;NOP;
BIU2: Store(T0,T1)(A++); BIU2: Store(T0,T1)(A++);
MFetch: REPEAT @(15);