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Recv_symb修改上传

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This commit is contained in:
HUOHUO 2025-05-27 10:22:07 -07:00
parent 696341f95d
commit c71fc90a43
30 changed files with 124576 additions and 62651 deletions
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3
.vscode/settings.json vendored
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@ -42,6 +42,7 @@
"receiver_sync_first_vars.h": "c",
"trasnsmitter_transform_para_func.h": "c",
"log_interface.h": "c",
"transform_para_func.h": "c"
"transform_para_func.h": "c",
"equalizer_1port.h": "c"
}
}

2
APE3/Makefile
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@ -1,6 +1,6 @@
############################
# mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp
MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp
############################
# tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

2
APE5/Makefile
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@ -1,6 +1,6 @@
############################
# mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp
MICRO_CODE_LIBS:=ByteCopy ByteSet BlockTransform Channel_Est Channel_Equ Fre_est Fre_comp
############################
# tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

3
APELib/Receiver_symb/inc/channelEquImpl.h
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@ -12,6 +12,7 @@
#include "type_define.h"
#include "ByteCopy.h"
#include "common.h"
#include "AgcShiftForFftInt32.h"
void ChannelEquImpl(
int *CfgFft4096,
@ -21,6 +22,7 @@ void ChannelEquImpl(
int *ConfigDataTurn,
int *ConfigAddCp,
int *CfgByteCopy,
int *CfgAgcShift,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,
@ -34,6 +36,7 @@ void ChannelEquImpl(
int *CalAddr1,
int *CalAddr2,
int *Lut_phase,
int *AgcFactor,
int res_ptr
);

4
APELib/Receiver_symb/inc/receiver_symb_macro.h
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@ -26,6 +26,7 @@
#define RECEIVER_SYMB_IFFT4096_CFG7_LENGTH (0x0360)
#define RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH (0x0070)
#define RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH (0x0070)
#define RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH (0x0130)
#define RECEIVER_SYMB_DeTransform2_CFG8_LENGTH (0x0060)
#define RECEIVER_SYMB_DeTransform4_CFG9_LENGTH (0x0080)
@ -38,7 +39,7 @@
#define RECEIVER_SYMB_FREOFF_CFG_LENGTH (RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH )
#define RECEIVER_SYMB_CHANNELEST_CFG_LENGTH (RECEIVER_SYMB_ChannelEst_CFG4_LENGTH)
#define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH )
#define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH )
#define RECEIVER_SYMB_DeTransformer_CFG_LENGTH (RECEIVER_SYMB_DeTransform2_CFG8_LENGTH + RECEIVER_SYMB_DeTransform4_CFG9_LENGTH + RECEIVER_SYMB_Transform8_CFG10_LENGTH)
#define RECEIVER_SYMB_COMMEN_CFG_LENGTH (RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH + RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH + RECEIVER_SYMB_DeTransformer_CFG_LENGTH)
@ -55,6 +56,7 @@
#define RECEIVER_SYMB_EqFactor1_LUT4_LENGTH (0x0800)
#define RECEIVER_SYMB_EqFactor_LUT5_LENGTH (0x0078)
#define RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH (0x0004)
#define RECEIVER_SYMB_AgcShiftFft_LUT7_LENGTH (0x0020)
//=======================================================================

2
APELib/Receiver_symb/src/ChannelEstImpl.s.c
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@ -15,7 +15,7 @@ void ChannelEstImpl(int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr)
}
ChannelEst(ConfigAddr, MPU_ADDR(InAddr1),MPU_ADDR(InAddr2),MPU_ADDR(OutAddr));
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
SVRReg[0] = MPU_ADDR(ConfigAddr);
channelEstAsm(SVRReg);

151
APELib/Receiver_symb/src/channelEquImpl.s.c
View File

@ -2,6 +2,8 @@
#include "ucps2.h"
#include "ucpm2.h"
#include <channelEquImpl.h>
#include "trace.h"
#ifdef IDE_TEST
#include <Test_Func.h>
@ -15,6 +17,7 @@ void ChannelEquImpl(
int *ConfigDataTurn,
int *ConfigAddCp,
int *CfgByteCopy,
int *CfgAgcShift,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,
@ -28,12 +31,13 @@ void ChannelEquImpl(
int *CalAddr1,
int *CalAddr2,
int *Lut_phase,
int *AgcFactor,
int res_ptr
){
volatile int a = 1;
int numSym = 7;
int numSym = 7 ; ///7;
int Scale = 13;
int NRE=4096;
int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
@ -51,14 +55,34 @@ void ChannelEquImpl(
/*****************************************FFT of channelEst*****************************************/
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InChannelEst_ddr_ptr + 4096*i) ,
(uint64_t)DM_TO_CSU_ADDR(channelEst_dm0_ptr),
4096*4,
DMA_TAG_G2L,
1);
ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)(InChannelEst_ddr_ptr + 4096*i) ,
(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
4096*4,
DMA_TAG_G2L,
1);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
AgcShiftForFftInt32(
(int)CfgAgcShift,
MPU_ADDR(Fft_est_dm3_ptr),
MPU_ADDR(Fft_est_dm3_ptr),
4096,
1,
MPU_ADDR(AgcFactor),
MPU_ADDR(AgcFactor),
MPU_ADDR(channelEst_dm0_ptr),
MPU_ADDR(channelEst_dm0_ptr)
);
SVRReg[0] = MPU_ADDR(CfgAgcShift);
AgcShiftForFftInt32Asm(SVRReg);
WAIT_MPU_STOP;
Fft4096Int32(
(int)CfgFft4096,
1,
@ -77,22 +101,60 @@ void ChannelEquImpl(
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_est_dm3_ptr),
(uint64_t)0x84c00000,
4096*4 ,
DMA_TAG_L2G,
1);
//构造第二根天线
ByteCopy((int)CfgByteCopy, MPU_ADDR(channelEst_dm0_ptr),MPU_ADDR(Fft_est_dm3_ptr + 4096),16384);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
if(i==1){
InData_ddr_ptr = InData_ddr_ptr + 7*(68+4096) + 1024 + 72;
}
/*****************************************channelEqu*****************************************/
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)(InData_ddr_ptr + 68) ,
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
4096*4,
DMA_TAG_G2L,
1);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
for(int j=0;j<numSym;j++){
AgcShiftForFftInt32(
(int)CfgAgcShift,
MPU_ADDR(Fft_outputdata_dm3_ptr),
MPU_ADDR(Fft_outputdata_dm3_ptr),
4096,
1,
MPU_ADDR(AgcFactor),
MPU_ADDR(AgcFactor),
MPU_ADDR(InData_dm0_ptr),
MPU_ADDR(InData_dm0_ptr)
);
SVRReg[0] = MPU_ADDR(CfgAgcShift);
AgcShiftForFftInt32Asm(SVRReg);
WAIT_MPU_STOP;
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
if(j==0){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*j + 68) ,
(uint64_t)DM_TO_CSU_ADDR(InData_dm0_ptr),
4096*4,
DMA_TAG_G2L,
1);
}
TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, *Fft_outputdata_dm3_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, *(Fft_outputdata_dm3_ptr+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 14, *InData_dm0_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 15, *(InData_dm0_ptr+1));
// FFT of Data
Fft4096Int32(
@ -109,13 +171,19 @@ void ChannelEquImpl(
MPU_ADDR(Scale0)
);
SVRReg[0] = MPU_ADDR((int)CfgFft4096);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
Fft4096Int32Asm(SVRReg);
WAIT_MPU_STOP;
// 构造第二根天线数据，与第一根相同
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
(uint64_t)0x84d00000,
4096*4 ,
DMA_TAG_L2G,
1);
// 构造第二根天线数据，与第一根相同
ByteCopy((int)CfgByteCopy, MPU_ADDR(InData_dm0_ptr),MPU_ADDR(Fft_outputdata_dm3_ptr + 4096),16384);
SVRReg[0] = MPU_ADDR(CfgByteCopy);
ByteCopyAsm(SVRReg);
@ -127,7 +195,6 @@ void ChannelEquImpl(
WAIT_MPU_STOP;
EQ21Part1(
CfgEQ21Part1,
NRE,
@ -142,15 +209,6 @@ void ChannelEquImpl(
);
SVRReg[0] = MPU_ADDR(CfgEQ21Part1);
EQ21Part1Asm(SVRReg);
if(j<numSym-1){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*(j+1) + 68) ,
(uint64_t)DM_TO_CSU_ADDR(InData_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
}
WAIT_MPU_STOP;
int *Equ_Output_2 = available_ptr_dm2; //第一根天线均衡输出
@ -166,11 +224,32 @@ void ChannelEquImpl(
MPU_ADDR(Equ_Output_2),
MPU_ADDR(Equ_Output_21)
);
WAIT_MPU_STOP;
SVRReg[0]= MPU_ADDR(ConfigBaseAddr3);
EQ1Part2Asm(SVRReg);
WAIT_MPU_STOP;
int *Temp1 = Fft_outputdata_dm3_ptr; // 缓存
TRACE(TRACE_RECEIVER_SYMB_ADDR, 16, *Equ_Output_2);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, *(Equ_Output_2+2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, *(Equ_Output_2+3));
//提前准备下一块数据
if(j<numSym-1){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*(j+1) + 68), //(68+4096)*(j+1) + 68)
(uint64_t)DM_TO_CSU_ADDR(Fft_outputdata_dm3_ptr),
4096*4,
DMA_TAG_G2L,
0);
}
/****************************** IFFT ****************************************8*/
int *Temp1 = Fft_outputdata_dm3_ptr + 0x1000; // 缓存
IFFT4096DataTurn(
(int)ConfigDataTurn,
1,
@ -180,13 +259,11 @@ void ChannelEquImpl(
MPU_ADDR(Equ_Output), //dm0
MPU_ADDR(Temp1) //dm3 无效
);
SVRReg[0]= MPU_ADDR(ConfigDataTurn);
IFFT4096DataTurnAsm(SVRReg);
WAIT_MPU_STOP;
int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
IFFT4096(
(int)CfgIFFT4096,
@ -218,10 +295,12 @@ void ChannelEquImpl(
MPU_ADDR(Lut_phase) //
);
SVRReg[0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(SVRReg);
WAIT_MPU_STOP;
SVRReg[0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(SVRReg);
WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *(Equ_Output_2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *(Equ_Output_2+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(Equ_Output_2+2));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(

11
APELib/Receiver_symb/src/channelEqu_proc.s.c
View File

@ -2,6 +2,7 @@
#include "receiver_symb_func.h"
#include "ByteSet.h"
void ChannelEqu_Proc(
uint32_t* param_data_ptr,
int32_t *temp_dm0_ptr,
@ -42,7 +43,8 @@ void ChannelEqu_Proc(
uint32_t *CfgEQ1Part2 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH;
uint32_t *CfgIFFT4096 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH;
uint32_t *CfgIFFT4096TURN = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH;
uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH;
uint32_t *CfgAgcShift = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH;
uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_AgcShiftFft_CFG7_LENGTH;
uint32_t *CfgByteCopy= receiver_symb_config_dm0_ptr + RECEIVER_SYMB_COMMEN_CFG_LENGTH + RECEIVER_SYMB_ByteSet_CFG10_LENGTH;
// LUT
@ -52,11 +54,13 @@ void ChannelEqu_Proc(
uint32_t *Lut_EqFactor = receiver_symb_config_dm1_ptr;
uint32_t *Lut_Zero = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH; //useless
uint32_t *Lut_phase = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH ;
uint32_t *Lut_agcFactor = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH + RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH;
// channelEst and data
uint32_t *InputCHEst_ddr_ptr = (uint32_t *)CHANNELEST_DATA_DDR_PTR;
uint32_t *InputData_ddr_ptr = (uint32_t *)COMPENSATED_DATA_DDR_PTR;
ChannelEquImpl(CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,CfgByteCopy,
uint32_t *InputData_ddr_ptr = (uint32_t *)(COMPENSATED_DATA_DDR_PTR + 2048*4); //去除导频
ChannelEquImpl(CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,CfgByteCopy,CfgAgcShift,
available_ptr_dm0,
available_ptr_dm1,
available_ptr_dm2 ,
@ -70,6 +74,7 @@ void ChannelEqu_Proc(
Lut_EqFactor1,
Lut_EqFactor,
Lut_phase,
Lut_agcFactor,
res_ptr
);

22
APELib/Receiver_symb/src/channelEst_Proc.s.c
View File

@ -43,12 +43,15 @@ void ChannelEst_Proc(
time_data_ddr_ptr = COMPENSATED_DATA_DDR_PTR + sliceIndex[subIndex]*4;
time_data_length = 1024;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(InputPilotAddr),
time_data_length*4,
DMA_TAG_G2L,
0);
ape_csu_dma_1D_G2L_ch0ch1_transfer(
(uint64_t)time_data_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(InputPilotAddr),
time_data_length*4,
DMA_TAG_G2L,
1);
WAIT_MPU_STOP;
// 新增了Pilot正变换
double thita[6];
@ -58,12 +61,11 @@ void ChannelEst_Proc(
uint32_t *PilotTrans = temp_dm3_ptr;
Transform((int)cfg_transform8,MPU_ADDR(Pilot_orig_LUT),MPU_ADDR(PilotTrans), 8, db_real, db_imag, 1);
SVRReg[0] = MPU_ADDR(cfg_transform8);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
Transform8Asm(SVRReg);
WAIT_MPU_STOP;
ChannelEstImpl(ConfigAddr_channelEst, PilotTrans, InputPilotAddr, channelEstOutAddr + subIndex*4096);
// TODO 此处应使用PilotTrans替换Pilot_orig_LUT
ChannelEstImpl(ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr + subIndex*4096);
WAIT_MPU_STOP;
}

14
APELib/Receiver_symb/src/freOffCompImpl.s.c
View File

@ -25,7 +25,7 @@ void freOffCompImpl(int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOut
int *input_data_ptr = ava_ptr_dm3;
int *fre_comp_exp_ptr = ava_ptr_dm2;
int *output_data_ptr = ava_ptr_dm3;
int *output_data_ptr = freEstOutAddr + 0x1000;
int time_data_length = count*128;
@ -42,7 +42,12 @@ void freOffCompImpl(int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOut
1);
WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, *fre_comp_exp_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, *(fre_comp_exp_ptr+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, *(fre_comp_exp_ptr+2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, *freEstOutAddr);
freOffComp(ConfigAddr_comp,MPU_ADDR(input_data_ptr),MPU_ADDR(fre_comp_exp_ptr),MPU_ADDR(output_data_ptr));
ape_csu_task_lookup(DMA_TAG_G2L, 1);
WAIT_MPU_STOP;
@ -50,6 +55,11 @@ void freOffCompImpl(int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOut
freOffCompAsm(SVRReg);
WAIT_MPU_STOP;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, *output_data_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, *(output_data_ptr+1));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 23, *(output_data_ptr+2));
TRACE(TRACE_RECEIVER_SYMB_ADDR, 24, *(output_data_ptr+3));
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr),
(uint64_t)(res_ptr_ddr + res_ptr_offset),
time_data_length*4 ,

2
APELib/Receiver_symb/src/freOffEstImpl.s.c
View File

@ -7,6 +7,7 @@
#include "common.h"
v16u32 KI = {2,4,6};
@ -16,6 +17,7 @@ void freOffEstImpl(int* ConfigBaseAddr_est, int *InputAddr0,int *InputAddr1,int
freOffEst(ConfigBaseAddr_est, MPU_ADDR(InputAddr0), MPU_ADDR(InputAddr1), MPU_ADDR(freEstOutAddr));
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
SVRReg[0] = MPU_ADDR(ConfigBaseAddr_est);
freOffEstAsm(SVRReg);

31
APELib/Receiver_symb/src/freoff_Proc.s.c
View File

@ -20,15 +20,16 @@ void FreOff_Proc(
uint32_t time0, time1;
// Read Global Buff
time_data_ddr_ptr = (uint32_t)*param_ptr;
time_data_ddr_ptr = (uint32_t)param_ptr;
time_data_length = 2048;
TRACE(TRACE_RECEIVER_SYMB_ADDR, 14, time_data_ddr_ptr);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(time_data_dm3_ptr),
time_data_length*4,
DMA_TAG_G2L,
0);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
// Get Configuration
uint32_t *ConfigAddr_est = receiver_symb_config_dm0_ptr;
uint32_t *ConfigAddr_comp = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH;
@ -37,10 +38,27 @@ void FreOff_Proc(
// Get CP and Pilot
uint32_t *InputCPAddr = (uint32_t *)time_data_dm3_ptr;
uint32_t *InputPilotAddr = InputCPAddr + 1024;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 15, *InputCPAddr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 16, *InputPilotAddr);
uint32_t *freEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0020);
time0 = Time_offset(0);
//20250509
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)receiver_symb_config_dm0_ptr),
(uint64_t)0x84c00000,
144*4,
DMA_TAG_L2G,
1);
ape_csu_task_lookup(DMA_TAG_L2G, 1);
freOffEstImpl(ConfigAddr_est, InputCPAddr, InputPilotAddr, freEstOutAddr);
WAIT_MPU_STOP;
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 9, time1-time0);
time0 = time1;
@ -51,6 +69,15 @@ void FreOff_Proc(
else{
storedfreoffestvalue = 0.7*storedfreoffestvalue + 0.3*freEstOutAddr[0];
}
TRACE(TRACE_RECEIVER_SYMB_ADDR, 12, freEstOutAddr[0]);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 13, 0xa0870);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 17, freEstOutAddr[1]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 18, freEstOutAddr[2]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 19, freEstOutAddr[3]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 20, freEstOutAddr[4]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 21, freEstOutAddr[5]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 22, freEstOutAddr[6]);
// TRACE(TRACE_RECEIVER_SYMB_ADDR, 23, freEstOutAddr[7]);
freEstOutAddr[0] = storedfreoffestvalue;
// Frequency Offset Compensate

53
APELib/Receiver_symb/src/receiver_Symb_Init.s.c
View File

@ -63,4 +63,57 @@ void Receiver_Symb_Init()
{
LOG_ERROR_S("Receiver_Symb_cfg_dm3.dat not found!\n");
}
uint32_t timedata_ptr;
int32_t timedata_len;
ret = osp_get_cfgfile("timedatasym.dat",
(uint32_t *)&(timedata_ptr),
(int32_t *)&(timedata_len));
if(-1 == ret)
{
LOG_ERROR_S("timedatasym.dat not found!\n");
}
// int* param_ptr = (int *)RECEIVER_SYMB_CFG_BASE;
// STORE_EX_W(param_ptr, timedata_ptr);
// STORE_EX_W((param_ptr+1), timedata_len);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr),
(uint64_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR,//第一次固定搬移到dm0
timedata_len,
DMA_TAG_G2G,
1);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(timedata_ptr),
(uint64_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR,//第一次固定搬移到dm0
timedata_len,
DMA_TAG_G2G,
1);
uint32_t ptr1,ptr2,len1,len2;
ret = osp_get_cfgfile("channel_est_1_Quan.dat",
(uint32_t *)&(ptr1),
(int32_t *)&(len1));
if(-1 == ret)
{
LOG_ERROR_S("timedatasym.dat not found!\n");
}
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(ptr1),
(uint64_t)CHANNELEST_DATA_DDR_PTR,//第一次固定搬移到dm0
len1,
DMA_TAG_G2G,
1);
ret = osp_get_cfgfile("EquIn_Quan.dat",
(uint32_t *)&(ptr2),
(int32_t *)&(len2));
if(-1 == ret)
{
LOG_ERROR_S("timedatasym.dat not found!\n");
}
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(ptr2),
(uint64_t)COMPENSATED_DATA_DDR_PTR,//第一次固定搬移到dm0
len2,
DMA_TAG_G2G,
1);
}

14
APELib/Receiver_symb/src/receiver_Symb_Proc.s.c
View File

@ -68,12 +68,12 @@ void Receiver_Symb_Proc(
return ;
// //计算结果搬移到外存
// temp_u32 = 1000;//计算byte数
// WAIT_MPU_STOP;
// ape_csu_task_lookup(DMA_TAG_G2L, 1);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 2);
time0 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 4, time0);
@ -83,6 +83,7 @@ void Receiver_Symb_Proc(
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 5, time1 -time0);
time0 = time1;
ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr,temp_dm2_ptr,temp_dm3_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 4);
@ -95,7 +96,12 @@ void Receiver_Symb_Proc(
time1 = Time_offset(0);
TRACE_MAX(TRACE_RECEIVER_SYMB_ADDR, 7, time1 -time0);
time0 = time1;
__ucps2_synch(0);
__ucps2_synch(0);
__ucps2_synch(0);
__ucps2_synch(0);
__ucps2_synch(0);
__ucps2_dbgbreak();
Transform_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 6);
time1 = Time_offset(0);

6
APELib/Receiver_symb/src/receiver_Symb_Task.s.c
View File

@ -9,6 +9,7 @@
*****************************************************************/
#include "receiver_symb_func.h"
#include "transform_para_func.h"
#define ADDR_ALIGN(addr, val) ((((uint32_t)(addr) + (2<<(val)) - 1)>>(val))<<(val))
@ -54,12 +55,13 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
//DM0第一段，调度信息
receiver_symb_param_ptr = (uint32_t)receiver_symb_malloc_dm0_ptr;
const uint32_t receiver_param_len = sizeof(receiver_sync2symb_t); //
if(0 < receiver_param_len)
{
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)msg_ptr,
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)msg_ptr,
(uint64_t)DM_TO_CSU_ADDR(receiver_symb_param_ptr),
receiver_param_len,
DMA_TAG_G2L,
DMA_TAG_G2L,
0);
}
//DM0第二段，微码相关空间

98
APELib/Receiver_symb/src/transform_Proc.s.c
View File

@ -14,7 +14,6 @@ void Transform_Proc(
uint32_t equ_data_ddr_ptr = CHANNELEQU_DATA_DDR_PTR; // COMPENSATED_DATA_DDR_PTR; // EQU_DATA_DDR_PTR;
// uint32_t res_ptr = CHANNELEQU_DATA_DDR_PTR;
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
uint32_t symbol_SM_addr_in = equ_data_ddr_ptr;
uint32_t symbol_SM_addr_out = TRANSFORMER_DATA_DDR_PTR;
@ -31,67 +30,70 @@ void Transform_Proc(
double *db_imag = proc_info->transform_para_real;
double *db_real = proc_info->transform_para_imag;
// int current_state[9 + 11 + 13];
// for (int ii = 0; ii < 9 + 11 + 13; ii++){
// int tmp = rand();
// if(tmp>RAND_MAX/2)
// current_state[ii] = 1;
// else
// current_state[ii] = 0;
// }
// get_thita(current_state,thita);
// double* thita1, * thita2, * thita3;
// thita1 = thita2 = thita;
// thita3 = thita;
for(int iBlk = 0;iBlk < 7;iBlk++){
ape_csu_dma_1D_G2L_ch2ch3_transfer(
for(int iBlk = 0;iBlk < 7;iBlk++){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(equ_data_ddr_ptr + 4096*4*2*iBlk),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(TransTemp), //uint64_t addrDst
4096*4*2, //uint32_t dataLen
DMA_TAG_G2L, //uint8_t tag
1 //uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TransformImpl(SVRReg, Cfg_DeTransform4,TransTemp,OutputAddr_Trans, 4, db_real, db_imag, -1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)OutputAddr_Trans),
Transform((int)Cfg_DeTransform4,MPU_ADDR(TransTemp),MPU_ADDR(OutputAddr_Trans), 4, db_real, db_imag, -1);
SVRReg[0]= MPU_ADDR(Cfg_DeTransform4);
Transform4Asm(SVRReg);
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)OutputAddr_Trans),
(uint64_t)symbol_SM_addr_in + 4096*4*2*iBlk,
4096*4*2,
DMA_TAG_L2G,
1);
}
for(int iSym = 0;iSym < 8;iSym++){
//reading 2D data from SM
ape_csu_dma_3Dto1D_G2L_ch6ch2_simp_transfer(
symbol_SM_addr_in + 512*4*iSym, //addrSrc
512*4, //xNumSrc
14, //yNumSrc
4096*4, //yStepSrc
0, //zStepSrc
DM_TO_CSU_ADDR(InputAddr_Trans), //DM_TO_CSU_ADDR(InputAddr_Trans)
14*512*4, //dataLen
DMA_TAG_G2L, //tag
1);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TransformImpl(SVRReg, Cfg_DeTransform2,InputAddr_Trans,TransTemp, 2, db_real, db_imag, -1);
for(int i = 0; i<14;i++){
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(TransTemp + 512*4*i), //uint64_t addrSrc
(uint64_t)(symbol_SM_addr_out + 4096*4*i + 512*4*iSym), //uint64_t addrDst
512*4, //uint32_t dataLen
DMA_TAG_L2G, //uint8_t tag
1);
ape_csu_task_lookup(DMA_TAG_L2G, 1);
}
}
}
return ;
for(int iSym = 0;iSym < 8;iSym++){
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_2Dto2D_transfer(
symbol_SM_addr_out + 512*4*iSym,//源地址
512*4, //源第一维度搬移字节数
4096*4, //源第二维度搬移步进字节数
DM_TO_CSU_ADDR(InputAddr_Trans), //目的地址
2048, //目的第一维度搬移字节数
2048,//目的第二维度搬移步进字节数
28672,//搬移总字节数
DMA_TAG_G2L, //Tag
1, //iswait
2, //reggroup
DMA_DIR_G2L);
Transform((int)Cfg_DeTransform2,MPU_ADDR(InputAddr_Trans),MPU_ADDR(TransTemp), 2, db_real*1.375, db_imag*1.375, -1);
SVRReg[0] = MPU_ADDR(Cfg_DeTransform2);
Transform2Asm(SVRReg);
WAIT_MPU_STOP;
ape_csu_dma_2Dto2D_transfer(
DM_TO_CSU_ADDR(TransTemp),
//DM_TO_CSU_ADDR(InputAddr_Trans),
2048,
2048,
symbol_SM_addr_out + 2048*iSym,//源地址
512*4, //源第一维度搬移字节数
4096*4, //源第二维度搬移步进字节数
28672,//搬移总字节数14*512*4
DMA_TAG_L2G, //Tag
1, //iswait
2, //reggroup
DMA_DIR_L2G);
}
return ;
}

8
APELib/Receiver_sync/src/receiver_Sync_Proc.s.c
View File

@ -196,6 +196,14 @@ void Receiver_Sync_Proc(
receiver_sync2first_sync_t temp_msg;
temp_msg.sfn = cur_sfn;
temp_msg.slot = cur_slot;
// phy_et_msg_send((uint32_t)(&temp_msg),
// sizeof(receiver_sync2first_sync_t),
// UCP4008_KERNEL_INTER,
// APE4_CORE_ID,
// APE6_CORE_ID,
// PHY_TASK_RECEIVER_SYNC,
// PHY_TASK_RECEIVER_BIT);
phy_et_msg_send((uint32_t)(&temp_msg),
sizeof(receiver_sync2first_sync_t),
UCP4008_KERNEL_INNER,

57344
Config/EquIn_Quan.dat Normal file
View File

File diff suppressed because it is too large Load Diff

150
Config/Receiver_Symb_cfg_dm0.dat
View File

@ -338,12 +338,12 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0x04000400,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
@ -398,22 +398,22 @@
0x00000000,
0x00000000,
0x00000000,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x01010000,
0x01010000,
0x01010000,
@ -2670,6 +2670,118 @@
0x00000002,
0x00000002,
0x00000002,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00400306,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00400306,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x0040004a,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0xffffffff,
0xffffffff,
0x00000000,
0x00ffffff,
0x0040004a,
0x00000000,
0x00000000,
0x00000003,
0x00000003,
0x00000100,

2144
Config/Receiver_Symb_cfg_dm2.dat
View File

File diff suppressed because it is too large Load Diff

4096
Config/channel_est_1_Quan.dat Normal file
View File

File diff suppressed because it is too large Load Diff

122854
Config/timedatasym.dat
View File

File diff suppressed because it is too large Load Diff

8
MicroCode/Channel_Equ/inc/AgcShiftForFftInt32.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef AGCSHIFTFORFFTINT32_H_
#define AGCSHIFTFORFFTINT32_H_
#include "ucps2.h"
MPU_ENTRY void AgcShiftForFftInt32Asm(v16u32 src);
void AgcShiftForFftInt32(int ConfigAddr,int InAddr_1,int InAddr_2,int ReNum,int nSyms,int AgcAddr_1,int AgcAddr_2,int OutAddr_1,int OutAddr_2);
#endif

37
MicroCode/Channel_Equ/src/mpu0/AgcShiftForFftInt32Asm.m0.asm Normal file
View File

@ -0,0 +1,37 @@
.section .text.m0, "ax"
.file "AgcShiftForFftInt32Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global AgcShiftForFftInt32Asm
AgcShiftForFftInt32Asm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0];
BIU1:Load(T0)(A++) -> BIU1.T1;
BIU1:Load(T0)(A++) -> M[2];//agcfactor
BIU1:Load(T0)(A++) -> M[3];
BIU1:Load(T0)(A++) -> M[4];
BIU1:Load(T0)(A++) -> M[5];
BIU1:Load(T0)(A++) -> M[6];
NOP;
NOP;
R5:PreConfig(M[0]);
R5:WriteConf(Mfetch)->KI[0-3];
R0:M[2] -> BIU0.T1;
R0:M[3] -> BIU0.T2;
R1:M[4] -> BIU1.T2;
R2:M[5] -> BIU2.T1;
R3:M[6] -> BIU3.T1;
NOP;
NOP;
MFetch:LPTO %Symbol @(KI0);
BIU1:Load(T1)(A++) -> IMA2.T4;
BIU0:Wait 0 || IMA2: Wait 10 || BIU2:Wait 13 || BIU1:Wait 0 || IMA0: Wait 10 || BIU3:Wait 13 ;
BIU0:Load(T2)(A++) -> IMA2.T0 || IMA2: T0 << T4(S) -> BIU2.T0 || BIU2:Store(T0,T1)(A++)(Mask) || MFetch:REPEAT @(KI1);
Symbol:
MFetch:Repeat @(20);
MFetch:MPU.STOP;

46
MicroCode/Channel_Equ/src/spu/AgcShiftForFftInt32.s.c Normal file
View File

@ -0,0 +1,46 @@
#include <AgcShiftForFftInt32.h>
#include "ucps2.h"
#include "ucpm2.h"
void AgcShiftForFftInt32(int ConfigAddr,int InAddr_1,int InAddr_2,int ReNum,int nSyms,
int AgcAddr_1,int AgcAddr_2,int OutAddr_1,int OutAddr_2)
{
for(int ii=0;ii<16;ii++){
AgcAddr_1[ii] = 1;
}
int *Para = (int *)ConfigAddr;
int temp0 = (ReNum+15)>>4;
int i;
Para[0] = nSyms;
Para[1] = temp0;
Para[1*16] = AgcAddr_1;
Para[2*16] = AgcAddr_2;
Para[3*16] = InAddr_1;
Para[3*16+1] = InAddr_1;
Para[3*16+5] = ReNum*4;
Para[3*16+8] = (temp0<<16)+temp0;
Para[4*16] = InAddr_2;
Para[4*16+1] = InAddr_2;
Para[4*16+5] = ReNum*4;
Para[4*16+8] = (temp0<<16)+temp0;
Para[5*16] = OutAddr_1;
Para[5*16+1] = OutAddr_1;
Para[5*16+5] = ReNum*4;
Para[5*16+8] = (temp0<<16)+temp0;
Para[5*16+12] = (temp0*(nSyms-1)*16+ReNum)*4;
Para[6*16] = OutAddr_2;
Para[6*16+1] = OutAddr_2;
Para[6*16+5] = ReNum*4;
Para[6*16+8] = (temp0<<16)+temp0;
Para[6*16+12] = (temp0*(nSyms-1)*16+ReNum)*4;
}

84
MicroCode/Channel_Est/inc/ConfigMatrix.dat
View File

@ -1,21 +1,21 @@
//ShiftMode
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
0x0000023b,
//InputA
0x00000000,
@ -26,8 +26,8 @@
0x00000000,
0x00000000,
0x00000000,
0x04000400,
0x00200020,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
@ -39,12 +39,12 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000040,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0x04000400,
0x00200020,
0x00000000,
0x00000000,
0x003fffff,
@ -57,11 +57,11 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0x00000020,
0x00000002,
0x00000000,
0x00000000,
0x00000000,
@ -72,7 +72,7 @@
//ki
0x00000400,
0x00000020,
0x00000001,
0x00000000,
0x00000000,
0x00000000,
@ -86,4 +86,40 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
0x00000200,
//Index1
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,
0x01010000,

7
MicroCode/Channel_Est/src/mpu0/channelEstAsm.m0.asm
View File

@ -36,6 +36,7 @@
R2:M[3] -> BIU2.T0(Mode0);//output1
NOP;
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA0:SetShiftMode(T1) -> SHIFTMODE1(Mode0)||IMA1:SetShiftMode(T1) -> SHIFTMODE1(Mode0)||IMA2:SetShiftMode(T1) -> SHIFTMODE1(Mode0)||IMA3:SetShiftMode(T1) -> SHIFTMODE1(Mode0);
R5:PreConfig(M[63])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
@ -47,14 +48,13 @@
NOP;
NOP;
NOP;
MFetch:LPTO %Double @(KI1 - 0);
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
IMA1:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA1.MR(Mode0);
IMA2:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA2.MR(Mode0);
IMA3:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA3.MR(Mode0);
MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
BIU0:Load(T0)(A++)-> SHU0.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA0.T2(Mode0);
BIU0:Load(T0)(A++)-> SHU0.T2(Mode0)||BIU3:Load(T0)(A++)-> IMA1.T2(Mode0);
BIU3:Load(T0)(A++)-> IMA1.T2(Mode0);
/*BIU0:Load(T0)(A++)-> IMA2.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA2.T2(Mode0);
BIU0:Load(T0)(A++)-> IMA3.T1(Mode0)||BIU3:Load(T0)(A++)-> IMA3.T2(Mode0);*/
NOP;
@ -68,7 +68,7 @@ MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
NOP;
NOP;
SHU0:Index(T4,T1,T0) -> IMA0.T1(Mode0);
SHU0:Index(T4,T2,T0) -> IMA1.T1(Mode0);
SHU0:Index(T4,T1,T0) -> IMA1.T1(Mode0);
NOP;
NOP;
IMA0:MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
@ -90,6 +90,5 @@ ComplexMult_Loop:
NOP;
NOP;
NOP;
Double:
MFetch:Repeat @(10);
MFetch:MPU.STOP;

18
MicroCode/Fre_comp/src/mpu0/cordicSCAsm.m0.asm
View File

@ -28,7 +28,7 @@ cordicSCAsm:
R1: M[4] -> SHU0.T7(Mode0);
R2: M[6] -> BIU2.T1(Mode0);
R5: M[20] -> IMA0.T4(Mode0);
MFetch: REPEAT @(10);
IMA1: V(0) -> IMA1.T0 || IMA2: V(0) -> IMA2.T0;
IMA3: V(0) -> IMA3.T0; // y0
IMA1: VHigh(T0,0x8000) -> IMA1.T3 || IMA2: VHigh(T0,0x4000) -> IMA1.T1;
@ -40,11 +40,16 @@ cordicSCAsm:
BIU0: Load(T0) -> IMA1.T0;
MFetch: REPEAT @(10);
IMA1: T0 -> IMA0.T3;NOP;
IMA1: T0 -> IMA0.T3;
NOP;
NOP;
MFetch: REPEAT @(4);
MFetch: Lpto %ENDCORDIC @(KI1);
IMA0: T3 + T4(W)(U)(T) -> IMA1.T0;NOP;NOP;
IMA0: T3 + T4(W)(U)(T) -> IMA1.T0;
NOP;
NOP;
IMA1: T0 -> IMA0.T3; NOP;
IMA1: T0 + T3(W)(U)(T) -> IMA1.T4;NOP;
@ -82,8 +87,13 @@ cordicSCAsm:
IMA3: 0 - T0(W) -> IMA3.T0;
IMA0: T3 -> BIU0.T2;
IMA3: CPRS(T0)(CprsMode1) -> IMA2.T0;
NOP;
NOP;
NOP;
IMA3: CPRS(T1)(CprsMode1) -> IMA2.T1;
NOP;NOP;
NOP;
NOP;
NOP;
IMA2: T0 << 16(W)(U) -> IMA2.T0 || IMA3: V(0) -> IMA3.T0;
BIU0: Store(T2,T0);

12
MicroCode/Fre_est/src/mpu0/freOffEstAsm.m0.asm
View File

@ -29,15 +29,17 @@ freOffEstAsm:
R0: M[7] -> SHU0.T7(Mode0);
IMA0: SetMR(0)(L);
IMA0: SetMR(0)(H);
IMA0: SetMR(0)(O1);
IMA0: SetMR(0)(O2);
NOP;
NOP;
Mfetch: Lpto %MFA @(KI0);
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 11 ;
BIU0: Load(T0)(A++) -> IMA0.T0(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0);
BIU1: Load(T1)(A++) -> IMA0.T1(Mode0);
BIU0: Wait 0 || BIU1: Wait 0 || IMA1: Wait 11 || IMA2: Wait 11 || IMA0: Wait 13 ;
BIU0: Load(T0)(A++) -> IMA1.T0(Mode0) || BIU1: Load(T1)(A++) -> IMA2.T1(Mode0) || IMA1: T0>>4(S) -> IMA0.T0(Mode0) || IMA2: T1>>4(S) -> IMA0.T1(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0);
MFA:
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 ;
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 || IMA1:Wait 0 || IMA2:Wait 0 ;
MFetch: REPEAT @(15);
IMA0: ReadMR(L) -> IMA0.T0; // real
@ -68,7 +70,7 @@ freOffEstAsm:
Mfetch: Lpto %ENDCORDIC @(KI1);
IMA3: T0 -> M[19];
IMA3: T0>>8(W) -> M[19];
NOP;
R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0);

1
MicroCode/Fre_est/src/spu/freOffEst.s.c
View File

@ -20,6 +20,7 @@ void freOffEst(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int freEstOutAd
//Output
Para[16*5+0] = freEstOutAddr;
Para[16*5+4] = 4;
return;