jinhong/YB_TX_RX_APE_PRJ
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245.76采样率，TX RX合并的工程，Platform采用25_06_05 23:00方案

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This commit is contained in:
HUOHUO 2025-06-05 08:35:11 -07:00
parent ccf3bafb12
commit df15a759af
47 changed files with 128332 additions and 165983 deletions
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2
APE0/Makefile
View File

@ -1,7 +1,7 @@
############################
# mpu libs need to link to this APE, could be specified by user
#MICRO_CODE_LIBS:=LDPCCBSegment LDPCEncoding RMLDPC Modulation Transform ByteCopy
MICRO_CODE_LIBS:=LDPCCBSegment LDPCEncoding RMLDPC Modulation BlockTransform ByteCopy
MICRO_CODE_LIBS:=LDPCCBSegment LDPCEncoding RMLDPC Modulation BlockTransform ByteCopy InterpolationLTE_2nd
############################
# tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

6
APELib/Receiver_sync/src/receiver_Sync_Proc.s.c
View File

@ -257,7 +257,7 @@ void Receiver_Sync_Proc(
if(loop_idx < 3)
{
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(dec_base_in_addr + (loop_idx+1)*30720*4),
(uint64_t)DM_TO_CSU_ADDR(nxt_in_addr),
(uint64_t)DM_TO_CSU_ADDR(nxt_in_addr+16*4),
(30720)<<2,
DMA_TAG_G2L,
0);
@ -269,8 +269,8 @@ void Receiver_Sync_Proc(
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(data_out_addr),
(uint64_t)(dec_base_out_addr + loop_idx*(30720*4/2)),
(30720)<<2>>1,
(uint64_t)(dec_base_out_addr + loop_idx*(30720*2)),
(30720)<<1,
DMA_TAG_L2G,
0);
}

4
APELib/Receiver_sync_first/inc/receiver_sync_first_macro.h
View File

@ -15,8 +15,8 @@
//=======================================================================
//微码配置空间长度定义，单位为word(4Byte)
#define RECEIVER_SYNC_FIRST_ConfigByteCopy_CFG1_LENGTH (0x0030)
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelation_CFG2_LENGTH (0x00a0)
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0080)
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelation_CFG2_LENGTH (0x0070)
#define RECEIVER_SYNC_FIRST_ConfigSlidingCorrelationSecond_CFG3_LENGTH (0x0070)
#define RECEIVER_SYNC_FIRST_ConfigSyncVer_CFG4_LENGTH (0x00a0)
//SPU查找表各字段长度定义,单位为word(4Byte)

24
APELib/Receiver_sync_first/src/receiver_Sync_First_Proc.s.c
View File

@ -191,17 +191,17 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
#ifndef RECV_DBG_DATA_TEST
if( 1 == (slot & 0x01) )
{
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
}
else
{
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
}
#else
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR;
src_addr0 = (uint32_t)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
src_addr1 = (uint32_t)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
#endif
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0),
@ -291,13 +291,13 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 13, maxsum);
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 14, receiver_sync_first_temp_dm3_ptr[2]);
TRACE(TRACE_RECEIVER_SYNC_FIRST_ADDR, 15, receiver_sync_first_temp_dm3_ptr[3]);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + (sample_per_csu<<2)),
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(src_addr0 + ((sample_per_csu-1024)<<2)),
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_first_temp_dm0_ptr),//
(61440 - sample_per_csu)<<2,
(61440 - sample_per_csu+1024)<<2,
DMA_TAG_G2L,
0);
ape_csu_dma_1D_G2L_ch2ch3_transfer((uint64_t)(src_addr1),
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_first_temp_dm0_ptr + (61440 - sample_per_csu)),//
(uint64_t)DM_TO_CSU_ADDR(receiver_sync_first_temp_dm0_ptr + (61440 - sample_per_csu+1024)),//
(2048)<<2,
DMA_TAG_G2L,
0);
@ -310,7 +310,7 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
ByteCopy((int)cfg_addr,
MPU_ADDR(receiver_sync_first_temp_dm0_ptr + 1024),//数据之间相差1024
MPU_ADDR(receiver_sync_first_temp_dm1_ptr),
((sample_per_csu)<<2));
((sample_per_csu+1024)<<2));
WAIT_MPU_STOP;
@ -367,11 +367,7 @@ void Receiver_First_Sync_Proc(receiver_sync2first_sync_t* msg_ptr, uint32_t msg_
//执行完成，更新状态机
if(SYNC_OK == ret)
{
#ifndef CLOSE_AI_PROCECING
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_AI_PROCECING);
#else
STORE_EX_W(&g_receiver_sync_status_SM_ptr->sync_status , SYNC_TRACKING);
#endif
__ucps2_synch(0);
}
else

1
APELib/Transmitter/inc/transmitter_func.h
View File

@ -27,6 +27,7 @@
#include "Modulation.h"
#include "Transform.h"
#include "ByteCopy.h"
#include "InterpolationLTE_2nd.h"
//微码配置空间偏移结构体

8
APELib/Transmitter/inc/transmitter_macro.h
View File

@ -29,11 +29,13 @@
#define TRANSMITTER_TransformConfig_2_CFG1_LENGTH (0x0060)
#define TRANSMITTER_TransformConfig_4_CFG2_LENGTH (0x0080)
#define TRANSMITTER_TransformConfig_8_CFG3_LENGTH (0x00C0)
#define TRANSMITTER_ConfigByteCopy_CFG1_LENGTH (0x0030)
#define TRANSMITTER_ConfigByteCopy_CFG1_LENGTH (0x0030)
#define TRANSMITTER_InterpolationLTE_2nd_CFG1_LENGTH (0x00D0)
//SPU查找表各字段长度定义,单位为word(4Byte)
#define TRANSMITTER_CalBG1HMatrix_LUT1_LENGTH (0x0448)
#define TRANSMITTER_CalBG2HMatrix_LUT2_LENGTH (0x0280)
#define TRANSMITTER_Pilot_Data_LENGTH (0x0400)
#define TRANSMITTER_Pilot_Data_LENGTH (0x0400)
#define TRANSMITTER_InterpolationLTE_2nd_LUT_LENGTH (0x000E)
//6006
//=======================================================================
#endif

8
APELib/Transmitter/inc/transmitter_struct.h
View File

@ -34,6 +34,9 @@ typedef struct transmitter_table_param_s
uint32_t TransformConfig_4_CFG2_Offset;
uint32_t TransformConfig_8_CFG3_Offset;
uint32_t ConfigByteCopy_CFG1_Offset;
uint32_t InterpolationLTE_2nd_CFG1_Offset;
// 存储微码参数表的ddr基地址和长度
uint32_t transmitter_config0_ddr_ptr;//transmitter DM0微码配置文件ddr地址
uint32_t transmitter_config0_length;//transmitter DM0微码配置文件ddr长度
@ -48,9 +51,10 @@ typedef struct transmitter_table_param_s
uint32_t CalBG1HMatrix_LUT1_Offset;
uint32_t CalBG2HMatrix_LUT2_Offset;
uint32_t Pilot_Data_Offset;
uint32_t InterpolationLTE_2nd_LUT_Offset;
// SPU LUT SM基地址和长度
uint32_t pucch_lut_sm_ptr; //PUCCH查找表在SM中的基地址
uint32_t pucch_lut_length; //PUCCH查找表总长度
//uint32_t transmitter_config0_ddr_ptr; //PUCCH查找表在SM中的基地址
//uint32_t transmitter_lut_length; //PUCCH查找表总长度
} transmitter_table_param_t;

2
APELib/Transmitter/src/transmitter_Init.s.c
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@ -47,6 +47,8 @@ void Transmitter_Init()
g_transmitter_table_param.Pilot_Data_Offset = g_transmitter_table_param.TransformConfig_8_CFG3_Offset + TRANSMITTER_TransformConfig_8_CFG3_LENGTH;
g_transmitter_table_param.ConfigByteCopy_CFG1_Offset = g_transmitter_table_param.Pilot_Data_Offset + TRANSMITTER_Pilot_Data_LENGTH;
g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset = g_transmitter_table_param.ConfigByteCopy_CFG1_Offset + TRANSMITTER_ConfigByteCopy_CFG1_LENGTH;
g_transmitter_table_param.InterpolationLTE_2nd_LUT_Offset = g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset + TRANSMITTER_InterpolationLTE_2nd_CFG1_LENGTH;
//DM2
//DM3

135
APELib/Transmitter/src/transmitter_Proc.s.c
View File

@ -56,9 +56,12 @@ void Transmitter_Proc(
uint32_t source_bit_ddr_ptr;// 配置地址指针
uint32_t source_bit_length;// 源比特数据的长度（单位：bytes）
int32_t *output_data_ptr;// 最终输出数据地址(dm)
uint32_t output_data_ptr_ddr_even = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR;// 最终输出数据地址(ddr)
uint32_t output_data_ptr_ddr_odd = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR;// 最终输出数据地址(ddr)
uint32_t output_data_ptr_ddr_even = TRANSMITTER_BEFORE_INTERP_EVEN;//
uint32_t output_data_ptr_ddr_odd = TRANSMITTER_BEFORE_INTERP_ODD;//
uint32_t output_final_data_ptr_ddr_even = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR;//
uint32_t output_final_data_ptr_ddr_odd = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR;//
uint32_t output_data_ptr_ddr;
uint32_t output_final_data_ptr;
uint32_t mpu_temp_dm0_ptr;
uint32_t mpu_temp_dm1_ptr;
uint32_t mpu_temp_dm2_ptr;
@ -342,7 +345,11 @@ void Transmitter_Proc(
);
temp_16QAMOUT_SM_addr = temp_16QAMOUT_SM_addr + after_16QAM_bit_len/8;
}
int32_t *cfg_addr1 = (int32_t *)transmitter_config_dm1_ptr + g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset;
uint32_t *FIR_LUT1 = (int32_t *) transmitter_config_dm1_ptr + g_transmitter_table_param.InterpolationLTE_2nd_LUT_Offset;
//LOG_ERROR_S("cfg_addr:%d %d %d FIR_LUT: \n", cfg_addr1 , g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset , FIR_LUT1);
//LOG_ERROR_S(":%d %d %d %d\n", *cfg_addr1 ,* (cfg_addr1+1), * (cfg_addr1+2),*FIR_LUT1);
// Transform--------------------------------------------------------------------------------------------------------------------------------------------------------------
uint32_t InputAddr_Trans,OutputAddr_Trans;
@ -382,9 +389,12 @@ void Transmitter_Proc(
WAIT_MPU_STOP;
// TODO 03
if(cur_slot % 2 == 0)
output_data_ptr_ddr = output_data_ptr_ddr_even; // output_data_ptr_ddr = output_data_ptr_ddr_odd;
output_data_ptr_ddr = output_data_ptr_ddr_odd; // output_data_ptr_ddr = output_data_ptr_ddr_odd;
else
output_data_ptr_ddr = output_data_ptr_ddr_odd; // output_data_ptr_ddr = output_data_ptr_ddr_even;
output_data_ptr_ddr = output_data_ptr_ddr_even; // output_data_ptr_ddr = output_data_ptr_ddr_even;
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(mpu_temp_dm3_ptr),//uint64_t addrSrc
(uint64_t)(output_data_ptr_ddr),//uint64_t addrDst
@ -468,6 +478,8 @@ void Transmitter_Proc(
TransTemp = mpu_temp_dm3_ptr;//DM3
OutputAddr_Trans = mpu_temp_dm2_ptr;//DM2
for(int iBlk = 0; iBlk < 7; iBlk++){
//read data from SM
//*********Important:import data 'TransTemp' to DM at here
@ -484,7 +496,7 @@ void Transmitter_Proc(
SVRReg[0] = MPU_ADDR(cfg_addr);
Transform4Asm(SVRReg);
WAIT_MPU_STOP;
TRACE(TRACE_TRANSMITTER_ADDR, 3, 700+iBlk);
// TRACE(TRACE_TRANSMITTER_ADDR, 3, 700+iBlk);
//*********Important:import data 'OutData' to RM-DDR at here 直接先搬到射频模块DDR预定位置
//由于OutputAddr_Trans每次有两组4096，因此按照下面方式传输
@ -598,12 +610,121 @@ void Transmitter_Proc(
//'OutData' size is 2*4096 point equals to 2*4096*32bit
}
//**********************pilot trans**********************
//发送数据后更新递推
//LOG_ERROR_S("dt %d %d %d %d %d %d\n", cur_sfn, cur_slot, g_thita1_val, g_thita2_val, g_thita34_val, GET_CNT_VAL(0));
transform_para_update(1);
//transform_para_update(1);
if(cur_slot % 2 == 0)
output_final_data_ptr = output_final_data_ptr_ddr_even; // output_data_ptr_ddr = output_data_ptr_ddr_odd;
else
output_final_data_ptr = output_final_data_ptr_ddr_odd; // output_data_ptr_ddr = output_data_ptr_ddr_even;
cfg_addr = (int32_t *)transmitter_config_dm1_ptr + g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset;
uint32_t *FIR_LUT = (int32_t *) transmitter_config_dm1_ptr + g_transmitter_table_param.InterpolationLTE_2nd_LUT_Offset;
//LOG_ERROR_S("cfg_addr:%d %d %d FIR_LUT: \n", cfg_addr , g_transmitter_table_param.InterpolationLTE_2nd_CFG1_Offset , FIR_LUT);
//LOG_ERROR_S(":%d %d %d %d\n", *cfg_addr ,* (cfg_addr+1), * (cfg_addr+2),*FIR_LUT);
int32_t *InputAddr0 = mpu_temp_dm0_ptr;
int32_t *InputAddr1 = mpu_temp_dm1_ptr;
int32_t *OutputAddr0 = mpu_temp_dm2_ptr;
int32_t *OutputAddr1 = mpu_temp_dm3_ptr;
int length = 15360+13;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
memset(InputAddr0,0,24);
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(output_data_ptr_ddr),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(InputAddr0+6),//uint64_t addrDst
15367*4,//uint32_t dataLen
DMA_TAG_G2L,//uint8_t tag
1//uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(output_data_ptr_ddr+15354*4),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(InputAddr1),//uint64_t addrDst
15373*4,//uint32_t dataLen
DMA_TAG_G2L,//uint8_t tag
1//uint8_t isWait
);
InterpolationLTE_2nd((int)cfg_addr,
MPU_ADDR(InputAddr0),
MPU_ADDR(InputAddr1),
MPU_ADDR(OutputAddr0),
MPU_ADDR(OutputAddr1),
MPU_ADDR(FIR_LUT),
15373,
2);
SVRReg[0] = MPU_ADDR(cfg_addr);
InterpolationLTE_2ndAsm(SVRReg);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_L2G, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(OutputAddr0),//uint64_t addrSrc
(uint64_t)(output_final_data_ptr),//uint64_t addrDst
30720*4,//uint32_t dataLen
DMA_TAG_L2G,//uint8_t tag
1//uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_L2G, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(OutputAddr1),//uint64_t addrSrc
(uint64_t)(output_final_data_ptr+30720*4),//uint64_t addrDst
30720*4,//uint32_t dataLen
DMA_TAG_L2G,//uint8_t tag
1//uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(output_data_ptr_ddr+30714*4),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(InputAddr0),//uint64_t addrDst
15373*4,//uint32_t dataLen
DMA_TAG_G2L,//uint8_t tag
1//uint8_t isWait
);
memset(InputAddr1+15366,0,28);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(output_data_ptr_ddr+46074*4),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(InputAddr1),//uint64_t addrDst
15366*4,//uint32_t dataLen
DMA_TAG_G2L,//uint8_t tag
1//uint8_t isWait
);
InterpolationLTE_2nd((int)cfg_addr,
MPU_ADDR(InputAddr0),
MPU_ADDR(InputAddr1),
MPU_ADDR(OutputAddr0),
MPU_ADDR(OutputAddr1),
MPU_ADDR(FIR_LUT),
15373,
2);
SVRReg[0] = MPU_ADDR(cfg_addr);
InterpolationLTE_2ndAsm(SVRReg);
WAIT_MPU_STOP;
ape_csu_task_lookup(DMA_TAG_L2G, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(OutputAddr0),//uint64_t addrSrc
(uint64_t)(output_final_data_ptr+61440*4),//uint64_t addrDst
30720*4,//uint32_t dataLen
DMA_TAG_L2G,//uint8_t tag
1//uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_L2G, 1);
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(OutputAddr1),//uint64_t addrSrc
(uint64_t)(output_final_data_ptr+92160*4),//uint64_t addrDst
30720*4,//uint32_t dataLen
DMA_TAG_L2G,//uint8_t tag
1//uint8_t isWait
);
return;
}

11
APELib/Transmitter/src/transmitter_Task.s.c
View File

@ -62,12 +62,13 @@ void Transmitter_Task()
TRACE(TRACE_TRANSMITTER_ADDR, 3, 0x990);
return;
}
int rr3 = getMemoryMalloced(APE_DM0);
TRACE(TRACE_TRANSMITTER_ADDR, 6, rr3);
//DM0第三段，堆空间
transmitter_temp_dm0_ptr = (int32_t *)ADDR_ALIGN(transmitter_malloc_dm0_ptr, 12);//起始地址4k对齐
int rr3 = getMemoryMalloced(APE_DM3);
TRACE(TRACE_TRANSMITTER_ADDR, 6, rr3);
//3. DM3空间申请
transmitter_malloc_dm3_ptr = dmemalign_unit(0x4000, 160*1024, APE_DM3);//申请了224KiB 首地址16k对齐
//若空间申请失败，则释放已申请的空间，再退出任务
@ -106,12 +107,16 @@ void Transmitter_Task()
DMA_TAG_G2L,
0);
}
//LOG_ERROR_S("config_length: %d\n", g_transmitter_table_param.transmitter_config1_length);
//LOG_ERROR_S(":%d %d %d %d\n", *cfg_addr1 ,* (cfg_addr1+1), * (cfg_addr1+2),*FIR_LUT1);
//DM1第二段，堆空间
transmitter_temp_dm1_ptr = (int32_t *)ADDR_ALIGN(transmitter_config_dm1_ptr + \
g_transmitter_table_param.transmitter_config1_length, 12); //起始地址4k对齐
//5. DM2空间申请
transmitter_malloc_dm2_ptr = dmemalign_unit(0x4000, 128*1024, APE_DM2);//申请了224KiB 首地址16k对齐
transmitter_malloc_dm2_ptr = dmemalign_unit(0x4000, 192*1024, APE_DM2);//申请了224KiB 首地址16k对齐
//若空间申请失败，释放已申请的空间，再退出任务
if (NULLPTR == transmitter_malloc_dm2_ptr)
{

58
Common/inc/mem_def.h
View File

@ -68,24 +68,43 @@
#endif
/************************************SM2--1.5M***********************************************/
#define TRANSMITTER_OUT (SM2_BASE) //4k对齐
//#define TRANSMITTER_BEFORE_INTERP_EVEN (SM2_BASE+TIME_DATA_SLOT_LEN)
//#define TRANSMITTER_BEFORE_INTERP_ODD (TRANSMITTER_BEFORE_INTERP_EVEN+TIME_DATA_SLOT_LEN)
#define TRANSMITTER_BEFORE_INTERP_EVEN (0x70300000)
#define TRANSMITTER_BEFORE_INTERP_ODD (0x70400000)
/************************************SM3--1.5M***********************************************/
#define SM3_PHY_MSG_BUFFER_ADDR (SM3_BASE)
#define SM3_PHY_TASKS_MGR_ADDR (SM3_PHY_MSG_BUFFER_ADDR + SM3_PHY_MSG_BUFFER_LEN)
#define RECEIVER_OUT3 (SM3_BASE + 0x4000)
/************************************SM4--1.5M***********************************************/
#define RECEIVER_BASE (SM4_BASE) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE)
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_BASE (0x71000000) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)//0x0a278000
#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)//0xa2b4000
#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
/*
#define RECEIVER_BASE (SM4_BASE) //4k对齐
#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)//0x0a278000
#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)//0xa2b4000
#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
*/
/************************************SM5--1.5M***********************************************/
//SM5前面区域被占用
#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t)
#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (SM5_BASE)
//#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t)
#ifdef CORE_ODD
#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN)
#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN)
@ -101,22 +120,23 @@
//接收端数据来源选择
//---------------TX RX JESD地址接口---------------------------------------------------------
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
//#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
//#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (SM4_BASE) //0x1E0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (SM4_BASE+0x78000) //0x1E0000
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000)
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000)
#ifdef TX_RX_LOOP
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR) //TODO:需要修改成TX的61440对应buffer
#define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR) //TODO:需要修改成TX的61440对应buffer
#elif !defined(TX_RX_LOOP) && !defined(RECV_DBG_DATA_TEST)
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR)
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR)
#else
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000)
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000)
#endif
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (0x70000000) //!!!DDR_PHY_BASE 0x1E0000
#define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (0x70200000) // 0x1E0000
#else
//---------------RECV测试用DDR空间--------------------------------------
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (0x88800000) //61440*4
#define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (0x8883c000) //
#endif
#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR (0x6BFC0000) // 61440*4 用于暂存数据供first_sync处理
#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理
//---------------APE4 RECV START FIRSTSYNC FLAG---------------------------------------------

2
Common/inc/test_macro.h
View File

@ -8,7 +8,7 @@
//#define RECV_SYMB_DBG_DATA_TEST
/*RX数据输入直接从TX Buffer读入，数据环回开关*/
#define TX_RX_LOOP
//#define TX_RX_LOOP
/*Transmit加载Trans.dat作为输入数据*/
#define TRANS_DBG_DATA_TEST

57344
Config/EquIn_Quan.dat
View File

File diff suppressed because it is too large Load Diff

130
Config/Receiver_Sync_First_cfg_dm0.dat
View File

@ -130,22 +130,6 @@
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
@ -174,38 +158,6 @@
0x00000000,
0x00000000,
0x00000000,
0x02434241,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x02424140,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000200,
0x00000207,
0x00000207,
@ -226,6 +178,38 @@
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
@ -270,23 +254,7 @@
0x0000000e,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
0x00000295,
0x00000400,
0x00000400,
0x00007a00,
0x00000000,
@ -302,38 +270,6 @@
0x00000000,
0x00000000,
0x00000000,
0x02434241,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x02424140,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000200,
0x00000207,
0x00000207,

32
Config/Receiver_Sync_cfg_dm1.dat
View File

@ -1,17 +1,17 @@
0x7fff7fff,
0xfffafffa,
0x00280028,
0xff5fff5f,
0x01dd01dd,
0xfb62fb62,
0x0a440a44,
0xe8f2e8f2,
0x50065006,
0x50065006,
0xe8f2e8f2,
0x0a440a44,
0xfb62fb62,
0x01dd01dd,
0xff5fff5f,
0x00280028,
0xfffafffa,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

222
Config/Transmitter_cfg_dm1.dat
View File

@ -5526,3 +5526,225 @@
0x004000ce,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x01010000,
0x21212020,
0x03030202,
0x23232222,
0x05050404,
0x25252424,
0x07070606,
0x27272626,
0x09090808,
0x29292828,
0x0b0b0a0a,
0x2b2b2a2a,
0x0d0d0c0c,
0x2d2d2c2c,
0x0f0f0e0e,
0x2f2f2e2e,
0x01010000,
0x03030202,
0x05050404,
0x07070606,
0x09090808,
0x0b0b0a0a,
0x0d0d0c0c,
0x0f0f0e0e,
0x11111010,
0x13131212,
0x15151414,
0x17171616,
0x19191818,
0x1b1b1a1a,
0x1d1d1c1c,
0x1f1f1e1e,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x00000016,
0x0000ff93,
0x00000153,
0x0000fcaf,
0x00000757,
0x0000ef9f,
0x5a82389e,
0x0000389e,
0x0000ef9f,
0x00000757,
0x0000fcaf,
0x00000153,
0x0000ff93,
0x00000016,

4096
Config/channel_est_1_Quan.dat
View File

File diff suppressed because it is too large Load Diff

BIN
Lib/OspLib/libape_spu.a
View File

Binary file not shown.

BIN
Lib/OspLib/libecs_rfm_spu0.a
View File

Binary file not shown.

64
MicroCode/InterpolationLTE_2nd/inc/Ant0DataIn.dat Normal file
View File

@ -0,0 +1,64 @@
0x03690c8b,
0x086010f0,
0x0be71007,
0x0bb909d0,
0x07050162,
0xff69fad3,
0xf86bf896,
0xf5b0fa27,
0xf8ddfcca,
0x0093fdbf,
0x0925fc58,
0x0e9ffa67,
0x0edbfacd,
0x0a73ff3c,
0x040d06bc,
0xfeb00e0a,
0xfc3b117c,
0xfccd0f49,
0xff450899,
0x023300db,
0x0482fbd8,
0x05a0fbac,
0x0545ffd9,
0x036505cc,
0x00550a5f,
0xfd040b6e,
0xfaca08b5,
0xfabc03ac,
0xfce3fea2,
0xfffefb9f,
0x022afb7d,
0x0225fd98,
0x00410031,
0xfe5d015c,
0xfeb50010,
0x0254fce7,
0x0832f9f5,
0x0dacf9b9,
0x1019fd8e,
0x0e620486,
0x098e0b7d,
0x03fd0e91,
0xffda0b5a,
0xfe050296,
0xfe00f829,
0xfed2f143,
0xfff7f19d,
0x0184f967,
0x038a051a,
0x05420f58,
0x051813c0,
0x01c11115,
0xfbad098b,
0xf589012f,
0xf324fb7c,
0xf70ef99d,
0x0080fa47,
0x0b24fb14,
0x1122fa58,
0x0e70f83d,
0x0359f685,
0xf486f748,
0xe884fb72,
0xe435020f,

102
MicroCode/InterpolationLTE_2nd/inc/Ant0DataOutput.dat Normal file
View File

@ -0,0 +1,102 @@
0xfaa3fac1,
0xf92cfb13,
0xf8b5fbdd,
0xf951fcd8,
0xfaf4fdba,
0xfd6afe4b,
0x0067fe68,
0x038cfe13,
0x0677fd6a,
0x08d0fca5,
0x0a56fc0a,
0x0ae7fbdc,
0x0a81fc52,
0x0942fd87,
0x0763ff75,
0x052801f4,
0x02dd04c3,
0x00c30789,
0xff1209ed,
0xfde90b9c,
0xfd550c5c,
0xfd4d0c15,
0xfdbc0ace,
0xfe8108b6,
0xff7b0614,
0x00890340,
0x018e009a,
0x0275fe74,
0x032ffd0f,
0x03b4fc8c,
0x03fafcf0,
0x03fdfe1e,
0x03b9ffe4,
0x033101fb,
0x02660419,
0x016405f5,
0x003c0755,
0xff070810,
0xfde30814,
0xfcf20769,
0xfc500628,
0xfc14047b,
0xfc460298,
0xfce100b6,
0xfdccff08,
0xfee5fdb9,
0xfffefce7,
0x00ecfc9b,
0x0187fccf,
0x01bbfd6b,
0x0184fe4c,
0x00f3ff43,
0x002d0022,
0xff6700be,
0xfed700f6,
0xfeb000b9,
0xff15000b,
0x0015ff04,
0x01a5fdcf,
0x039ffca2,
0x05cbfbba,
0x07e5fb4f,
0x09aafb8f,
0x0ae0fc8d,
0x0b61fe45,
0x0b210091,
0x0a2b0332,
0x08a405d6,
0x06c1081f,
0x04bd09b4,
0x02d10a4c,
0x012a09bf,
0xffe50806,
0xff0b054a,
0xfe9901d4,
0xfe79fe0f,
0xfe95fa74,
0xfed5f77e,
0xff2af594,
0xff8bf4fb,
0xfff9f5d3,
0x0079f806,
0x0112fb55,
0x01c3ff5a,
0x0280039b,
0x03330797,
0x03b70ad9,
0x03e70d0a,
0x039a0df7,
0x02b80d99,
0x013d0c14,
0xff3f09ac,
0xfcf106bf,
0xfa9b03ae,
0xf89900d6,
0xf743fe7c,
0xf6e8fcce,
0xf7b3fbd4,
0xf9acfb7b,
0xfcaafb99,
0x005afbf4,
0x0445fc53,

64
MicroCode/InterpolationLTE_2nd/inc/Ant1DataIn.dat Normal file
View File

@ -0,0 +1,64 @@
0xf7e008b2,
0xf9940852,
0xfce308a0,
0x009b092f,
0x032d08b0,
0x035a063c,
0x00e70262,
0xfce9ff12,
0xf96bfe46,
0xf878006e,
0xfae803ce,
0xffb7057b,
0x04610353,
0x0634fd94,
0x03eef6df,
0xfe99f29c,
0xf922f2db,
0xf6a8f731,
0xf89dfd36,
0xfdc30252,
0x02de055e,
0x049b070d,
0x01aa08d9,
0xfb9c0b6b,
0xf5fe0dd3,
0xf4310e23,
0xf74f0afb,
0xfd7104ce,
0x02d6fde8,
0x0428f920,
0x0091f822,
0xfa49fa8f,
0xf54ffe7b,
0xf51401e5,
0xfa7e03fa,
0x03700547,
0x0c0906d1,
0x10d208e4,
0x108e0a90,
0x0caa0a41,
0x082506fb,
0x05b90144,
0x0655fafc,
0x08c1f653,
0x0a7ef49a,
0x0954f5c9,
0x04a1f8ee,
0xfdb0fcfa,
0xf7070145,
0xf31a055b,
0xf31f086e,
0xf6a1092e,
0xfbe60668,
0x00f10027,
0x0478f860,
0x0655f25b,
0x0732f0fd,
0x07caf4de,
0x0821fba3,
0x07600136,
0x0461023f,
0xfeaffe4d,
0xf755f83b,
0xf0d1f45f,

102
MicroCode/InterpolationLTE_2nd/inc/Ant1DataOutput.dat Normal file
View File

@ -0,0 +1,102 @@
0x00a301af,
0xff48005d,
0xfdd0ff57,
0xfc6ffec8,
0xfb58fec7,
0xfab7ff52,
0xfaac004d,
0xfb3f0183,
0xfc6502b0,
0xfdfb038e,
0xffcc03e0,
0x0197037d,
0x03180259,
0x0415008d,
0x0462fe49,
0x03f0fbd8,
0x02c7f98b,
0x010ef7b1,
0xff02f688,
0xfceff632,
0xfb24f6b4,
0xf9e5f7f6,
0xf964f9c5,
0xf9b3fbe1,
0xfac6fe07,
0xfc70ffff,
0xfe6a01a4,
0x006402e5,
0x020703cb,
0x030b0471,
0x034104fc,
0x029b058e,
0x012d0641,
0xff2c071c,
0xfce50812,
0xfab20904,
0xf8ec09c6,
0xf7d90a27,
0xf7a609fe,
0xf85a0933,
0xf9da07c3,
0xfbe805c4,
0xfe300365,
0x005700e3,
0x0201fe84,
0x02ecfc89,
0x02f0fb23,
0x020dfa6f,
0x0066fa6f,
0xfe40fb0f,
0xfbf5fc27,
0xf9e7fd81,
0xf870feec,
0xf7d8003d,
0xf8460156,
0xf9bd022f,
0xfc1a02cf,
0xff1d034a,
0x026e03bb,
0x05ad0438,
0x088204d1,
0x0aa30586,
0x0be40649,
0x0c3906fb,
0x0bb40777,
0x0a870799,
0x08f40740,
0x0745065c,
0x05c204ef,
0x04a20310,
0x040b00e5,
0x0403fe9f,
0x047afc74,
0x0545fa95,
0x0630f928,
0x06faf845,
0x076bf7f0,
0x0753f822,
0x0698f8c6,
0x0538f9c4,
0x0345fb00,
0x00eafc63,
0xfe5dfddc,
0xfbddff60,
0xf9a700e5,
0xf7f10263,
0xf6e103c9,
0xf6870504,
0xf6e405f5,
0xf7e3067e,
0xf95f067d,
0xfb2c05d9,
0xfd190487,
0xfefa0292,
0x00aa001b,
0x0212fd5b,
0x0328fa9b,
0x03f1f82b,
0x047af65a,
0x04d4f561,
0x0516f562,
0x054df65a,

208
MicroCode/InterpolationLTE_2nd/inc/Config_InterpolationLTE_2nd.dat Normal file
View File

@ -0,0 +1,208 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x00400006,
0x00000000,
0x00000000,
0x01010000,
0x21212020,
0x03030202,
0x23232222,
0x05050404,
0x25252424,
0x07070606,
0x27272626,
0x09090808,
0x29292828,
0x0b0b0a0a,
0x2b2b2a2a,
0x0d0d0c0c,
0x2d2d2c2c,
0x0f0f0e0e,
0x2f2f2e2e,
0x01010000,
0x03030202,
0x05050404,
0x07070606,
0x09090808,
0x0b0b0a0a,
0x0d0d0c0c,
0x0f0f0e0e,
0x11111010,
0x13131212,
0x15151414,
0x17171616,
0x19191818,
0x1b1b1a1a,
0x1d1d1c1c,
0x1f1f1e1e,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,
0x000e0111,
0x00000000,

14
MicroCode/InterpolationLTE_2nd/inc/InterpolationLTE_2nd.h Normal file
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@ -0,0 +1,14 @@
#ifndef INTERPOLATIONLTE_2ND_H_
#define INTERPOLATIONLTE_2ND_H_
MPU_ENTRY void InterpolationLTE_2ndAsm(v16u32 src);
void InterpolationLTE_2nd(int ConfigBaseAddr,
int InputAddr0,
int InputAddr1,
int OutputAddr0,
int OutputAddr1,
int LUTAddr,
int Length,
int AntNum);
#endif /* INTERPOLATIONLTE_2ND_H_ */

14
MicroCode/InterpolationLTE_2nd/inc/hbfir2_fixed.dat Normal file
View File

@ -0,0 +1,14 @@
0x00000016,
0x0000ff93,
0x00000153,
0x0000fcaf,
0x00000757,
0x0000ef9f,
0x5a82389e,
0x0000389e,
0x0000ef9f,
0x00000757,
0x0000fcaf,
0x00000153,
0x0000ff93,
0x00000016,

67
MicroCode/InterpolationLTE_2nd/src/mpu0/InterpolationLTE_2ndAsm.m0.asm Normal file
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@ -0,0 +1,67 @@
.section .text.m0, "ax"
.ifdef enable_dynamic_mim
.include "InterpolationLTE.inc"
.endif
.file "InterpolationLTE_2ndAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global InterpolationLTE_2ndAsm
InterpolationLTE_2ndAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0];
BIU1:Load(T0)(A++) -> M[1];
BIU1:Load(T0)(A++) -> M[2];
BIU1:Load(T0)(A++) -> M[3];
BIU1:Load(T0)(A++) -> M[4];
BIU1:Load(T0)(A++) -> M[5];
BIU1:Load(T0)(A++) -> M[6];
BIU1:Load(T0)(A++) -> M[7];
BIU1:Load(T0)(A++) -> M[8];
BIU1:Load(T0)(A++) -> M[9] || R5:PreConfig(M[0]);
BIU1:Load(T0)(A++) -> M[10] || R5:WriteConf(Mfetch)-> KI[0-15] || R2:M[1]->BIU2.T1;
BIU1:Load(T0)(A++) -> M[11] || R0:M[2]->BIU0.T0;
BIU1:Load(T0)(A++) -> M[12] || R0:M[3]->BIU0.T1;
R0:M[4]->BIU0.T2;
R1:M[5]->BIU1.T0 || BIU2:Load(T1)->SHU0.T0;
R1:M[6]->BIU1.T1;
R1:M[7]->BIU1.T2;
R2:M[8]->BIU2.T2;
R3:M[9]->BIU3.T2;
IMA0:V(0x0d0d)->SHU0.T1 || R3:M[10]->SHU3.T5 || R2:M[10]->SHU2.T5 || R1:M[10]->SHU1.T5 || R0:M[10]->SHU0.T5;
IMA0:V(0)->SHU0.T2 || R0:M[11]->SHU0.T4 || R1:M[11]->SHU1.T4 || R2:M[11]->SHU2.T4 || R3:M[11]->SHU3.T4;
R1:PreConfig(M[12]) || R3:PreConfig(M[12]) || IMA0:V(0)->IMA0.T5 || IMA1:V(0)->IMA1.T5 || IMA2:V(0)->IMA2.T5 || IMA3:V(0)->IMA3.T5;
R1:WriteConf->MC.WALL(I) || R3:WriteConf->MC.WALL(I);
R3:WriteConf->MC.RALL(I) || IMA0:SetShiftMode(T5)->ShiftMode0 || IMA1:SetShiftMode(T5)->ShiftMode0 || IMA2:SetShiftMode(T5)->ShiftMode0 || IMA3:SetShiftMode(T5)->ShiftMode0;
R1:WriteConf->MC.RALL(I);
SHU0:Index(T0,T0,T1)->M[16];
SHU0:Index(T0,T0,T2)(T7=T2+V(2))->M[I++,A++] || R0:M[16]->IMA0.T3 || R1:M[16]->IMA1.T3 || R2:M[16]->IMA2.T3 || R3:M[16]->IMA3.T3;
SHU0:Index(T0,T0,T7)(T7=T7+V(2))->M[I++,A++] || MFetch:Repeat @(13);
BIU0:Wait 0 || SHU3:Wait 11 || R0:Wait 10 || IMA0:Wait 12 || SHU2:Wait 14 || R1:Wait 13 || IMA1:Wait 15 || BIU2:Wait 33 || BIU1:Wait 0 || SHU1:Wait 11 || R2:Wait 10 || IMA2:Wait 12 || SHU0:Wait 14 || R3:Wait 13 || IMA3:Wait 15 || BIU3:Wait 33;
MFetch:LPTO %Filter @(KI0);
BIU0:Load(T0)(A++)(Mask)->SHU3.T0 || SHU3:Index(T1,T0,T4)(T7=T4+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:0+T2*T3(ShiftMode0)(S)(SSS)->SHU3.T2 || SHU2:Index(T1,T0,T4)(T7=T4+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:0+T2*T3(ShiftMode0)(S)(SSS)->SHU2.T2 || BIU2:Store(T0,T2)(Mask)(A++) || BIU1:Load(T0)(A++)(Mask)->SHU1.T0 || SHU1:Index(T1,T0,T4)(T7=T4+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:0+T2*T3(ShiftMode0)(S)(SSS)->SHU1.T2 || SHU0:Index(T1,T0,T4)(T7=T4+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:0+T2*T3(ShiftMode0)(S)(SSS)->SHU0.T2 || BIU3:Store(T0,T2)(Mask)(A++);
BIU0:Load(T1)(A++)(Mask)->SHU3.T1 || SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:0+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:0+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || BIU2:Store(T0,T2)(Mask)(A++) || BIU1:Load(T1)(A++)(Mask)->SHU1.T1 || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:0+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:0+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR || BIU3:Store(T0,T2)(Mask)(A++);
BIU0:Load(T2)(A++)(Mask)->IMA0.T2 || SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || BIU1:Load(T2)(A++)(Mask)->IMA2.T2 || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
BIU0:Load(T0)(A++)(Mask)->SHU2.T0 || SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || BIU2:Store(T0,T2)(Mask)(A++) || BIU1:Load(T0)(A++)(Mask)->SHU0.T0 || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR || BIU3:Store(T0,T2)(Mask)(A++);
BIU0:Load(T1)(A++)(Mask)->SHU2.T1 || SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || BIU2:Store(T0,T2)(Mask)(A++) || BIU1:Load(T1)(A++)(Mask)->SHU0.T1 || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR || BIU3:Store(T0,T2)(Mask)(A++);
BIU0:Load(T2)(A++)(Mask)->IMA1.T2 || SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || BIU1:Load(T2)(A++)(Mask)->IMA3.T2 || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
SHU3:Index(T1,T0,T7)(T7=T7+V(2))->IMA0.T0 || R0:M[I++,A++]->IMA0.T1 || IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA0.MR || SHU2:Index(T1,T0,T7)(T7=T7+V(2))->IMA1.T0 || R1:M[I++,A++]->IMA1.T1 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA1.MR || SHU1:Index(T1,T0,T7)(T7=T7+V(2))->IMA2.T0 || R2:M[I++,A++]->IMA2.T1 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA2.MR || SHU0:Index(T1,T0,T7)(T7=T7+V(2))->IMA3.T0 || R3:M[I++,A++]->IMA3.T1 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->IMA3.MR;
IMA0:MR+T0*T1(ShiftMode0)(S)(SSS)->SHU3.T3 || IMA1:MR+T0*T1(ShiftMode0)(S)(SSS)->SHU2.T3 || IMA2:MR+T0*T1(ShiftMode0)(S)(SSS)->SHU1.T3 || IMA3:MR+T0*T1(ShiftMode0)(S)(SSS)->SHU0.T3;
MFetch:Repeat @(4);
SHU3:Index(T3,T2,T5)(T7=T5+V(16))->BIU2.T0 || SHU2:Index(T3,T2,T5)(T7=T5+V(16))->BIU2.T0 || SHU1:Index(T3,T2,T5)(T7=T5+V(16))->BIU3.T0 || SHU0:Index(T3,T2,T5)(T7=T5+V(16))->BIU3.T0;
SHU3:Index(T3,T2,T7)->BIU2.T0 || SHU2:Index(T3,T2,T7)->BIU2.T0 || SHU1:Index(T3,T2,T7)->BIU3.T0 || SHU0:Index(T3,T2,T7)->BIU3.T0;
Filter:
BIU0:Wait 0 || SHU3:Wait 0 || R0:Wait 0 || IMA0:Wait 0 || SHU2:Wait 0 || R1:Wait 0 || IMA1:Wait 0 || BIU2:Wait 0 || BIU1:Wait 0 || SHU1:Wait 0 || R2:Wait 0 || IMA2:Wait 0 || SHU0:Wait 0 || R3:Wait 0 || IMA3:Wait 0 || BIU3:Wait 0;
MFetch:REPEAT @(17);
MFetch:MPU.STOP;

51
MicroCode/InterpolationLTE_2nd/src/spu/InterpolationLTE_2nd.s.c Normal file
View File

@ -0,0 +1,51 @@
void InterpolationLTE_2nd(int ConfigBaseAddr,
int InputAddr0,
int InputAddr1,
int OutputAddr0,
int OutputAddr1,
int LUTAddr,
int Length,
int AntNum)
{
volatile unsigned int *addr = (volatile unsigned int *)ConfigBaseAddr;
int cycle0 = ((Length-13)*2+63)>>6;
//0 cycle
addr[0] = cycle0;
//1 copy hbfir1_fixed
addr[16 * 1 + 0] = LUTAddr;
//2 BIU0.T0
addr[16 * 2 + 0] = InputAddr0;
addr[16 * 2 + 12] = Length * 4;
//3 BIU0.T1
addr[16 * 3 + 0] = InputAddr0 + 16 * 4;
addr[16 * 3 + 12] = Length * 4;
//4 BIU0.T2
addr[16 * 4 + 0] = InputAddr0 + 6 * 4;
addr[16 * 4 + 12] = Length * 4;
//5 BIU1.T0
addr[16 * 5 + 0] = InputAddr1;
addr[16 * 5 + 12] = AntNum > 1 ? (Length * 4) : 0;
//6 BIU1.T1
addr[16 * 6 + 0] = InputAddr1 + 16 * 4;
addr[16 * 6 + 12] = AntNum > 1 ? (Length * 4) : 0;
//7 BIU1.T2
addr[16 * 7 + 0] = InputAddr1 + 6 * 4;
addr[16 * 7 + 12] = AntNum > 1 ? (Length * 4) : 0;
//8 BIU2.T2
addr[16 * 8 + 0] = OutputAddr0;
addr[16 * 8 + 12] = (Length - 13) * 2 * 4;
//9 BIU3.T2
addr[16 * 9 + 0] = OutputAddr1;
addr[16 * 9 + 12] = AntNum > 1 ? (Length - 13) * 2 * 4 : 0;
}

64
MicroCode/InterpolationLTE_2nd/src/spu/main.s.c Normal file
View File

@ -0,0 +1,64 @@
#ifndef REMOVE_MC_TEST
#include "ucp2.h"
#include <InterpolationLTE_2nd.h>
//DM0 input data0
__DM0 int InputAddr0[30740] = {
#include <Ant0DataIn.dat>
};
//DM1 input data1
__DM1 int InputAddr1[30740] = {
#include <Ant1DataIn.dat>
};
//DM2 output data0
__DM2 int OutputAddr0[61450] = {};
//DM3 output data1
__DM3 int OutputAddr1[61450] = {};
//DM3 filter factor
__DM3 int LUTAddr[14] = {
#include <hbfir2_fixed.dat>
};
//DM3 configuration.dat
__DM3 int ConfigBaseAddr[] = {
#include <Config_InterpolationLTE_2nd.dat>
};
__DM3 v16s32 SVRReg = {
0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0,
0xffff, 0x6, 0, 0
};
int main(void)
{
volatile int a = 1;
int Length = 64;
int AntNum = 2;
InterpolationLTE_2nd((int)ConfigBaseAddr,
MPU_ADDR(InputAddr0),
MPU_ADDR(InputAddr1),
MPU_ADDR(OutputAddr0),
MPU_ADDR(OutputAddr1),
MPU_ADDR(LUTAddr),
Length,
AntNum);
SVRReg[0] = MPU_ADDR(ConfigBaseAddr);
InterpolationLTE_2ndAsm(SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
return a;
}
#endif

58
MicroCode/SlidingCorrelation/inc/ConfigSlidingCorrelation.dat
View File

@ -59,7 +59,7 @@
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0xffffffff,
0x00000000,
0x00000000,
0x003fffff,
@ -76,25 +76,7 @@
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Output2 useless
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0xffffffff,
0x00000000,
0x00000000,
0x003fffff,
@ -136,40 +118,4 @@
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//index1
0x02434241,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//index2
0x02424140,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

130
MicroCode/SlidingCorrelation/inc/ConfigSlidingCorrelationSecond.dat
View File

@ -15,44 +15,7 @@
0x00000207,
0x00000207,
0x00000207,
//InputA2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//InputB2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xf000f000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Maxdata read
//InputA
0x00000000,
0x00000000,
0x00000000,
@ -69,8 +32,59 @@
0x0000000e,
0x00000000,
0x00000000,
//InputB
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//InputA2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xffffffff,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//InputB2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000,
0x00000004,
0x00000000,
0x00000000,
0x00020002,
0xffffffff,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Maxdata write
//Maxdata
0x00000000,
0x00000000,
0x00000000,
@ -89,7 +103,7 @@
0x00000000,
//KI0
0x00000295,
0x00000400,
0x00000400,
0x00007600,
0x00000000,
@ -105,39 +119,3 @@
0x00000000,
0x00000000,
0x00000000,
//index1
0x02434241,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//index2
0x02424140,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

62464
MicroCode/SlidingCorrelation/inc/Input1_part1.dat
View File

File diff suppressed because it is too large Load Diff

64512
MicroCode/SlidingCorrelation/inc/Input1_part2.dat
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File diff suppressed because it is too large Load Diff

62464
MicroCode/SlidingCorrelation/inc/Input2_part1.dat
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File diff suppressed because it is too large Load Diff

41709
MicroCode/SlidingCorrelation/inc/Input2_part2.dat
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File diff suppressed because it is too large Load Diff

36
MicroCode/SlidingCorrelation/src/mpu0/SlidingCorrelationAsm.m0.asm
View File

@ -14,11 +14,11 @@
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
BIU1:Load(T0)(A++) -> M[3](Mode0);//InputA2
BIU1:Load(T0)(A++) -> M[4](Mode0);//InputB2
BIU1:Load(T0)(A++) -> M[5](Mode0);//useless
//BIU1:Load(T0)(A++) -> M[5](Mode0);//useless
BIU1:Load(T0)(A++) -> M[6](Mode0);//Maxdata
BIU1:Load(T0)(A++) -> M[63](Mode0);//KI0
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//index1
BIU1:Load(T0)(A++) -> SHU0.T4(Mode0);//index2
//BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//index1
//BIU1:Load(T0)(A++) -> SHU0.T4(Mode0);//index2
NOP;
NOP;
NOP;
@ -75,24 +75,6 @@ Sum_1024:
IMA3:V(1) -> IMA3.T1;
IMA3:V(0) -> IMA3.T0;
IMA1:V(0) -> IMA1.T0;
/*IMA0:ReadMR(L)-> SHU0.T1(Mode0);
IMA0:ReadMR(O1)-> SHU0.T2(Mode0);
IMA0:ReadMR(O1)-> IMA2.T2(Mode0);
R0:M[3] -> BIU0.T0(Mode0);
R3:M[4] -> BIU3.T0(Mode0);
IMA1:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA1.MR(Mode0);
IMA3:V(1) -> IMA3.T1;
IMA3:V(0) -> IMA3.T0;
IMA1:V(0) -> IMA1.T0;
SHU0:Index(T1,T0)(Mode0);
SHU0:Index(T2,T0)->IMA2.T1(Mode0);
IMA2:T2 >> 2 (W) (U) -> SHU0.T2;
NOP;
IMA2:T1 >> 2 (W) (U) -> SHU0.T1;
NOP;
NOP;
SHU0:Index(T1,T4)(Mode0);
SHU0:Index(T2,T4)->IMA1.T3(Mode0);*/
MFetch:LPTO %Slide_Win @(KI2 - 0);
BIU0:Load(T0)(A++) -> IMA0.T0(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T1(Mode0);
BIU0:Load(T0)(A++) -> IMA0.T2(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T3(Mode0);
@ -145,21 +127,11 @@ Slide_Win:
NOP;
BIU2:Store(T1,T0)(Mode0)(A++);
BIU2:Store(T2,T0)(Mode0)(A++);
BIU2:Store(T3,T0)(Mode0)(A++);
//BIU2:Store(T3,T0)(Mode0)(A++);
NOP;
NOP;
NOP;
NOP;
IMA0:ReadMR(L)-> BIU2.T1(Mode0);
IMA0:ReadMR(O1)-> BIU2.T2(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
BIU2:Store(T1,T0)(Mode0)(A++);
BIU2:Store(T2,T0)(Mode0)(A++);
NOP;
NOP;
NOP;
NOP;

66
MicroCode/SlidingCorrelation/src/mpu0/SlidingCorrelationSecondAsm.m0.asm
View File

@ -10,13 +10,13 @@
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0);
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA2
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB2
BIU1:Load(T0)(A++) -> M[3](Mode0);//Maxdata read
BIU1:Load(T0)(A++) -> M[4](Mode0);//Maxdata write
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
BIU1:Load(T0)(A++) -> M[3](Mode0);//InputA2
BIU1:Load(T0)(A++) -> M[4](Mode0);//InputB2
//BIU1:Load(T0)(A++) -> M[5](Mode0);//useless
BIU1:Load(T0)(A++) -> M[6](Mode0);//Maxdata
BIU1:Load(T0)(A++) -> M[63](Mode0);//KI0
BIU1:Load(T0)(A++) -> SHU0.T0(Mode0);//index1
BIU1:Load(T0)(A++) -> SHU0.T4(Mode0);//index2
NOP;
NOP;
NOP;
@ -25,17 +25,20 @@
R0:M[0] -> IMA0.T0(Mode0);
R0:M[1] -> BIU0.T0(Mode0) || R1:M[0] -> IMA1.T0(Mode0);
R3:M[2] -> BIU3.T0(Mode0) || R2:M[0] -> IMA2.T0(Mode0);
R2:M[3] -> BIU2.T0(Mode0) || R3:M[0] -> IMA3.T0(Mode0);
R2:M[4] -> BIU2.T1(Mode0);
R3:M[0] -> IMA3.T0(Mode0);
R5:PreConfig(M[63])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0)||IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R5:WriteConf(Mfetch)->KI[4-7](Mode0)||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0)||R2:M[6]->BIU2.T0(Mode0);
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T3(Mode0);
BIU2:Load(T0)(A++) -> IMA0.T1(Mode0);
BIU2:Load(T0)(A++) -> IMA0.T2(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
MFetch:LPTO %Sum_1024 @(KI0 - 0);
BIU0:Load(T0)(A++) -> IMA0.T1(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T2(Mode0);
NOP;
NOP;
NOP;
@ -46,11 +49,31 @@
NOP;
NOP;
NOP;
IMA0:SetMR(T1)(O1) (Mode0);
IMA0:SetMR(T2)(L) (Mode0);
IMA0: MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
NOP;
NOP;
NOP;
//IMA0:SetMR(0)(H)(Mode0);
Sum_1024:
//IMA0: MR + 0*0(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.T3(Mode0);
R0:M[3] -> BIU0.T0(Mode0);
R3:M[4] -> BIU3.T0(Mode0);
IMA0:ReadMR(L)->IMA2.T0;//real
IMA0:ReadMR(O1)->IMA2.T2;//overflow real
NOP;
NOP;
NOP;
NOP;
IMA2:T0>>10(W)(U)->T0;
NOP;
NOP;
IMA2:T2>>16(W)(U)->T2;
IMA2:Ttmp<<22(W)(T)->IMA2.T2;
IMA2:T0+Ttmp(W)(U)->IMA1.T3;
IMA3:V(1) -> IMA3.T1;
IMA3:V(0) -> IMA3.T0;
IMA1:V(0) -> IMA1.T0;
MFetch:LPTO %Slide_Win @(KI2 - 0);
BIU0:Load(T0)(A++) -> IMA0.T0(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T1(Mode0);
BIU0:Load(T0)(A++) -> IMA0.T2(Mode0)||BIU3:Load(T0)(A++) -> IMA0.T3(Mode0);
@ -94,13 +117,19 @@ Slide_Win:
NOP;
NOP;
NOP;
IMA1:T0 -> BIU2.T2;
IMA1:T3 -> BIU2.T3;
IMA1:T0 -> BIU2.T1;
IMA1:T3 -> BIU2.T2;
NOP;
NOP;
NOP;
NOP;
NOP;
BIU2:Store(T1,T0)(Mode0)(A++);
BIU2:Store(T2,T0)(Mode0)(A++);
//BIU2:Store(T3,T0)(Mode0)(A++);
NOP;
NOP;
NOP;
BIU2:Store(T2,T1)(Mode0)(A++);
BIU2:Store(T3,T1)(Mode0)(A++);
NOP;
NOP;
NOP;
@ -109,4 +138,3 @@ Slide_Win:
NOP;
MFetch:REPEAT @(10);
MFetch:MPU.STOP;

4
MicroCode/SlidingCorrelation/src/spu/SlidingCorrelation.s.c
View File

@ -3,11 +3,11 @@
void SlidingCorrelation(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr) {
volatile unsigned int *Para = (volatile unsigned int *)ConfigAddr;
Para[16*1+0] = InAddr1;
Para[16*1+0] = InAddr1;
Para[16*2+0] = InAddr2;
Para[16*3+0] = InAddr1;
Para[16*3+1] = InAddr1;
Para[16*4+0] = InAddr2;
Para[16*4+1] = InAddr2;
Para[16*6+0] = MaxAddr;
Para[16*5+0] = MaxAddr;
}

13
MicroCode/SlidingCorrelation/src/spu/SlidingCorrelationSecond.s.c
View File

@ -3,11 +3,12 @@
void SlidingCorrelationSecond(int ConfigAddr, int InAddr1, int InAddr2, int MaxAddr) {
volatile unsigned int *Para = (volatile unsigned int *)ConfigAddr;
Para[16*1+0] = InAddr1;
Para[16*1+1] = InAddr1;
Para[16*2+0] = InAddr2;
Para[16*2+1] = InAddr2;
Para[16*3+0] = MaxAddr;
Para[16*4+0] = MaxAddr;
Para[16*1+0] = InAddr1;
Para[16*2+0] = InAddr2;
Para[16*3+0] = InAddr1;
Para[16*3+1] = InAddr1;
Para[16*4+0] = InAddr2;
Para[16*4+1] = InAddr2;
Para[16*5+0] = MaxAddr;
}

24
MicroCode/SlidingCorrelation/src/spu/main.s.c
View File

@ -39,8 +39,8 @@ __DM3 int ConfigMatrix2[] = {
__DM1 int slice1[1055]; // 用于存储Input1切片数据
__DM2 int slice2[1055]; // 用于存储Input2切片数据
__DM5 int MaxData[4];//bestposition maxsum lastsum
__DM5 int MaxData2[4];//bestposition maxsum
__DM5 int MaxData[2];//bestposition maxsum lastsum
__DM5 int MaxData2[2];//bestposition maxsum
__DM0 int result[2]; // 存储SyncVer微码模块的计算结果
__DM4 int OutputData2[1055];
@ -78,10 +78,10 @@ int main(void) {
SlidingCorrelationAsm(SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
MaxData2[0] = MaxData[0];
MaxData2[1] = MaxData[1];
MaxData2[2] = MaxData[2];
MaxData2[3] = MaxData[3];
maxPosition = MaxData[0]&0x0000ffff;
maxsum = MaxData[1];
printf("初步同步位置：%d\n", maxPosition);
printf("maxsum：%d\n", maxsum);
//second part
SlidingCorrelationSecond((int)ConfigMatrix2, MPU_ADDR(Input1_part2), MPU_ADDR(Input2_part2), MPU_ADDR(MaxData2));
SVRReg[0] = MPU_ADDR(ConfigMatrix2);
@ -89,7 +89,8 @@ int main(void) {
a = __ucps2_getStatB();
__ucps2_delay();
uint32_t time1 = tick();
if(0==MaxData2[0])
/*if(0==MaxData2[0])
{
if(MaxData[1]==MaxData2[1])
{
@ -104,13 +105,14 @@ int main(void) {
{
maxPosition = MaxData2[0]&0x0000ffff+DATA_SIZE/2-1;
maxsum = MaxData2[1];
};
};*/
// 设置同步标志
is_synced = 1;
printf("初步同步位置：%d\n", maxPosition);
printf("maxsum：%d\n", maxsum);
printf("time：%d\n", time1-time0);
maxPosition = MaxData2[0]&0x0000ffff;
maxsum = MaxData2[1];
printf("初步同步位置：%d\n", maxPosition);
printf("maxsum：%d\n", maxsum);
}
/*// 同步后，执行精确同步位置计算

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Platform/build/libecs_rfm_spu0.a
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