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合入sync_symb部分

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HUOHUO 2025-03-30 09:50:15 -07:00
parent 56a44181a6
commit ee9e8844e8
76 changed files with 248357 additions and 15 deletions
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3
.vscode/settings.json vendored
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@ -24,6 +24,7 @@
"ape_csu.h": "c",
"mem_sections.h": "c",
"msg_transfer_layer.h": "c",
"typedef.h": "c"
"typedef.h": "c",
"receiver_bit_func.h": "c"
}
}

2
APE5/Makefile
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@ -1,6 +1,6 @@
############################
# mpu libs need to link to this APE, could be specified by user
MICRO_CODE_LIBS:=
MICRO_CODE_LIBS:=Block_Transform Channel_Est Channel_Equ Fre_est Fre_comp
############################
# tool path, could be specified by user
#UCP_HOME=/opt/sdk/ucp2.0_sdk/bin

10
APELib/Receiver_symb/inc/ChannelEstImpl.h Normal file
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@ -0,0 +1,10 @@
//#ifndef REMOVE_MC_TEST
#ifndef CHANNELESTIMPL_H_
#define CHANNELESTIMPL_H_
#include "ucps2.h"
#include <ChannelEst.h>
#include "stdio.h"
void ChannelEstImpl(v16u32 * SVRReg,int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr);
#endif //DEBUG_MC

10
APELib/Receiver_symb/inc/TransformImpl.h Normal file
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@ -0,0 +1,10 @@
//#ifndef REMOVE_MC_TEST
#ifndef TRANSFORMIMPL_H_
#define TRANSFORMIMPL_H_
#include "ucps2.h"
#include <Transform.h>
#include "stdio.h"
void TransformImpl(v16u32 * SVRReg,int *ConfigAddr, int InAddr, int OutAddr, int N, double* thita, int direct);
#endif //DEBUG_MC

38
APELib/Receiver_symb/inc/channelEquImpl.h Normal file
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@ -0,0 +1,38 @@
//#ifndef REMOVE_MC_TEST
#ifndef CHANNELEQUIMPL_H_
#define CHANNELEQUIMPL_H_
#include "ucps2.h"
#include "stdio.h"
#include <Equalizer_1port.h>
#include <Fft4096Int32.h>
#include <IFFT4096.h>
#include "IFFT4096DataTurn.h"
#include "AddCP.h"
#include "ape_common.h"
#include "type_define.h"
void ChannelEquImpl(
v16u32 * SVRReg,
int *CfgFft4096,
int *CfgEQ21Part1,
int *ConfigBaseAddr3,
int *CfgIFFT4096,
int *ConfigDataTurn,
int *ConfigAddCp,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,
int *available_ptr_dm3,
int *InChannelEst_ddr_ptr,
int *InData_ddr_ptr,
int *signal0, // DM2
int *InputNoise,
int *W4096, // DM2
int *CalAddr0,
int *CalAddr1,
int *CalAddr2,
int *Lut_phase,
int res_ptr
);
#endif //DEBUG_MC

12
APELib/Receiver_symb/inc/freOffCompImpl.h Normal file
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@ -0,0 +1,12 @@
#ifndef FREOFFCOMP_H_
#define FREOFFCOMP_H_
#include "ucps2.h"
#include "ucpm2.h"
#include "ape_common.h"
#include "type_define.h"
MPU_ENTRY void freOffCompAsm(v16u32 src);
void freOffCompImpl(v16u32 * SVRReg, int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOutAddr,int* data_ptr_ddr,int* res_ptr_ddr, int *ava_ptr_dm2, int *ava_ptr_dm3);
#endif /* FREQOFFSETEST_H_ */

12
APELib/Receiver_symb/inc/freOffEstImpl.h Normal file
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@ -0,0 +1,12 @@
#ifndef FREOFFESTIMPL_H_
#define FREOFFESTIMPL_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void freOffEstAsm(v16u32 src);
void freOffEstImpl(v16u32 * SVRReg, int* ConfigBaseAddr_est,int *InputAddr0,int *InputAddr1, int *freEstOutAddr);
#endif

36
APELib/Receiver_symb/inc/receiver_symb_func.h
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@ -26,12 +26,14 @@
//微码配置空间偏移结构体
extern receiver_symb_table_param_t g_receiver_symb_table_param;
extern uint32_t *receiver_symb_config_dm0_ptr;
extern uint32_t *receiver_symb_config_dm1_ptr;
extern uint32_t *receiver_symb_config_dm2_ptr;
extern uint32_t *receiver_symb_config_dm3_ptr;
extern int32_t storedfreoffestvalue ;
void Receiver_Symb_Init();
void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len);
@ -43,4 +45,38 @@ void Receiver_Symb_Proc(
int32_t* temp_dm3_ptr
);
void FreOff_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t* temp_dm2_ptr,
int32_t* temp_dm3_ptr
);
void ChannelEst_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr
);
void ChannelEqu_Proc(
uint32_t* param_data_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t* temp_dm2_ptr,
int32_t* temp_dm3_ptr
);
void Transform_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t *temp_dm2_ptr,
int32_t *temp_dm3_ptr
);
#endif

39
APELib/Receiver_symb/inc/receiver_symb_macro.h
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@ -1,5 +1,5 @@
/******************************************************************
* @file receiver_symb_macro.h
* @file RECEIVER_SYMB_symb_macro.h
* @brief: [file description]
* @author: HUOHUO
* @Date 2024年10月30日
@ -10,10 +10,45 @@
#ifndef RECEIVER_SYMB_MACRO_H
#define RECEIVER_SYMB_MACRO_H
//GENERATE with Generate_receiver_symb_macro_h.m
//GENERATE with Generate_RECEIVER_SYMB_symb_macro_h.m
//DO NOT MODIFY
//=======================================================================
//微码配置空间长度定义，单位为word(4Byte)
#define RECEIVER_SYMB_FreOffEst_CFG1_LENGTH (0x0090)
#define RECEIVER_SYMB_FreOffComp_CFG2_LENGTH (0x0040)
#define RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH (0x0070)
#define RECEIVER_SYMB_ChannelEst_CFG4_LENGTH (0x0050)
#define RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH (0x0350)
#define RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH (0x00E0)
#define RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH (0x00C0)
#define RECEIVER_SYMB_IFFT4096_CFG7_LENGTH (0x0360)
#define RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH (0x0070)
#define RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH (0x0130)
#define RECEIVER_SYMB_DeTransform2_CFG8_LENGTH (0x0060)
#define RECEIVER_SYMB_DeTransform4_CFG9_LENGTH (0x0080)
#define RECEIVER_SYMB_FREOFF_CFG_LENGTH (RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH )
#define RECEIVER_SYMB_CHANNELEST_CFG_LENGTH (RECEIVER_SYMB_ChannelEst_CFG4_LENGTH)
#define RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH (RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH + RECEIVER_SYMB_IFFT4096_AddCP_CFG7_LENGTH )
//SPU查找表各字段长度定义,单位为word(4Byte)
#define RECEIVER_SYMB_PilotOrig_LUT1_LENGTH (0x0420)
#define RECEIVER_SYMB_EqW4096_LUT2_LENGTH (0x2000)
#define RECEIVER_SYMB_EqFactor0_LUT3_LENGTH (0x0800)
#define RECEIVER_SYMB_EqFactor1_LUT4_LENGTH (0x0800)
#define RECEIVER_SYMB_EqFactor_LUT5_LENGTH (0x0078)
#define RECEIVER_SYMB_EqCpPhase_LUT6_LENGTH (0x0004)
//=======================================================================
#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000) //equ output
#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
//SPU查找表各字段长度定义,单位为word(4Byte)

15
APELib/Receiver_symb/inc/receiver_symb_struct.h
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@ -19,8 +19,16 @@
//各微码或查找表偏移及指针定义
typedef struct receiver_symb_table_param_s
{
//MPU CONFIG OFFSET
//MPU CONFIG OFFSET 基地址
uint32_t FreOffEst_CFG1_Offset;
uint32_t FreOffComp_CFG2_Offset;
uint32_t FreOffCordic_CFG3_Offset;
uint32_t ChannelEst_CFG4_Offset;
uint32_t Fft4096Int32_CFG5_Offset;
uint32_t EQ21Part1_CFG6_Offset;
uint32_t IFFT4096_CFG7_Offset;
uint32_t DeTransform2_CFG8_Offset;
uint32_t DeTransform4_CFG9_Offset;
// 存储微码参数表的ddr基地址和长度
uint32_t receiver_symb_config0_ddr_ptr;//receiver DM0微码配置文件ddr地址
uint32_t receiver_symb_config0_length;//receiver DM0微码配置文件ddr长度
@ -36,7 +44,8 @@ typedef struct receiver_symb_table_param_s
// SPU LUT SM基地址和长度
uint32_t pucch_lut_sm_ptr; //PUCCH查找表在SM中的基地址
uint32_t pucch_lut_length; //PUCCH查找表总长度
}receiver_symb_table_param_t;

28
APELib/Receiver_symb/src/ChannelEstImpl.s.c Normal file
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@ -0,0 +1,28 @@
#include <ChannelEstImpl.h>
#include <ChannelEst.h>
#include "ucps2.h"
#include "ucpm2.h"
void ChannelEstImpl(v16u32 * SVRReg,int *ConfigAddr, int *InAddr1, int *InAddr2, int *OutAddr)
{
for(int i=0;i<32;i++){
InAddr1[i+1024] = InAddr1[i];
InAddr2[i+1024] = InAddr2[i];
}
volatile int a;
ChannelEst(ConfigAddr, MPU_ADDR(InAddr1),MPU_ADDR(InAddr2),MPU_ADDR(OutAddr));
SVRReg[0][0] = MPU_ADDR(ConfigAddr);
channelEstAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
for(int i=32;i<4096;i++){
OutAddr[i] = 0;
}
}

29
APELib/Receiver_symb/src/TransformImpl.s.c Normal file
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@ -0,0 +1,29 @@
#include <TransformImpl.h>
#include <Transform.h>
#include "ucps2.h"
#include "ucpm2.h"
void TransformImpl(v16u32 * SVRReg,int *ConfigAddr, int InAddr, int OutAddr, int N, double* thita, int direct){
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
volatile int a;
Transform((int)ConfigAddr,MPU_ADDR(InAddr),MPU_ADDR(OutAddr), N, thita, direct);
SVRReg[0][0] = MPU_ADDR(ConfigAddr);
if(N==2){
Transform2Asm(*SVRReg);
}
else if(N==4){
Transform4Asm(*SVRReg);
}
a = __ucps2_getStatB();
__ucps2_delay();
}

268
APELib/Receiver_symb/src/channelEquImpl.s.c Normal file
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@ -0,0 +1,268 @@
#include "ucps2.h"
#include "ucpm2.h"
#include <channelEquImpl.h>
void ChannelEquImpl(
v16u32 * SVRReg,
int *CfgFft4096,
int *CfgEQ21Part1,
int *ConfigBaseAddr3,
int *CfgIFFT4096,
int *ConfigDataTurn,
int *ConfigAddCp,
int *available_ptr_dm0,
int *available_ptr_dm1,
int *available_ptr_dm2,
int *available_ptr_dm3,
int *InChannelEst_ddr_ptr,
int *InData_ddr_ptr,
int *signal0,
int *InputNoise,
int *W4096 ,
int *CalAddr0,
int *CalAddr1,
int *CalAddr2,
int *Lut_phase,
int res_ptr
){
volatile int a = 1;
int numSym = 7;
int Scale = 13;
int NRE=4096;
int ShiftFactor[] = {7,1,0,0,0,0,0,0,0,0,0,0};
int NumCB = 2;
for(int i=0;i<NumCB;i++){
int *Scalep = available_ptr_dm0;
int *Scale0 = available_ptr_dm0 + 0x0040;
int *Scales = available_ptr_dm0 + 0x0080;
int *tmp0 = (int*)(((int)available_ptr_dm1 + 0x4000 - 1) & ~(0x4000 - 1)); // LENGTH: 0x2000
int *Fft_est_dm3_ptr = (int*)(((int)available_ptr_dm3 + 0x4000 - 1) & ~(0x4000 - 1)); // LENGTH: 0x1000
int *channelEst_dm0_ptr = (int*)(((int)Scales + 0x0100 + 0x4000 - 1) & ~(0x4000 - 1));
/*****************************************FFT of channelEst*****************************************/
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InChannelEst_ddr_ptr + 4096*i) ,
(uint64_t)DM_TO_CSU_ADDR(channelEst_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
Fft4096Int32(
(int)CfgFft4096,
1,
Scale,
ShiftFactor,
MPU_ADDR(W4096), //DM2
MPU_ADDR(channelEst_dm0_ptr), //DM0
MPU_ADDR(available_ptr_dm2), //DM2
MPU_ADDR(Fft_est_dm3_ptr), //DM3
MPU_ADDR(tmp0), //DM1
MPU_ADDR(Scalep),
MPU_ADDR(Scale0)
);
SVRReg[0][0] = MPU_ADDR(CfgFft4096);
Fft4096Int32Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
/*****************************************channelEqu*****************************************/
// for(int m=0;m<4096;m++){
// *(Fft_est_dm3_ptr + 4096 + m) = Fft_est_dm3_ptr[m];
// }
for(int j=0;j<numSym;j++){
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
int *Fft_outputdata_dm3_ptr = Fft_est_dm3_ptr + 0x2000;
int *InData_dm0_ptr = channelEst_dm0_ptr + 0x2000;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)(InData_ddr_ptr + (68+4096)*j + 68) ,
(uint64_t)DM_TO_CSU_ADDR(InData_dm0_ptr),
4096*4,
DMA_TAG_G2L,
0);
// FFT of Data
Fft4096Int32(
(int)CfgFft4096,
1,
Scale,
ShiftFactor,
MPU_ADDR(W4096),
MPU_ADDR(InData_dm0_ptr), //DM0
MPU_ADDR(available_ptr_dm2), //DM2
MPU_ADDR(Fft_outputdata_dm3_ptr), //DM3
MPU_ADDR(tmp0), //DM1
MPU_ADDR(Scalep),
MPU_ADDR(Scale0)
);
SVRReg[0][0] = MPU_ADDR(CfgFft4096);
Fft4096Int32Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
// 构造第二根天线数据，与第一根相同
for(int m=0;m<4096;m++){
*(Fft_outputdata_dm3_ptr + 4096 + m) = Fft_outputdata_dm3_ptr[m];
}
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
int *Equ_Output = InData_dm0_ptr + 0x1000; //LENGTH 0x2000 (the second ant occupied additional space 0x1000)
int *InOut2_dm1_ptr = tmp0; //LENGTH 0x1000
int *InOut3_dm0_ptr = InData_dm0_ptr + 0x3000; //LENGTH 0x2000
int *InOut1_dm1_ptr = tmp0 + 0x1000; //LENGTH 0x1000
EQ21Part1(
CfgEQ21Part1,
NRE,
1,
MPU_ADDR(Fft_est_dm3_ptr), //dm3 信道估计fft
MPU_ADDR(InputNoise), //dm3 噪声全0
MPU_ADDR(Fft_outputdata_dm3_ptr), //dm3 数据fft
MPU_ADDR(Equ_Output), //dm0
MPU_ADDR(InOut1_dm1_ptr), //dm1
MPU_ADDR(InOut2_dm1_ptr), //dm1
MPU_ADDR(InOut3_dm0_ptr) //dm0
);
SVRReg[0][0] = MPU_ADDR(CfgEQ21Part1);
EQ21Part1Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
int *Equ_Output_2 = available_ptr_dm2; //第一根天线均衡输出
int *Equ_Output_21 = available_ptr_dm2 + 0x2000; //第二根天线均衡输出
EQ1Part2(
ConfigBaseAddr3,
NRE,
1,
MPU_ADDR(Equ_Output),
MPU_ADDR(InOut1_dm1_ptr),
MPU_ADDR(InOut2_dm1_ptr),
MPU_ADDR(InOut3_dm0_ptr),
MPU_ADDR(Equ_Output_2),
MPU_ADDR(Equ_Output_21)
);
SVRReg[0][0] = MPU_ADDR(ConfigBaseAddr3);
EQ1Part2Asm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
// for (size_t i = 0; i < 4096; i++) {
// int32_t num = Equ_Output_2[i];
//
// int16_t real = (int16_t)(num & 0xFFFF);
// int16_t imag = (int16_t)(num >> 16);
// real /= 8;
// imag /= 8;
//
// *(Equ_Output + i) = ((int32_t)imag << 16) | ((uint16_t)real);
// }
int *Temp1 = Fft_outputdata_dm3_ptr; // 缓存
IFFT4096DataTurn(
(int)ConfigDataTurn,
1,
1,
MPU_ADDR(Equ_Output_2), //dm2
MPU_ADDR(tmp0), //dm1 无效
MPU_ADDR(Equ_Output), //dm0
MPU_ADDR(Temp1) //dm3 无效
);
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
SVRReg[0][0] = MPU_ADDR(ConfigDataTurn);
IFFT4096DataTurnAsm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
int *Temp0 = available_ptr_dm2; // buff, Equ_Output_2
IFFT4096(
(int)CfgIFFT4096,
1,
MPU_ADDR(Temp0), //DM2
MPU_ADDR(Temp1), //DM3
MPU_ADDR(Equ_Output), //DM0
MPU_ADDR(tmp0), //DM1
MPU_ADDR(CalAddr0), //DM2
MPU_ADDR(CalAddr1), //DM3
MPU_ADDR(CalAddr2)); //DM1
SVRReg[0][0] = MPU_ADDR(CfgIFFT4096);
IFFT4096Asm(*SVRReg);
__ucps2_getStatB();
__ucps2_delay();
int CPLength0 = 352;
int CPLength1 = 288;
AddCP(
(int) ConfigAddCp,
2,
1,
CPLength0,
CPLength1,
MPU_ADDR(Equ_Output), //DM0
MPU_ADDR(tmp0), //DM1 invalid
MPU_ADDR(Equ_Output_2), //DM2
MPU_ADDR(Temp1), //DM3 invalid
MPU_ADDR(Lut_phase) //
);
SVRReg[0][0] = MPU_ADDR(ConfigAddCp);
AddCPAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR((Equ_Output_2+CPLength0)),
(uint64_t)res_ptr,
4096*4 ,
DMA_TAG_L2G,
1);
res_ptr = res_ptr + 16384;
}
}
return;
}

75
APELib/Receiver_symb/src/channelEqu_proc.s.c Normal file
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@ -0,0 +1,75 @@
#include "receiver_symb_func.h"
void ChannelEqu_Proc(
uint32_t* param_data_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t* temp_dm2_ptr,
int32_t* temp_dm3_ptr
)
{
//局部变量定义
int32_t *cfg_addr = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH;
int32_t *lut_addr = receiver_symb_config_dm2_ptr + RECEIVER_SYMB_PilotOrig_LUT1_LENGTH;
// Temporary input for test
uint32_t * InputNoise = ((((uint32_t)&temp_dm3_ptr[0] + 4096*2 + 4095)>>12)<<12);
for(int i=0;i<4096;i++){
InputNoise[i] = 0;
}
uint32_t res_ptr = CHANNELEQU_DATA_DDR_PTR; //Store result of Equ
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
// available address space for channelEqu
uint32_t * available_ptr_dm0 = temp_dm0_ptr;
uint32_t * available_ptr_dm1 = temp_dm1_ptr + 0x1000;
uint32_t * available_ptr_dm2 = temp_dm2_ptr;
uint32_t * available_ptr_dm3 = InputNoise + 0x1000;
// Configuration
uint32_t *CfgFft4096Int32 = cfg_addr;
uint32_t *CfgEQ21Part1 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH;
uint32_t *CfgEQ1Part2 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH;
uint32_t *CfgIFFT4096 = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH;
uint32_t *CfgIFFT4096TURN = cfg_addr + RECEIVER_SYMB_Fft4096Int32_CFG5_LENGTH + RECEIVER_SYMB_EQ21Part1_CFG6_LENGTH + RECEIVER_SYMB_EQ1Part2_CFG6_1_LENGTH + RECEIVER_SYMB_IFFT4096_CFG7_LENGTH;
uint32_t *CfgIFFT4096AddCP = CfgIFFT4096TURN + RECEIVER_SYMB_IFFT4096_TURN_CFG7_LENGTH;
// LUT
uint32_t *Lut_W4096 = lut_addr;
uint32_t *Lut_EqFactor0 = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH;
uint32_t *Lut_EqFactor1 = receiver_symb_config_dm3_ptr;
uint32_t *Lut_EqFactor = receiver_symb_config_dm1_ptr;
uint32_t *Lut_Zero = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH; //useless
uint32_t *Lut_phase = lut_addr + RECEIVER_SYMB_EqW4096_LUT2_LENGTH + RECEIVER_SYMB_EqFactor0_LUT3_LENGTH + RECEIVER_SYMB_EqFactor1_LUT4_LENGTH + RECEIVER_SYMB_EqFactor_LUT5_LENGTH ;
// channelEst and data
uint32_t *InputCHEst_ddr_ptr = (uint32_t *)CHANNELEST_DATA_DDR_PTR;
uint32_t *InputData_ddr_ptr = (uint32_t *)COMPENSATED_DATA_DDR_PTR;
ChannelEquImpl(SVRReg,CfgFft4096Int32,CfgEQ21Part1,CfgEQ1Part2,CfgIFFT4096,CfgIFFT4096TURN,CfgIFFT4096AddCP,
available_ptr_dm0,
available_ptr_dm1,
available_ptr_dm2 ,
available_ptr_dm3 ,
InputCHEst_ddr_ptr,
InputData_ddr_ptr,
Lut_Zero,
InputNoise,
Lut_W4096,
Lut_EqFactor0,
Lut_EqFactor1,
Lut_EqFactor,
Lut_phase,
res_ptr
);
}

59
APELib/Receiver_symb/src/channelEst_Proc.s.c Normal file
View File

@ -0,0 +1,59 @@
#include "receiver_symb_func.h"
void ChannelEst_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr
)
{
//局部变量定义
int32_t *cfg_addr;
uint32_t time_data_ddr_ptr;
uint32_t time_data_length;
uint32_t time_data_dm0_ptr = ((((uint32_t)&temp_dm0_ptr[0] + 4095)>>12)<<12);
uint32_t res_ptr = CHANNELEST_DATA_DDR_PTR;
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
int numSub = 2;
int sliceIndex[2] = {1024,31268}; // position of pilot
for(int subIndex=0;subIndex<numSub;subIndex++){
time_data_ddr_ptr = COMPENSATED_DATA_DDR_PTR + sliceIndex[subIndex];
time_data_length = 1024;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
time_data_length*4,
DMA_TAG_G2L,
0);
// Get Configuration and LUT
uint32_t *ConfigAddr_channelEst = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH + RECEIVER_SYMB_FreOffCordic_CFG3_LENGTH;
uint32_t *Pilot_orig_LUT = receiver_symb_config_dm2_ptr;
uint32_t *InputPilotAddr = (uint32_t *)time_data_dm0_ptr;
uint32_t *channelEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0080);
ChannelEstImpl(SVRReg,ConfigAddr_channelEst, Pilot_orig_LUT, InputPilotAddr, channelEstOutAddr);
WAIT_MPU_STOP;
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)channelEstOutAddr),
(uint64_t)res_ptr,
4096*4 ,
DMA_TAG_L2G,
1);
res_ptr += 0x4000;
}
}

60
APELib/Receiver_symb/src/freOffCompImpl.s.c Normal file
View File

@ -0,0 +1,60 @@
#include "ucps2.h"
#include "ucpm2.h"
#include <freOffComp.h>
#include <freOffCompImpl.h>
#include <cordicSC.h>
#include "ape_common.h"
//v16u32 KI = {2,4,6};
void freOffCompImpl(v16u32 * SVRReg, int* ConfigAddr_comp, int* ConfigAddr_cordic, int *freEstOutAddr,int* data_ptr_ddr,int* res_ptr_ddr, int *ava_ptr_dm2, int *ava_ptr_dm3){
volatile int a = 1;
int count = 7680;
freEstOutAddr[0] = freEstOutAddr[0]>>10;
int increment = freEstOutAddr[0];
for(int i=0;i<8;i++){
int res_ptr_offset = i*count;
int *input_data_ptr = ava_ptr_dm3;
int *fre_comp_exp_ptr = ava_ptr_dm2;
int *output_data_ptr = ava_ptr_dm3;
int time_data_length = count;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)data_ptr_ddr,
(uint64_t)DM_TO_CSU_ADDR(input_data_ptr),
time_data_length*4,
DMA_TAG_G2L,
0);
cordicSC(ConfigAddr_cordic,MPU_ADDR(freEstOutAddr),MPU_ADDR(fre_comp_exp_ptr),increment,count);
SVRReg[0][0] = MPU_ADDR(ConfigAddr_cordic);
cordicSCAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
freOffComp(ConfigAddr_comp,MPU_ADDR(input_data_ptr),MPU_ADDR(fre_comp_exp_ptr),MPU_ADDR(output_data_ptr));
SVRReg[0][0] = MPU_ADDR(ConfigAddr_comp);
freOffCompAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)output_data_ptr),
(uint64_t)(res_ptr_ddr + res_ptr_offset),
time_data_length*4 ,
DMA_TAG_L2G,
1);
}
return ;
}

26
APELib/Receiver_symb/src/freOffEstImpl.s.c Normal file
View File

@ -0,0 +1,26 @@
#include "ucps2.h"
#include "ucpm2.h"
#include<freOffEst.h>
#include<freOffEstImpl.h>
v16u32 KI = {2,4,6};
void freOffEstImpl(v16u32 * SVRReg,int* ConfigBaseAddr_est, int *InputAddr0,int *InputAddr1,int *freEstOutAddr){
volatile int a = 1;
freOffEst(ConfigBaseAddr_est, MPU_ADDR(InputAddr0), MPU_ADDR(InputAddr1), MPU_ADDR(freEstOutAddr));
SVRReg[0][0] = MPU_ADDR(ConfigBaseAddr_est);
freOffEstAsm(*SVRReg);
a = __ucps2_getStatB();
__ucps2_delay();
return ;
}

106
APELib/Receiver_symb/src/freoff_Proc.s.c Normal file
View File

@ -0,0 +1,106 @@
#include "receiver_symb_func.h"
void FreOff_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t* temp_dm2_ptr,
int32_t* temp_dm3_ptr
)
{
//局部变量定义
int32_t *cfg_addr;
uint32_t time_data_ddr_ptr;
uint32_t time_data_length;
uint32_t time_data_dm3_ptr = ((((uint32_t)&temp_dm3_ptr[0] + 4095)>>12)<<12);
uint32_t res_ptr = RECEIVER_SYMB_OUT;
// Read Global Buff
time_data_ddr_ptr = (uint32_t)*param_ptr;
time_data_length = 2048;
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)time_data_ddr_ptr,
(uint64_t)DM_TO_CSU_ADDR(time_data_dm3_ptr),
time_data_length*4,
DMA_TAG_G2L,
0);
// Get Configuration
uint32_t *ConfigAddr_est = receiver_symb_config_dm0_ptr;
uint32_t *ConfigAddr_comp = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH;
uint32_t *ConfigAddr_cordic = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FreOffEst_CFG1_LENGTH + RECEIVER_SYMB_FreOffComp_CFG2_LENGTH;
// Get CP and Pilot
uint32_t *InputCPAddr = (uint32_t *)time_data_dm3_ptr;
uint32_t *InputPilotAddr = InputCPAddr + 1024;
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
uint32_t *freEstOutAddr = (uint32_t *)(temp_dm1_ptr + 0x0020);
SVRReg[0] = (v16u32){0, 0, 0, 0,
0x40, 0, 0, 0,
0xff00ff, 0, 0, 0x0000,
0xffff, 0x6, 0, 0};
freOffEstImpl(SVRReg,ConfigAddr_est, InputCPAddr, InputPilotAddr, freEstOutAddr);
// Low-pass Filter
if(storedfreoffestvalue > 600000){
storedfreoffestvalue = freEstOutAddr[0];
}
else{
storedfreoffestvalue = 0.7*storedfreoffestvalue + 0.3*freEstOutAddr[0];
}
freEstOutAddr[0] = storedfreoffestvalue;
// Frequency Offset Compensate
uint32_t *available_ptr_dm2 = temp_dm2_ptr;
uint32_t *available_ptr_dm3 = temp_dm3_ptr;
freOffCompImpl(
SVRReg,
ConfigAddr_comp,
ConfigAddr_cordic,
freEstOutAddr,
(uint32_t *)time_data_ddr_ptr,
(uint32_t *)res_ptr,
available_ptr_dm2,
available_ptr_dm3
);
}
// //计算结果搬移到SM
//
// temp_u32 = (uint32_t)(((time_data_length +7)>>3)<<3);//计算byte数
// WAIT_MPU_STOP;
// ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR(time_data_dm0_ptr),
// (uint64_t)res_ptr,
// temp_u32,
// DMA_TAG_L2G,
// 1);
//
// return;
//}

8
APELib/Receiver_symb/src/receiver_Symb_Proc.s.c
View File

@ -58,6 +58,14 @@ void Receiver_Symb_Proc(
// temp_u32,
// DMA_TAG_L2G,
// 1);
FreOff_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
ChannelEst_Proc(param_ptr,temp_dm0_ptr,temp_dm1_ptr);
ChannelEqu_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
Transform_Proc(param_ptr, temp_dm0_ptr, temp_dm1_ptr, temp_dm2_ptr, temp_dm3_ptr);
#ifdef IDE_TEST
printf("DataTrans");
#endif
//7.核间消息to APE2

10
APELib/Receiver_symb/src/receiver_Symb_Task.s.c
View File

@ -76,7 +76,7 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
}
//DM0第三段，堆空间
receiver_symb_temp_dm0_ptr = (int32_t *)ADDR_ALIGN(receiver_symb_config_dm0_ptr + \
g_receiver_symb_table_param.receiver_symb_config0_length, 12);//起始地址4k对齐
(g_receiver_symb_table_param.receiver_symb_config0_length>>2), 12);//起始地址4k对齐
//3. DM3空间申请
receiver_symb_malloc_dm3_ptr = dmemalign_unit(0x4000, 196608, APE_DM3);//申请了192KiB 首地址16k对齐
@ -101,7 +101,7 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
}
//DM3第二段，堆空间
receiver_symb_temp_dm3_ptr = (int32_t *)ADDR_ALIGN(receiver_symb_config_dm3_ptr + \
g_receiver_symb_table_param.receiver_symb_config3_length, 14); //起始地址16k对齐
(g_receiver_symb_table_param.receiver_symb_config3_length>>2), 14); //起始地址16k对齐
//4. DM1空间申请
receiver_symb_malloc_dm1_ptr = dmemalign_unit(0x4000, 131072, APE_DM1);//申请了128KiB 首地址16k对齐
//若空间申请失败，则释放已申请的空间，再退出任务
@ -125,7 +125,7 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
}
//DM1第二段，堆空间
receiver_symb_temp_dm1_ptr = (int32_t *)ADDR_ALIGN(receiver_symb_config_dm1_ptr + \
g_receiver_symb_table_param.receiver_symb_config1_length, 12); //起始地址4k对齐
(g_receiver_symb_table_param.receiver_symb_config1_length>>2), 12); //起始地址4k对齐
//5. DM2空间申请
receiver_symb_malloc_dm2_ptr = dmemalign_unit(0x4000, 196608, APE_DM2);//申请了192KiB 首地址16k对齐
//若空间申请失败，释放已申请的空间，再退出任务
@ -144,7 +144,7 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
if(0 < g_receiver_symb_table_param.receiver_symb_config2_length)
{
ape_csu_task_lookup(DMA_TAG_G2L, 1);
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint32_t)g_receiver_symb_table_param.receiver_symb_config2_ddr_ptr,
ape_csu_dma_1D_G2L_ch0ch1_transfer((uint64_t)g_receiver_symb_table_param.receiver_symb_config2_ddr_ptr,
DM_TO_CSU_ADDR(receiver_symb_config_dm2_ptr),
g_receiver_symb_table_param.receiver_symb_config2_length,
DMA_TAG_G2L,
@ -152,7 +152,7 @@ void Receiver_Symb_Task(receiver_sync2symb_t* msg_ptr, uint32_t msg_len)
}
//DM2第二段，堆空间
receiver_symb_temp_dm2_ptr = (int32_t *)ADDR_ALIGN(receiver_symb_config_dm2_ptr + \
g_receiver_symb_table_param.receiver_symb_config2_length, 14); //起始地址16k对齐
(g_receiver_symb_table_param.receiver_symb_config2_length>>2), 14); //起始地址16k对齐
TRACE(TRACE_RECEIVER_SYMB_ADDR, 3, 1);

1
APELib/Receiver_symb/src/receiver_Symb_Var.s.c
View File

@ -15,3 +15,4 @@ uint32_t *receiver_symb_config_dm0_ptr = NULLPTR;
uint32_t *receiver_symb_config_dm1_ptr = NULLPTR;
uint32_t *receiver_symb_config_dm2_ptr = NULLPTR;
uint32_t *receiver_symb_config_dm3_ptr = NULLPTR;
int32_t storedfreoffestvalue = 1000000;

99
APELib/Receiver_symb/src/transform_Proc.s.c Normal file
View File

@ -0,0 +1,99 @@
#include "receiver_symb_func.h"
void Transform_Proc(
uint32_t *param_ptr,
int32_t *temp_dm0_ptr,
int32_t *temp_dm1_ptr,
int32_t *temp_dm2_ptr,
int32_t *temp_dm3_ptr
)
{
//局部变量定义
uint32_t equ_data_ddr_ptr = CHANNELEQU_DATA_DDR_PTR; // COMPENSATED_DATA_DDR_PTR; // EQU_DATA_DDR_PTR;
// uint32_t res_ptr = CHANNELEQU_DATA_DDR_PTR;
v16u32 * SVRReg = (v16u32 *)temp_dm1_ptr;
uint32_t symbol_SM_addr_in = equ_data_ddr_ptr;
uint32_t symbol_SM_addr_out = TRANSFORMER_DATA_DDR_PTR;
uint32_t *Cfg_DeTransform2 = receiver_symb_config_dm0_ptr + RECEIVER_SYMB_FREOFF_CFG_LENGTH + RECEIVER_SYMB_CHANNELEST_CFG_LENGTH + RECEIVER_SYMB_CHANNELEQU_CFG_LENGTH;
uint32_t *Cfg_DeTransform4 = Cfg_DeTransform2 + RECEIVER_SYMB_DeTransform2_CFG8_LENGTH;
uint32_t TransTemp = (uint32_t)(temp_dm1_ptr + 0x1000) ;
uint32_t OutputAddr_Trans = (uint32_t)temp_dm3_ptr;
uint32_t InputAddr_Trans = (uint32_t)temp_dm3_ptr;
volatile int a;
/*****************************************initial*****************************************/
double thita[6];
int current_state[9 + 11 + 13];
for (int ii = 0; ii < 9 + 11 + 13; ii++){
int tmp = rand();
if(tmp>RAND_MAX/2)
current_state[ii] = 1;
else
current_state[ii] = 0;
}
get_thita(current_state,thita);
double* thita1, * thita2, * thita3;
thita1 = thita2 = thita;
thita3 = thita + 2;
for(int iBlk = 0;iBlk < 7;iBlk++){
ape_csu_dma_1D_G2L_ch2ch3_transfer(
(uint64_t)(equ_data_ddr_ptr + 4096*4*2*iBlk),//uint64_t addrSrc
(uint64_t)DM_TO_CSU_ADDR(TransTemp), //uint64_t addrDst
4096*4*2, //uint32_t dataLen
DMA_TAG_G2L, //uint8_t tag
1 //uint8_t isWait
);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TransformImpl(SVRReg, Cfg_DeTransform4,TransTemp,OutputAddr_Trans, 4, thita3, -1);
ape_csu_dma_1D_L2G_ch0ch1_transfer((uint64_t)DM_TO_CSU_ADDR((uint32_t)OutputAddr_Trans),
(uint64_t)symbol_SM_addr_in + 4096*4*2*iBlk,
4096*4*2,
DMA_TAG_L2G,
1);
}
for(int iSym = 0;iSym < 8;iSym++){
//reading 2D data from SM
ape_csu_dma_3Dto1D_G2L_ch6ch2_simp_transfer(
symbol_SM_addr_in + 512*4*iSym, //addrSrc
512*4, //xNumSrc
14, //yNumSrc
4096*4, //yStepSrc
0, //zStepSrc
DM_TO_CSU_ADDR(InputAddr_Trans), //DM_TO_CSU_ADDR(InputAddr_Trans)
14*512*4, //dataLen
DMA_TAG_G2L, //tag
1);
ape_csu_task_lookup(DMA_TAG_G2L, 1);
TransformImpl(SVRReg, Cfg_DeTransform2,InputAddr_Trans,TransTemp, 2, thita2, -1);
for(int i = 0; i<14;i++){
ape_csu_dma_1D_L2G_ch0ch1_transfer(
(uint64_t)DM_TO_CSU_ADDR(TransTemp + 512*4*i), //uint64_t addrSrc
(uint64_t)(symbol_SM_addr_out + 4096*4*i + 512*4*iSym), //uint64_t addrDst
512*4, //uint32_t dataLen
DMA_TAG_L2G, //uint8_t tag
1);
ape_csu_task_lookup(DMA_TAG_L2G, 1);
}
}
// printf("DataTranssss");
return ;
}

1
Common/inc/mem_def.h
View File

@ -55,6 +55,7 @@
#define RECEIVER_OUT1 (SM4_BASE)
#define RECEIVER_OUT2 (SM4_BASE + 0x4000)
#define RECEIVER_OUT3 (SM4_BASE + 0x8000)
#define RECEIVER_SYMB_OUT (RECEIVER_OUT1)
/************************************SM5--1.5M***********************************************/
#define RECEIVER_BASE (SM5_BASE) //4k对齐

4
Common/inc/task_define.h
View File

@ -22,12 +22,12 @@ typedef enum
PHY_TASK_PRI_CONFIG,
PHY_TASK_PRI_SLOT_IND,
PHY_TASK_PRI_TRANSMITTER,
PCIE_TASK_PRI_RECEIVER,
PHY_TASK_PRI_RECEIVER_SYNC,
PHY_TASK_PRI_RECEIVER_SYMB,
PHY_TASK_PRI_RECEIVER_BIT,
PHY_TASK_PRI_TEST,
PHY_TASK_PRI_RECEIVER_FIRST_SYNC,
PCIE_TASK_PRI_RECEIVER,
PHY_TASK_PRI_EQUAL_PRI, //不需要优先级抢占的任务，设置为该优先级
}task_pri_e;
@ -39,12 +39,12 @@ typedef enum
PHY_TASK_CONFIG,
PHY_TASK_SLOT_IND,
PHY_TASK_TRANSIMITTER,
PCIE_TASK_RECEIVER,
PHY_TASK_RECIEVER_SYNC,
PHY_TASK_RECIEVER_SYMB,
PHY_TASK_RECIEVER_BIT,
PHY_TASK_TEST,
PHY_TASK_RECIEVER_FIRST_SYNC,
PCIE_TASK_RECEIVER,
PHY_TASK_PHY_MGR,
PHY_TASK_MAX=32
}task_id_e;

3171
Config/Receiver_Symb_cfg_dm0.dat Normal file
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File diff suppressed because it is too large Load Diff

121
Config/Receiver_Symb_cfg_dm1.dat Normal file
View File

@ -0,0 +1,121 @@
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010101,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010101,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010101,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010101,
0x01010101,
0x01010101,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010101,
0x01010101,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010101,
0x01010101,
0x01010100,
0x01010101,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,
0x01010100,

13468
Config/Receiver_Symb_cfg_dm2.dat Normal file
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File diff suppressed because it is too large Load Diff

2048
Config/Receiver_Symb_cfg_dm3.dat Normal file
View File

File diff suppressed because it is too large Load Diff

102
MicroCode/Block_Transform/inc/DeTransformConfig_2.dat Normal file
View File

@ -0,0 +1,102 @@
//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

136
MicroCode/Block_Transform/inc/DeTransformConfig_4.dat Normal file
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//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1 right move 2
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index3 6
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index4 7
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

204
MicroCode/Block_Transform/inc/DeTransformConfig_8.dat Normal file
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//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1 right move 2
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
0x00000203,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index3 6
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index4 7
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index5 8
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index6 9
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index7 10
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index8 11
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

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MicroCode/Block_Transform/inc/Input_16.dat Normal file
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53248
MicroCode/Block_Transform/inc/Input_64.dat Normal file
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57344
MicroCode/Block_Transform/inc/Input_mod.dat Normal file
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58907
MicroCode/Block_Transform/inc/Input_old.dat Normal file
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1024
MicroCode/Block_Transform/inc/Input_pilot.dat Normal file
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14
MicroCode/Block_Transform/inc/Transform.h Normal file
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#ifndef Transform_H_
#define Transform_H_
#include "ucps2.h"
void Transform(int ConfigAddr, int InAddr, int OutAddr, int N, double* thita, int direct);
void get_thita(int* current_state, double* thita);
void RowCopy(int* Matrix,int* Block,int idx,int direct);
void ColCopy(int* Matrix,int* Block,int idx,int direct);
MPU_ENTRY void Transform2Asm(v16u32 src);
MPU_ENTRY void Transform4Asm(v16u32 src);
MPU_ENTRY void Transform8Asm(v16u32 src);
#endif /* Transform_H_ */

102
MicroCode/Block_Transform/inc/TransformConfig_2.dat Normal file
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//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

136
MicroCode/Block_Transform/inc/TransformConfig_4.dat Normal file
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//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index3 6
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index4 7
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

204
MicroCode/Block_Transform/inc/TransformConfig_8.dat Normal file
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//Mfetch 0
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//ShiftMode 1
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
0x00000003,
//input 2
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//output 3
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000040,
0x00000000,
0x00000000,
0x00000000,
0xffffffff,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Index1 4
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index2 5
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index3 6
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index4 7
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index5 8
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index6 9
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index7 10
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
//Index8 11
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000

10
MicroCode/Block_Transform/inc/ucp2_utils.h Normal file
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#ifndef UCP2_UTILS_H_
#define UCP2_UTILS_H_
void write_to_dm0(char* src, unsigned int size);
void print_string(char* string);
void print_char(unsigned char src);
void print_int(unsigned int src);
#endif /* UCP2_UTILS_H_ */

60
MicroCode/Block_Transform/src/mpu0/Transform2.m0.asm Normal file
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.section .text.m0, "ax"
.file "Transform2Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global Transform2Asm
Transform2Asm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
NOP;
NOP;
NOP;
NOP;
R5:PreConfig(M[0])(Mode0);
R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0);
R3:M[3] -> BIU3.T1(Mode0);
R0:M[10] -> IMA0.T1(Mode0) ||R1:M[10] -> IMA1.T2(Mode0) ;
R0:M[11] -> IMA0.T2(Mode0) ||R1:M[11] -> IMA1.T1(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
BIU2:wait 0 || IMA0: wait 10 || IMA1: wait 10|| SHU0: wait 14 ||SHU1: wait 14 ||BIU3: wait 17;
MFetch:LPTO %BLOCK @(KI0 - 0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || SHU0: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || SHU1: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BLOCK:
BIU2:wait 0 || IMA0: wait 0 || IMA1: wait 0 || SHU0: wait 0 || SHU1: wait 0 || BIU3: wait 0;
/*
BIU2:wait 0 || IMA0: wait 10 || IMA1: wait 10|| SHU0: wait 10 ||SHU1: wait 10 ||BIU3: wait 13;
MFetch:LPTO %BLOCK_0 @(KI0 - 0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
NOP;
NOP;
NOP;
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0);
BIU2:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0);
NOP;
NOP;
NOP;
SHU0: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
SHU1: T0+T1(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BLOCK_0:
BIU2:wait 0 || IMA0: wait 0 || IMA1: wait 0 || SHU0: wait 0 || SHU1: wait 0 || BIU3: wait 0;
*/
MFetch:REPEAT @(35);
MFetch:MPU.STOP;

56
MicroCode/Block_Transform/src/mpu0/Transform4.m0.asm Normal file
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.section .text.m0, "ax"
.file "Transform4Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global Transform4Asm
Transform4Asm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
BIU1:Load(T0)(A++) -> M[12](Mode0); //factor3
BIU1:Load(T0)(A++) -> M[13](Mode0); //factor4
NOP;
NOP;
R5:PreConfig(M[0])(Mode0);
R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0);
R2:M[1] -> IMA2.T0(Mode0) || R3:M[3] -> BIU3.T1(Mode0);
R0:M[10] -> IMA0.T1(Mode0) ||R2:M[1] -> IMA3.T0(Mode0) ;
R0:M[11] -> IMA0.T2(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || R2: M[10] -> IMA2.T3(Mode0) || R3: M[10] -> IMA3.T4(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
R0:M[12] -> IMA0.T3(Mode0) || R1: M[11] -> IMA1.T3(Mode0) || R2: M[11] -> IMA2.T4(Mode0) || R3: M[11] -> IMA3.T1(Mode0) || IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R0:M[13] -> IMA0.T4(Mode0) || R1: M[12] -> IMA1.T4(Mode0) || R2: M[12] -> IMA2.T1(Mode0) || R3: M[12] -> IMA3.T2(Mode0) || IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R1: M[13] -> IMA1.T1(Mode0) || R2: M[13] -> IMA2.T2(Mode0) || R3: M[13] -> IMA3.T3(Mode0) ||IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
MFetch:LPTO %BLOCK @(KI0 - 0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) ||IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) ||IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) ||IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) ||IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) ||IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) ||IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) ||IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) ||IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BLOCK:
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
MFetch:REPEAT @(35);
MFetch:MPU.STOP;

118
MicroCode/Block_Transform/src/mpu0/Transform8.m0.asm Normal file
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@ -0,0 +1,118 @@
.section .text.m0, "ax"
.file "Transform8Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global Transform8Asm
//need modify
Transform8Asm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0); //KI
BIU1:Load(T0)(A++) -> M[1](Mode0); //ShiftMode
BIU1:Load(T0)(A++) -> M[2](Mode0); //Input
BIU1:Load(T0)(A++) -> M[3](Mode0); //Output
BIU1:Load(T0)(A++) -> M[10](Mode0); //factor1
BIU1:Load(T0)(A++) -> M[11](Mode0); //factor2
BIU1:Load(T0)(A++) -> M[12](Mode0); //factor3
BIU1:Load(T0)(A++) -> M[13](Mode0); //factor4
BIU1:Load(T0)(A++) -> M[14](Mode0); //factor5
BIU1:Load(T0)(A++) -> M[15](Mode0); //factor6
BIU1:Load(T0)(A++) -> M[16](Mode0) || R5:PreConfig(M[0])(Mode0);//factor 7
BIU1:Load(T0)(A++) -> M[17](Mode0) || R0:M[1] -> IMA0.T0(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0);//factor 8
R0:M[1] -> IMA1.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0) || R5:WriteConf(Mfetch)->KI[4-7](Mode0);
R2:M[1] -> IMA2.T0(Mode0) || R3:M[3] -> BIU3.T1(Mode0) ;
R0:M[10] -> IMA0.T1(Mode0) ||R2:M[1] -> IMA3.T0(Mode0) ;
R0:M[11] -> IMA0.T2(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || R2: M[10] -> IMA2.T3(Mode0) || R3: M[10] -> IMA3.T4(Mode0) || IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);//load factor to IMA
R0:M[12] -> IMA0.T3(Mode0) || R1: M[11] -> IMA1.T3(Mode0) || R2: M[11] -> IMA2.T4(Mode0) ||IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R0:M[13] -> IMA0.T4(Mode0) || R1: M[12] -> IMA1.T4(Mode0) || IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA3:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
R3: M[15] -> IMA3.T1(Mode0);
R2: M[16] -> IMA2.T1(Mode0) || R3: M[16] -> IMA3.T2(Mode0);
R1: M[17] -> IMA1.T1(Mode0) || R2: M[17] -> IMA2.T2(Mode0) || R3: M[17] -> IMA3.T3(Mode0);
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || R0: wait 10 || R1: wait 10 || R2: wait 10 || R3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
MFetch:LPTO %BLOCK_0 @(KI0 - 0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || R0: M[14] -> IMA0.T1(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || R1: M[13] -> IMA1.T1(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || R2: M[12] -> IMA2.T1(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || R3: M[11] -> IMA3.T1(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || R0: M[15] -> IMA0.T2(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || R1: M[14] -> IMA1.T2(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || R2: M[13] -> IMA2.T2(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || R3: M[12] -> IMA3.T2(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[16] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[15] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[14] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[13] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[17] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[16] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[15] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[14] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[10] -> IMA0.T1(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[17] -> IMA1.T1(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[16] -> IMA2.T1(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[15] -> IMA3.T1(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[11] -> IMA0.T2(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[10] -> IMA1.T2(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[17] -> IMA2.T2(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[16] -> IMA3.T2(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[12] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[11] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[10] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[17] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0)|| R0: M[13] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0)|| R1: M[12] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0)|| R2: M[11] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0)|| R3: M[10] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BLOCK_0:
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R0: wait 0 || R1: wait 0 || R2: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
MFetch:REPEAT @(20);
R0:M[14] -> IMA0.T1(Mode0) || R1:M[13] -> IMA1.T1(Mode0) || R2:M[12] -> IMA2.T1(Mode0) || R3:M[11] -> IMA3.T1(Mode0);
R0:M[15] -> IMA0.T2(Mode0) || R1:M[14] -> IMA1.T2(Mode0) || R2:M[13] -> IMA2.T2(Mode0) || R3:M[12] -> IMA3.T2(Mode0);
R0:M[16] -> IMA0.T3(Mode0) || R1:M[15] -> IMA1.T3(Mode0) || R2:M[14] -> IMA2.T3(Mode0) || R3:M[13] -> IMA3.T3(Mode0);
R0:M[17] -> IMA0.T4(Mode0) || R1:M[16] -> IMA1.T4(Mode0) || R2:M[15] -> IMA2.T4(Mode0) || R3:M[14] -> IMA3.T4(Mode0);
BIU2:wait 0 || IMA0: wait 10 ||IMA1: wait 10 || IMA2: wait 10 || IMA3: wait 10 || R0: wait 10 || R1: wait 10 || R2: wait 10 || R3: wait 10 || SHU0: wait 14 || SHU1: wait 14 || SHU2: wait 14 || SHU3: wait 14 ||BIU3: wait 17;
MFetch:LPTO %BLOCK_1 @(KI0 - 0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0) || R0: M[10] -> IMA0.T1(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0) || R1: M[17] -> IMA1.T1(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0) || R2: M[16] -> IMA2.T1(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0) || R3: M[15] -> IMA3.T1(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T1(Mode0) || R0: M[11] -> IMA0.T2(Mode0) || SHU0: T0+T1(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T1(Mode0) || R1: M[10] -> IMA1.T2(Mode0) || SHU1: T0+T1(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T1(Mode0) || R2: M[17] -> IMA2.T2(Mode0) || SHU2: T0+T1(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T1(Mode0) || R3: M[16] -> IMA3.T2(Mode0) || SHU3: T0+T1(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[12] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[11] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[10] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[17] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[13] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[12] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[11] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[10] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[14] -> IMA0.T1(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[13] -> IMA1.T1(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[12] -> IMA2.T1(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T1*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[11] -> IMA3.T1(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[15] -> IMA0.T2(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[14] -> IMA1.T2(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[13] -> IMA2.T2(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T2*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[12] -> IMA3.T2(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU0.T0(Mode0)|| R0: M[16] -> IMA0.T3(Mode0) || SHU0: T2+T0(S) -> SHU0.T2(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU1.T0(Mode0)|| R1: M[15] -> IMA1.T3(Mode0) || SHU1: T2+T0(S) -> SHU1.T2(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU2.T0(Mode0)|| R2: M[14] -> IMA2.T3(Mode0) || SHU2: T2+T0(S) -> SHU2.T2(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3:0 + T3*T0(ShiftMode0)(C)(S)(SSS)(T) ->SHU3.T0(Mode0)|| R3: M[13] -> IMA3.T3(Mode0) || SHU3: T2+T0(S) -> SHU3.T2(Mode0);
BIU2:Load(T0) -> IMA0.T0(Mode0) || IMA0: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU0.T0(Mode0)|| R0: M[17] -> IMA0.T4(Mode0) || SHU0: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA1.T0(Mode0) || IMA1: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU1.T0(Mode0)|| R1: M[16] -> IMA1.T4(Mode0) || SHU1: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0) -> IMA2.T0(Mode0) || IMA2: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU2.T0(Mode0)|| R2: M[15] -> IMA2.T4(Mode0) || SHU2: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BIU2:Load(T0)(A++) -> IMA3.T0(Mode0) || IMA3: 0 + T4*T0(ShiftMode0)(C)(S)(SSS)(T) -> SHU3.T0(Mode0)|| R3: M[14] -> IMA3.T4(Mode0) || SHU3: T2+T0(S) -> BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
BLOCK_1:
BIU2:wait 0 || IMA0: wait 0 ||IMA1: wait 0 || IMA2: wait 0 || IMA3: wait 0 || R0: wait 0 || R1: wait 0 || R2: wait 0 || R3: wait 0 || SHU0: wait 0 || SHU1: wait 0 || SHU2: wait 0 || SHU3: wait 0 || BIU3: wait 0;
MFetch:REPEAT @(35);
MFetch:MPU.STOP;

414
MicroCode/Block_Transform/src/spu/Transform.s.c Normal file
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#include <stdlib.h>
#include <math.h>
#include <Transform.h>
#define PI 3.1415926
#define imag(x) (x&0xffff)<<16
#define real(x) x&0xffff
//factor range in [0~1]
void GenParam(double thita[], int* i_real,int* i_imag, int degree,int direct){
switch(degree){
case(2):
{
double p_real[2] = {0};
double p_imag[2] = {0};
double G1_I[2] = { cos(thita[0]), cos(thita[0]) };
double G1_Q[2] = { sin(thita[0]), sin(thita[0]) };
double G2_I[2] = { cos(thita[1]),-cos(thita[1]) };
double G2_Q[2] = { sin(thita[1]), -sin(thita[1]) };
double I[2];
double Q[2];
I[0] = (G1_I[0] + G2_I[0]) / 2;
Q[0] = (G1_Q[0] + G2_Q[0]) / 2;
I[1] = (G1_I[1] + G2_I[1]) / 2;
Q[1] = (G1_Q[1] + G2_Q[1]) / 2;
for(int j = 0;j<2;j++){
p_real[j] = I[j];
p_imag[j] = Q[j];
}
//now convert double to int
for(int j=0; j<2; j++)
{
//i_real[j] = (int)(p_real[j]*16384);
//i_imag[j] = (int)(p_imag[j]*16384);
i_real[j] = (int)(p_real[j]*4096);
i_imag[j] = (int)(p_imag[j]*4096);
}
break;
}
case(4):
{
double p_real[4] = {0};
double p_imag[4] = {0};
double G1_I[4] = { cos(thita[0]), cos(thita[0]) ,cos(thita[0]), cos(thita[0])};//[1 1 1 1]
double G1_Q[4] = { sin(thita[0]), sin(thita[0]) ,sin(thita[0]), sin(thita[0])};
double G2_I[4] = { cos(thita[1]),-sin(thita[1]) ,-cos(thita[1]) ,sin(thita[1]) };//[1 i -1 -i]
double G2_Q[4] = { sin(thita[1]),cos(thita[1]) ,-sin(thita[1]) ,-cos(thita[1]) };
double G3_I[4] = { cos(thita[2]), -cos(thita[2]),cos(thita[2]), -cos(thita[2]) };//[1 -1 1 -1]
double G3_Q[4] = { sin(thita[2]), -sin(thita[2]),sin(thita[2]), -sin(thita[2]) };
double G4_I[4] = { cos(thita[3]), sin(thita[3]), -cos(thita[3]) , -sin(thita[3]) };//[1 -i -1 i]
double G4_Q[4] = { sin(thita[3]), -cos(thita[3]), -sin(thita[3]), cos(thita[3]) };
double I[4];
double Q[4];
for(int i =0;i<4;i++){
I[i] = (G1_I[i] + G2_I[i] + G3_I[i] + G4_I[i]) / 4;
Q[i] = (G1_Q[i] + G2_Q[i] + G3_Q[i] + G4_Q[i]) / 4;
}
if(direct == 1){
p_imag[0] = Q[0];
p_real[0] = I[0];
p_imag[1] = Q[3];
p_real[1] = I[3];
p_imag[2] = Q[2];
p_real[2] = I[2];
p_imag[3] = Q[1];
p_real[3] = I[1];
}
else{
for(int j = 0;j<4;j++){
//p_real[j] = (G1_I[j] + G2_I[j] + G3_I[j] + G4_I[j]) / 4;
//p_imag[j] = (G1_Q[j] + G2_Q[j] + G3_Q[j] + G4_Q[j]) / 4;//conj
p_real[j] = I[j];
p_imag[j] = Q[j];
}
}
//now convert double to int
for(int j=0; j<4; j++)
{
//i_real[j] = (int)(p_real[j]*16384);
//i_imag[j] = (int)(p_imag[j]*16384);
i_real[j] = (int)(p_real[j]*4096);
i_imag[j] = (int)(p_imag[j]*4096);
}
break;
}
case(8):
{
double p_real[8] = {0};
double p_imag[8] = {0};
double G1_I[4] = { cos(thita[0]), cos(thita[0]) ,cos(thita[0]), cos(thita[0])};//[1 1 1 1]
double G1_Q[4] = { sin(thita[0]), sin(thita[0]) ,sin(thita[0]), sin(thita[0])};
double G2_I[4] = { cos(thita[1]),-sin(thita[1]) ,-cos(thita[1]) ,sin(thita[1]) };//[1 i -1 -i]
double G2_Q[4] = { sin(thita[1]),cos(thita[1]) ,-sin(thita[1]) ,-cos(thita[1]) };
double G3_I[4] = { cos(thita[2]), -cos(thita[2]),cos(thita[2]), -cos(thita[2]) };//[1 -1 1 -1]
double G3_Q[4] = { sin(thita[2]), -sin(thita[2]),sin(thita[2]), -sin(thita[2]) };
double G4_I[4] = { cos(thita[3]), sin(thita[3]), -cos(thita[3]) , -sin(thita[3]) };//[1 -i -1 i]
double G4_Q[4] = { sin(thita[3]), -cos(thita[3]), -sin(thita[3]), cos(thita[3]) };
double I[8];
double Q[8];
for(int j=0; j<4; j++)
{
I[2*j] = (G1_I[j] + G2_I[j]) / 4;
Q[2*j] = (G1_Q[j] + G2_Q[j]) / 4;
I[2*j+1] = (G3_I[j] + G4_I[j]) / 4;
Q[2*j+1] = (G3_Q[j] + G4_Q[j]) / 4;
}
if(direct == 1){
p_imag[0] = Q[0];
p_real[0] = I[0];
p_imag[1] = Q[7];
p_real[1] = I[7];
p_imag[2] = Q[6];
p_real[2] = I[6];
p_imag[3] = Q[5];
p_real[3] = I[5];
p_imag[4] = Q[4];
p_real[4] = I[4];
p_imag[5] = Q[3];
p_real[5] = I[3];
p_imag[6] = Q[2];
p_real[6] = I[2];
p_imag[7] = Q[1];
p_real[7] = I[1];
}
else{
for(int j = 0;j<8;j++){
p_real[j] = I[j];
p_imag[j] = Q[j];
}
}
//now convert double to int
for(int j=0; j<8; j++)
{
//i_real[j] = (int)(p_real[j]*16384);
//i_imag[j] = (int)(p_imag[j]*16384);
i_real[j] = (int)(p_real[j]*4096);
i_imag[j] = (int)(p_imag[j]*4096);
}
break;
}
}
}
void get_thita(int* current_state, double* thita)
{
int tmp = (current_state[0] + current_state[4]) % 2;
for (int i = 1; i < 9; i++)
{
current_state[i - 1] = current_state[i];
}
current_state[8] = tmp;
int* p = current_state + 9;
tmp = (p[0] + p[2]) % 2;
for (int i = 1; i < 11; i++)
{
p[i - 1] = p[i];
}
p[10] = tmp;
p += 11;
tmp = (p[0] + p[1]+p[3]+p[4]) % 2;
for (int i = 1; i < 13; i++)
{
p[i - 1] = p[i];
}
p[12] = tmp;
thita[0] = 0;
for (int i = 0; i < 3; i++)
{
thita[0] += current_state[i] << i;
}
thita[0] = thita[0] / 8 * 2 * PI;
thita[1] = 0;
for (int i = 0; i < 3; i++)
{
thita[1] += current_state[i+4] << i;
}
thita[1] = thita[1] / 8 * 2 * PI;
thita[2] = 0;
for (int i = 0; i < 3; i++)
{
thita[2] += current_state[i + 7] << i;
}
thita[2] = thita[2] / 8 * 2 * PI;
thita[3] = 0;
for (int i = 0; i < 3; i++)
{
thita[3] += current_state[i + 10] << i;
}
thita[3] = thita[3] / 8 * 2 * PI;
thita[4] = 0;
for (int i = 0; i < 3; i++)
{
thita[4] += current_state[i + 13] << i;
}
thita[4] = thita[4] / 8 * 2 * PI;
thita[5] = 0;
for (int i = 0; i < 3; i++)
{
thita[4] += current_state[i + 16] << i;
}
thita[4] = thita[4] / 8 * 2 * PI;
}
int sign_extend_16_to_32(int num)
{
return (num<<16)>>16;
}
void Transform(int ConfigAddr, int InAddr, int OutAddr, int N, double* thita, int direct)
{
volatile int a;
int *Para = (int *)ConfigAddr;
int i_real[8] = {0};
int i_imag[8] = {0};
GenParam(thita,i_real,i_imag,N,direct);
switch(N)
{
case(2):
{
for(int i=0;i<2;i++){
for(int j=0;j<16;j++){
Para[16*(i+4) + j] = (real(i_real[i])) + (imag(i_imag[i]));
}
}
for(int i=0;i<2;i++){
//Para[i] = 1792;//3584/2
Para[i] = 224;//14*512/(2*16)
}
Para[16*2 + 0] = InAddr; //KB0
Para[16*2 + 1] = InAddr; //KB1
Para[16*2 + 2] = InAddr; //KB2
Para[16*2 + 3] = InAddr; //KB3
//Para[16*2 + 4] = 114688; //KS0
Para[16*2 + 4] = 14336; //KS0 7*512*32/8
//Para[16*2 + 5] = 16384; //KS1
Para[16*2 + 5] = 2048; //KS1 512*32/8
Para[16*2 + 6] = 64; //KS2
Para[16*2 + 7] = 0; //KS3
Para[16*2 + 8] = (2<<16) + 2; //KC0 KI0
Para[16*2 + 9] = (7<<16) + 7; //KC1 KI1
//Para[16*2 + 10] = (256<<16) + 256; //KC2 KI2
Para[16*2 + 10] = (32<<16) + 32; //KC2 KI2 512/16
Para[16*3 + 0] = OutAddr; //KB0
Para[16*3 + 1] = OutAddr; //KB1
Para[16*3 + 2] = OutAddr; //KB2
Para[16*3 + 4] = 14336; //KS0
Para[16*3 + 5] = 2048; //KS1
Para[16*3 + 6] = 64; //KS2
Para[16*3 + 8] = (2<<16) + 2; //KC0 KI0
Para[16*3 + 9] = (7<<16) + 7; //KC1 KI1
Para[16*3 + 10] = (32<<16) + 32; //KC2 KI2
break;
}
case(4):
{
for(int i=0;i<4;i++){
for(int j=0;j<16;j++){
Para[16*(i+4) + j] = (real(i_real[i])) + (imag(i_imag[i]));
}
}
for(int i=0;i<4;i++){
//Para[i] = 896;//3584/4
Para[i] = 128;//4096*2/(4*16)
}
Para[16*2 + 0] = InAddr; //KB0
Para[16*2 + 1] = InAddr; //KB1
Para[16*2 + 2] = InAddr; //KB2
Para[16*2 + 3] = InAddr; //KB3
Para[16*2 + 4] = 4096; //KS0
Para[16*2 + 5] = 64; //KS1
Para[16*2 + 6] = 16384; //KS2
Para[16*2 + 7] = 0; //KS3
Para[16*2 + 8] = (4<<16) + 4; //KC0 KI0
Para[16*2 + 9] = (64<<16) + 64; //KC1 KI1
//Para[16*2 + 10] = (14<<16) + 14; //KC2 KI2
Para[16*2 + 10] = (2<<16) + 2; //KC2 KI2 change to 2 one time handle 2 row
Para[16*3 + 0] = OutAddr; //KB0
Para[16*3 + 1] = OutAddr; //KB1
Para[16*3 + 2] = OutAddr; //KB2
Para[16*3 + 4] = 4096; //KS0
Para[16*3 + 5] = 64; //KS1
Para[16*3 + 6] = 16384; //KS2
Para[16*3 + 8] = (4<<16) + 4; //KC0 KI0
Para[16*3 + 9] = (64<<16) + 64; //KC1 KI1
//Para[16*3 + 10] = (14<<16) + 14; //KC2 KI2
Para[16*3 + 10] = (2<<16) + 2; //KC2 KI2
break;
}
case(8):
{
for(int i=0;i<N;i++){
for(int j=0;j<16;j++){
Para[16*(i+4) + j] = (real(i_real[i])) + (imag(i_imag[i]));
}
}
for(int i=0;i<N;i++){
Para[i] = 8;//64/8
}
Para[16*2 + 0] = InAddr; //KB0
Para[16*2 + 1] = InAddr; //KB1
Para[16*2 + 2] = InAddr; //KB2
Para[16*2 + 3] = InAddr; //KB3
Para[16*2 + 4] = 512; //KS0
Para[16*2 + 5] = 64; //KS1
Para[16*2 + 6] = 0; //KS2
//Para[16*2 + 7] = 0; //KS3
Para[16*2 + 8] = (8<<16) + 8; //KC0 KI0
Para[16*2 + 9] = (8<<16) + 8; //KC1 KI1
Para[16*2 + 10] = (8<<16) + 8; //KC2 KI2
Para[16*3 + 0] = OutAddr; //KB0
Para[16*3 + 1] = OutAddr; //KB1
Para[16*3 + 2] = OutAddr; //KB2
Para[16*3 + 4] = 512; //KS0
Para[16*3 + 5] = 64; //KS1
Para[16*3 + 6] = 2048; //KS2
Para[16*3 + 8] = (4<<16) + 4; //KC0 KI0
Para[16*3 + 9] = (8<<16) + 8; //KC1 KI1
Para[16*3 + 10] = (2<<16) + 2; //KC2 KI2
/*
Para[16*3 + 0] = OutAddr; //KB0
Para[16*3 + 1] = OutAddr; //KB1
Para[16*3 + 2] = OutAddr; //KB2
Para[16*3 + 4] = 64; //KS0
Para[16*3 + 5] = 512; //KS1
//Para[16*3 + 6] = 0; //KS2
Para[16*3 + 8] = (8<<16) + 8; //KC0 KI0
Para[16*3 + 9] = (8<<16) + 8; //KC1 KI1
//Para[16*3 + 10] = 0; //KC2 KI2
*/
break;
}
}
}
void RowCopy(int* Matrix,int* Block,int idx,int direct)
{
int RowOffset = 4096*2;
//idx from 0 to 6
int BaseAddr = RowOffset*idx;
if(direct == 1)
{
//load data from Matrix
for(int i = BaseAddr;i<BaseAddr+RowOffset;i++)
{
Block[i-BaseAddr] = Matrix[i];
}
}
else
{
//store data to Matrix
for(int i = BaseAddr;i<BaseAddr+RowOffset;i++)
{
Matrix[i] = Block[i-BaseAddr];
}
}
}
void ColCopy(int* Matrix,int* Block,int idx,int direct)
{
int ColOffset = 512;
int RowOffset = 4096;
int BaseAddr = idx*ColOffset;
if(direct == 1)
{
for(int i = 0;i<14;i++){
for(int j = 0;j<ColOffset;j++)
{
Block[j+i*ColOffset] = Matrix[BaseAddr+i*RowOffset+j];
}
}
}
else
{
for(int i = 0;i<14;i++){
for(int j = 0;j<ColOffset;j++)
{
Matrix[BaseAddr+i*RowOffset+j] = Block[j+i*ColOffset];
}
}
}
}

40
MicroCode/Block_Transform/src/spu/ucp2_utils.s.c Normal file
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#include "ucps2.h"
#include <ucp2_utils.h>
#define MAX_SIZE 256
__DM0 char RESULT[MAX_SIZE];
// Write to RESULT in DM0
void write_to_dm0(char* src, unsigned int size)
{
size = (size > MAX_SIZE) ? MAX_SIZE : size;
for (unsigned int i = 0; i < size; i++) {
RESULT[i] = src[i];
}
}
void print_string(char *string)
{
unsigned int i = 0;
while (string[i] != 0) {
print_char(string[i]);
i++;
}
return;
}
// print one char
void print_char(unsigned char src)
{
char * ptr = (char *)0xffffffff; // Temporary simulator output address
*ptr = src;
return;
}
void print_int(unsigned int src)
{
unsigned int * ptr = (unsigned int *)0xfffffff8; // Temporary simulator output address
*ptr = src;
return;
}

10
MicroCode/Channel_Equ/inc/AddCP.h Normal file
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#ifndef AddCP_H_
#define AddCP_H_
#include "ucps2.h"
MPU_ENTRY void AddCPAsm(v16u32 src);
void AddCP(int ConfigBaseAddr,int Nport,int Nsymbol,int CPLength0,int CPLength1,int InputAddr0,int InputAddr1,int OutputAddr0,int OutputAddr1,int CalAddr);
#endif /* AddCP_H_ */

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MicroCode/Channel_Equ/inc/Equalizer_1port.h Normal file
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#ifndef EQUALIZER_1PORT_H_
#define EQUALIZER_1PORT_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void EQ21Part1Asm(v16u32 src);
MPU_ENTRY void EQ41Part1Asm(v16u32 src);
MPU_ENTRY void EQ1Part2Asm(v16u32 src);
void EQ21Part1(int* ConfigBaseAddr,int NRE,int Nsymbol,int InputAddr0,int InputAddr1,int InputAddr2,int OutputAddr0,int OutputAddr1,int OutputAddr2,int OutputAddr3);
void EQ41Part1(int* ConfigBaseAddr,int NRE,int Nsymbol,int InputAddr0,int InputAddr1,int InputAddr2,int OutputAddr0,int OutputAddr1,int OutputAddr2,int OutputAddr3);
void EQ1Part2(int* ConfigBaseAddr,int NRE,int Nsymbol,int InputAddr0,int InputAddr1,int InputAddr2,int InputAddr3,int OutputAddr0,int OutputAddr1);
#endif /* EQUALIZER_1PORT_H_ */

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#ifndef FFT4096INT32_H_
#define FFT4096INT32_H_
#include "ucps2.h"
MPU_ENTRY void Fft4096Int32Asm(v16s32 SvrReg);
void Fft4096Int32(
int Config,
int numSym,
int Scale,
int *ShiftFactor,
int in_WnAddr,
int io_Addr0,
int io_Addr1,
int io_Addr2,
int io_Addr3,
int out_ScaleAddr0,
int out_ScaleAddr1
);
#endif /* FFT4096INT32_H_ */

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#ifndef IFFT4096_H_
#define IFFT4096_H_
#include "ucps2.h"
MPU_ENTRY void IFFT4096Asm(v16u32 src);
void IFFT4096(int ConfigBaseAddr,int Nsymbol,int Temp0,int Temp1,int InOutAddr0,int InOutAddr1,int CalAddr0,int CalAddr1,int CalAddr2);
#endif /* IFFT4096_H_ */

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#ifndef IFFT4096DATATURN_H_
#define IFFT4096DATATURN_H_
#include "ucps2.h"
MPU_ENTRY void IFFT4096DataTurnAsm(v16u32 src);
void IFFT4096DataTurn(int ConfigBaseAddr,int Nsymbol,int Nport,int InputAddr0,int InputAddr1,int OutputAddr0,int OutputAddr1);
#endif /* IFFT4096DATATURN_H_ */

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.section .text.m0,"ax",@progbits
.file "AddCPAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global AddCPAsm
AddCPAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0); //ConfigMFetch
BIU1:Load(T0)(A++) -> M[1](Mode0); //BIU0.T0_input
BIU1:Load(T0)(A++) -> M[2](Mode0); //BIU1.T0_input
BIU1:Load(T0)(A++) -> M[3](Mode0); //BIU2.T1_output dm0 symbol1
BIU1:Load(T0)(A++) -> M[4](Mode0); //BIU2.T2_output dm0
BIU1:Load(T0)(A++) -> M[5](Mode0); //BIU3.T1_output dm1 symbol1
BIU1:Load(T0)(A++) -> M[6](Mode0); //BIU3.T2_output dm1
BIU1:Load(T0)(A++) -> M[7](Mode0); //BIU0.T1 input cp1
BIU1:Load(T0)(A++) -> M[8](Mode0); //BIU0.T2 input cp2-4
BIU1:Load(T0)(A++) -> M[9](Mode0); //BIU1.T1 input cp1
BIU1:Load(T0)(A++) -> M[10](Mode0); //BIU1.T2 input cp2-4
BIU1:Load(T0)(A++) -> M[11](Mode0); //BIU2.T1 output cp1
BIU1:Load(T0)(A++) -> M[12](Mode0); //BIU2.T2 output cp2-4
BIU1:Load(T0)(A++) -> M[13](Mode0); //BIU3.T1 output cp1
BIU1:Load(T0)(A++) -> M[14](Mode0); //BIU3.T2 output cp2-4
BIU1:Load(T0)(A++) -> M[15](Mode0); //BIU0.T3 input phase factor
BIU1:Load(T0)(A++) -> M[16](Mode0); //index1
BIU1:Load(T0)(A++) -> M[17](Mode0); //index2
BIU1:Load(T0)(A++) -> M[20](Mode0);
R5:PreConfig(M[0])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R5:PreConfig(M[0])(Mode0);
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
R0:M[1] -> BIU0.T0(Mode0)||R1:M[2] -> BIU1.T0(Mode0);
R2:M[3] -> BIU2.T1(Mode0)||R3:M[5] -> BIU3.T1(Mode0);
R2:M[4] -> BIU2.T2(Mode0)||R3:M[6] -> BIU3.T2(Mode0);
R0:M[7] -> BIU0.T1(Mode0)||R1:M[9] -> BIU1.T1(Mode0);
R0:M[8] -> BIU0.T2(Mode0)||R1:M[10] -> BIU1.T2(Mode0);
R1:M[20] -> IMA1.T0(Mode0)|| R2:M[20] -> IMA2.T0(Mode0);
R0:M[15] -> BIU0.T3(Mode0);
R1:M[16] -> SHU1.T6(Mode0)|| R2:M[16] -> SHU2.T6(Mode0);
R1:M[17] -> SHU1.T7(Mode0)|| R2:M[17] -> SHU2.T7(Mode0)|| IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
NOP;
BIU0:Load(T3)(A++) -> SHU1.T0(Mode0);
BIU0:Load(T3)(A++) -> SHU2.T0(Mode0);
MFetch:REPEAT @(9);
BIU0:Wait 0 || BIU1:Wait 0 || IMA1: Wait 10 || IMA2: Wait 10 || BIU2:Wait 15 || BIU3:Wait 15 ;
SHU1:Index(T0,T7)(T7=T7+T6) -> IMA1.T2 (Mode0)|| SHU2:Index(T0,T7)(T7=T7+T6) -> IMA2.T2 (Mode0);
MFetch:LPTO %AddCPAsmCyc0 @(KI1 - 0); //dm0/dm1 symbol1
BIU0:Load(T0)(A++) -> IMA1.T0(Mode0) || IMA1: 0 + T0*T2(ShiftMode0)(C)(S)(SSS)(P) -> BIU2.T0 (Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || BIU1:Load(T0)(A++) -> IMA2.T0(Mode0) || IMA2: 0 + T0*T2(ShiftMode0)(C)(S)(SSS)(P) -> BIU3.T0 (Mode0) || BIU3:Store(T0,T1)(A++)(Mode0);
AddCPAsmCyc0:
MFetch:REPEAT @(28);
MFetch:IF(KI0 ==KI7) JUMP %AddCPAsm4ant;
MFetch:LPTO %AddCPAsmCyc1 @(KI0 - 0); //symbol2-4
SHU1:Index(T0,T7)(T7=T7+T6) -> IMA1.T2 (Mode0)|| SHU2:Index(T0,T7)(T7=T7+T6) -> IMA2.T2 (Mode0);
MFetch:LPTO %AddCPAsmCyc2 @(KI1 - 0);
BIU0:Load(T0)(A++) -> IMA1.T0(Mode0)|| IMA1: 0 + T0*T2(ShiftMode0)(C)(S)(SSS)(P) -> BIU2.T0 (Mode0)|| BIU2:Store(T0,T2)(A++)(Mode0)|| BIU1:Load(T0)(A++) -> IMA2.T0(Mode0)|| IMA2: 0 + T0*T2(ShiftMode0)(C)(S)(SSS)(P) -> BIU3.T0 (Mode0)|| BIU3:Store(T0,T2)(A++)(Mode0);
AddCPAsmCyc2:
MFetch:REPEAT @(17);
AddCPAsmCyc1:
AddCPAsm4ant:
BIU0:Wait 0 || BIU1:Wait 0 || BIU2:Wait 0 || BIU3:Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || IMA2: Wait 0 || IMA3: Wait 0 || R0:Wait 0 || R1:Wait 0 || R2:Wait 0 || R3:Wait 0 || SHU0:Wait 0 || SHU1:Wait 0 || SHU2:Wait 0 || SHU3:Wait 0 ;
MFetch:REPEAT @(17);
//add cp
R2:M[11] -> BIU2.T1(Mode0) || R3:M[13] -> BIU3.T1(Mode0);
R2:M[12] -> BIU2.T2(Mode0) || R3:M[14] -> BIU3.T2(Mode0);
BIU0:Wait 0 || BIU1:Wait 0 || R2:Wait 9 || R3:Wait 9 || BIU2:Wait 13 || BIU3:Wait 13 ;
//cp1
MFetch:LPTO %AddCPAsmCyc3 @(KI2 - 0); //dm0 symbol1
BIU0:Load(T1)(A++) -> M[1](Mode0)|| R2:M[1] -> BIU2.T0(Mode0)|| BIU2:Store(T0,T1)(A++)(Mode0);
BIU0:Load(T1)(A++) -> M[1](Mode0)|| R2:M[1] -> BIU2.T0(Mode0)|| BIU2:Store(T0,T1)(A++)(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
AddCPAsmCyc3:
MFetch:LPTO %AddCPAsmCyc4 @(KI4 - 0); //dm1 symbol1
BIU1:Load(T1)(A++) -> M[1](Mode0)|| R3:M[1] -> BIU3.T0(Mode0)|| BIU3:Store(T0,T1)(A++)(Mode0);
BIU1:Load(T1)(A++) -> M[1](Mode0)|| R3:M[1] -> BIU3.T0(Mode0)|| BIU3:Store(T0,T1)(A++)(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
AddCPAsmCyc4:
MFetch:IF(KI0 ==KI7) JUMP %AddCPAsm5ant;
//cp2-4
MFetch:LPTO %AddCPAsmCyc5 @(KI0 - 0); //dm0 and dm1 symbol 2-4
MFetch:LPTO %AddCPAsmCyc6 @(KI3 - 0);
BIU0:Load(T2)(A++) -> M[1](Mode0)|| R2:M[1] -> BIU2.T0(Mode0)|| BIU2:Store(T0,T2)(A++)(Mode0)|| BIU1:Load(T2)(A++) -> M[32](Mode0)|| R3:M[32] -> BIU3.T0(Mode0)|| BIU3:Store(T0,T2)(A++)(Mode0);
BIU0:Load(T2)(A++) -> M[1](Mode0)|| R2:M[1] -> BIU2.T0(Mode0)|| BIU2:Store(T0,T2)(A++)(Mode0)|| BIU1:Load(T2)(A++) -> M[32](Mode0)|| R3:M[32] -> BIU3.T0(Mode0)|| BIU3:Store(T0,T2)(A++)(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
AddCPAsmCyc6:
AddCPAsmCyc5:
AddCPAsm5ant:
BIU0:Wait 0 || BIU1:Wait 0 || BIU2:Wait 0 || BIU3:Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || IMA2: Wait 0 || IMA3: Wait 0 || R0:Wait 0 || R1:Wait 0 || R2:Wait 0 || R3:Wait 0 || SHU0:Wait 0 || SHU1:Wait 0 || SHU2:Wait 0 || SHU3:Wait 0 ;
MFetch:REPEAT @(25);
MFetch:MPU.STOP;

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.section .text.m0, "ax"
.file "EQ1Part2Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global EQ1Part2Asm
EQ1Part2Asm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[112](W1)(Mode0) || IMA3:V(0xff)->IMA3.T0(Mode0) || IMA2:V(0xff)->IMA2.T0(Mode0);//ki
BIU1:Load(T0)(A++) -> M[1](W1)(Mode0);//input invHH'
BIU1:Load(T0)(A++) -> M[2](W1)(Mode0) || IMA3:VHigh(T0,0)->IMA3.T0(Mode0) || IMA2:VHigh(T0,0)->IMA2.T0(Mode0);//input MF
BIU1:Load(T0)(A++) -> M[3](W1)(Mode0);//intput Qtemp0 QMF
BIU1:Load(T0)(A++) -> M[4](W1)(Mode0) || IMA3:SetShiftMode(T0)->ShiftMode0(Mode0) || IMA2:SetShiftMode(T0)->ShiftMode0(Mode0);//input H'H>>13
BIU1:Load(T0)(A++) -> M[5](W1)(Mode0);//output EQ
BIU1:Load(T0)(A++) -> M[6](W1)(Mode0) || IMA2:V(0x11)->IMA2.T3(Mode0) || IMA3:V(0x10)->IMA3.T3(Mode0);//output gainMMSE
BIU1:Load(T0)(A++) -> M[7](W1)(Mode0);//shut6
BIU1:Load(T0)(A++) -> M[8](W1)(Mode0) || IMA2:VHigh(T3,0)->IMA2.T3(Mode0) || IMA3:VHigh(T3,0)->IMA3.T3(Mode0);//shut7
BIU1:Load(T0)(A++) -> M[9](W1)(Mode0);//set Mreg SIA
BIU1:Load(T0)(A++) -> M[10](W1)(Mode0) || R5:PreConfig(M[112]);//
BIU1:Load(T0)(A++) -> SHU1.T6(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0) || R0:M[1]->BIU0.T0(Mode0);//
R0:M[2]->BIU0.T1(Mode0);
R0:M[3]->BIU0.T2(Mode0);
R1:M[4]->BIU1.T3(Mode0);
R3:M[5]->BIU3.T1(Mode0);
R2:M[6]->BIU2.T1(Mode0);
R0:M[7]->SHU0.T6(Mode0) || R2:M[7]->SHU2.T6(Mode0) || R3:M[7]->SHU3.T6(Mode0);
R0:M[8]->SHU0.T7(Mode0) || R2:M[8]->SHU2.T7(Mode0) || R3:M[8]->SHU3.T7(Mode0);
R0:M[9]->IMA0.T4(Mode0) || R1:M[9]->IMA1.T4(Mode0);
R0:M[10]->IMA0.T5(Mode0) || R1:M[10]->IMA1.T5(Mode0);
//cycle
BIU0:Wait 0 || BIU1:Wait 0 || IMA3:Wait 13 || R3:Wait 9 || R6:Wait 14 || SHU3:Wait 18 || IMA0:Wait 20 || SHU0:Wait 27 || BIU3:Wait 30 || R2:Wait 9 || R7:Wait 14 || IMA2:Wait 13 || SHU2:Wait 18 || IMA1:Wait 20 || SHU1:Wait 24 || BIU2:Wait 27;
Mfetch:Lpto %EQPart2AsmCyc @(KI0);
BIU0:Load(T0)(A++) -> M[60](W0)(Mode0) || BIU1:Load(T3)(A++) -> M[70](W1)(Mode0) || IMA3:0+T0*T1(SHIFTMODE0)(C)(S)(SSS)(L) -> SHU3.T0(Mode0) || R3:M[60]->IMA3.T0(Mode0) || R6:M[193]->IMA3.T4(Mode0) || SHU3:Index(T0,T1,T6)->IMA0.T0(Mode0) || IMA0:T0 >> T3(W) -> IMA0.T0 (Mode0) || SHU0:Index(T1,T0,T6)->BIU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mask)(Mode0) || R2:M[60]->IMA2.T0(Mode0) || R7:M[193]->IMA2.T4(Mode0) || IMA2:0+T0*T1(SHIFTMODE0)(S)(SSS)(L)->SHU2.T0(Mode0) || SHU2:Index(T0,T1,T6)->IMA1.T0(Mode0) || IMA1:T0>>T3(W)->IMA1.T0(Mode0) || SHU1:Index(T0,T0,T6)->BIU2.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mask)(Mode0);
BIU0:Load(T1)(A++) -> M[61](W0)(Mode0) || R3:M[61]->IMA3.T1(Mode0) || R6:M[194]->IMA3.T4(Mode0) || SHU3:Index(T0,T1,T7)->IMA0.T1(Mode0) || IMA0:T1 >> T3(W) -> IMA0.T1(Mode0) || R2:M[70]->IMA2.T1(Mode0) || IMA1: CompSel(Ttmp,T4,T4,Ttmp)(w) -> IMA1.T0(Mode0);
BIU0:Load(T2)(A++) -> M[193](W0)(Mode0) || IMA0: CompSel(T0,T4,T4,T0)(w) -> IMA0.T0(Mode0) || IMA1: CompSel(Ttmp,T5,Ttmp,T5)(w) -> SHU1.T0(Mode0);
BIU0:Load(T2)(A++) -> M[194](W0)(Mode0) || IMA0: CompSel(T1,T4,T4,T1)(w) -> IMA0.T1(Mode0);
IMA3:T3-T4(S)->IMA3.T2(Mode0) || IMA0: CompSel(T0,T5,T0,T5)(w) -> SHU0.T0(Mode0) || IMA2:T3-T4(S)->IMA1.T3(Mode0);
IMA3:Ttmp+T4(S)->IMA0.T3(Mode0) || IMA0: CompSel(T1,T5,T1,T5)(w) -> SHU0.T1(Mode0);
EQPart2AsmCyc:
mfetch:repeat @(34);
mfetch: mpu.stop;

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.section .text.m0, "ax"
.file "EQ21Part1Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global EQ21Part1Asm
EQ21Part1Asm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[112](W1)(Mode0) || IMA0:V(0x23d)->IMA0.T0 || IMA1:V(6)->IMA1.T0 || IMA2:V(0x1ff)->IMA2.T5;//ki
BIU1:Load(T0)(A++) -> M[1](W1)(Mode0);//input h
BIU1:Load(T0)(A++) -> M[2](W1)(Mode0) || IMA0:VHigh(T0,0)->IMA0.T0 || IMA1:VHigh(T0,0)->IMA1.T0 || IMA2:VHigh(T5,0)->IMA2.T5;//input noise
BIU1:Load(T0)(A++) -> M[3](W1)(Mode0);//input y
BIU1:Load(T0)(A++) -> M[4](W1)(Mode0) || IMA0:SetShiftMode(T0)->ShiftMode0 || IMA1:SetShiftMode(T0)->ShiftMode0;//out invHH'
BIU1:Load(T0)(A++) -> M[5](W1)(Mode0);//out H'y
BIU1:Load(T0)(A++) -> M[6](W1)(Mode0) || IMA1:V(0xffff)->IMA1.T4;//out Qtemp
BIU1:Load(T0)(A++) -> M[7](W1)(Mode0);//out H'H>>13
BIU1:Load(T0)(A++) -> M[8](W1)(Mode0) || IMA1:VHigh(T4,0)->IMA1.T4;//index t6
BIU1:Load(T0)(A++) -> M[9](W1)(Mode0);//index1 t7
BIU1:Load(T0)(A++) -> M[10](W1)(Mode0) || R5:PreConfig(M[112]);//Set SIA
BIU1:Load(T0)(A++) -> SHU1.T5(Mode0) || R5:WriteConf(Mfetch)->KI[0-3](Mode0)|| R0:M[1]->BIU0.T0(Mode0);
BIU1:Load(T0)(A++) -> SHU1.T0(Mode0) || R0:M[2]->BIU0.T1(Mode0);
BIU1:Load(T0)(A++) -> SHU1.T1(Mode0) || R0:M[3]->BIU0.T2(Mode0);
R1:M[4]->BIU1.T2(Mode0);//out invHH'
R3:M[5]->BIU3.T3(Mode0);//out H'y
R3:M[6]->BIU3.T1(Mode0);//out Qtemp
R2:M[7]->BIU2.T1(Mode0);//out H'H>>13
R0:M[8]->SHU0.T6(Mode0) || R1:M[8]->SHU1.T6(Mode0) || R2:M[8]->SHU2.T6(Mode0) || R3:M[8]->SHU3.T6(Mode0);
R0:M[9]->SHU0.T7(Mode0) || R1:M[9]->SHU1.T7(Mode0) || R2:M[9]->SHU2.T7(Mode0) || R3:M[9]->SHU3.T7(Mode0);
R1:PreConfig(M[10])(Mode0) || R3:PreConfig(M[10])(Mode0);
R1:WriteConf -> MC.W0(I) || R3:WriteConf -> MC.R2(I);
//cycle
BIU0:Wait 0 || R0:Wait 9 || R2:Wait 17 || SHU0:Wait 18 || BIU3:Wait 30 || R3:Wait 26 || IMA0:Wait 12 || SHU3:Wait 29 || SHU2:Wait 21 || BIU1:Wait 37 || IMA1:Wait 29 || SHU1:Wait 26 || IMA2:Wait 20 || IMA3:Wait 22 || BIU2:Wait 26;
Mfetch:Lpto %EQ21Part1AsmCyc0 @(KI0);
BIU0:Load(T0)(A++) -> M[28](W0)(Mode0) || R0:M[28] -> IMA0.T0(Mode0) || R2:M[I++,A++] -> IMA2.T4(Mode0) || SHU0:Index(T0, T1, T6) -> IMA[2,3].T2 (Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[50] -> BIU3.T0(Mode0) || IMA0:0+T0*T0(SHIFTMODE0)(C) (S) (SSS)-> IMA0.MR (Mode0) || SHU3:Index(T3, T2, T7) -> BIU3.T0 (Mode0) || SHU2:Index(T0, T1, T6) -> IMA3.T0 (Mode0) || BIU1:Store(T0,T2)(A++)(Mask)(Mode0) || IMA1:T1 & T4 -> IMA1.T0(Mode0) || SHU1:Index(T2,T5) -> SHU1.T2 (Mode0) || IMA2:T2 + T4 (W) -> IMA2.T1(Mode0) || IMA3:T2 >> 13(W) -> BIU2.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mask)(Mode0);
BIU0:Load(T0)(A++) -> M[29](W0)(Mode0) || R0:M[29] -> IMA0.T1(Mode0) || BIU3:Store(T0,T1)(A++) (Mask)(Mode0) || R3:M[64] -> BIU3.T0(Mode0) || IMA0:MR+T1*T1(SHIFTMODE0)(C) (S) (SSS) (L)-> SHU0.T0(Mode0) || SHU2:Index(T0, T1, T7) -> IMA3.T1(Mode0) || IMA1:0+Ttmp*T5(SHIFTMODE0)(S)(SSS) -> IMA1.T1 (Mode0) || SHU1:Index(T0, T0, T2) -> IMA1.T1 (Mode0) || IMA2:First(Ttmp) (w) -> M[50](w2)&IMA2.T2(Mode0) || IMA3:First(T0) (w) -> IMA3.T4 (Mode0);
BIU0:Load(T2)(A++) -> M[30](W0)(Mode0) || BIU3:Store(T0,T3)(A++) (Mask)(Mode0) || IMA1:T2 & T4 -> IMA1.T2(Mode0) || SHU1:Index(T1, T1, T2) -> IMA1.T2 (Mode0) || IMA2:T1 << Ttmp(W)->IMA2.T1 (Mode0) || IMA3:First(T1) (w) -> IMA3.T4(Mode0);
BIU0:Load(T2)(A++) -> M[31](W0)(Mode0) || R0:M[30] -> IMA0.T4(Mode0) || IMA0:0+T0*T4(SHIFTMODE0)(C) (S) (SSS) -> IMA0.MR (Mode0) || IMA2:Ttmp >> 16(W)->IMA2.T1(Mode0) || IMA3:CompSel(Ttmp,T4,T4,Ttmp) (W)(U) -> M[64](w3)&IMA3.T4(Mode0);
BIU0:Load(T1)(A++)(Mask) -> M[I++,A++](W0)(Mode0) || R0:M[31] -> IMA0.T4(Mode0) || IMA0:MR+T1*T4(SHIFTMODE0)(C) (S) (SSS) (L)-> SHU2.T0(Mode0) || IMA2:Ttmp >> 9(S)(U)->SHU1.T2(Mode0) || IMA3:T0 << Ttmp(W)(T) -> SHU3.T2 (Mode0);
IMA1:T1+T2 (S)->BIU1.T0(Mode0) || IMA2:T1 & T5 -> IMA1.T5(Mode0) || IMA3:T1 << T4(W)(T) -> SHU3.T3(Mode0);
EQ21Part1AsmCyc0:
mfetch:repeat @(41);
mfetch: mpu.stop;

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MicroCode/Channel_Equ/src/mpu0/Fft4096Int32Asm.m0.asm Normal file
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/*
* SrsCalRECorreValueAsm.m0.asm
*
* Created on: Aug 8, 2022
* Author: zhoukangkang
*/
.section .text.m0, "ax"
.file "Fft4096Int32Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global Fft4096Int32Asm
Fft4096Int32Asm:
r1:m[0]->biu1.t1;
nop;
nop;
nop;
biu1:load(t1)(a++)->m[0]; //KIs
biu1:load(t1)(a++)->m[1]; //load(ASI)
biu1:load(t1)(a++)->m[2]; //load(signal)(br)
biu1:load(t1)(a++)->m[3]; //store(fft_1_4)
biu1:load(t1)(a++)->m[4]; //factors
biu1:load(t1)(a++)->m[5]; //load(Wn_1-4)
biu1:load(t1)(a++)->m[6]; //shu(Wn) for fft_2
biu1:load(t1)(a++)->m[7]; //shu(Wn) for fft_3
biu1:load(t1)(a++)->m[8]; //shu(Wn) for fft_4
biu1:load(t1)(a++)->m[9]; /*shu(signal) for fft_1A*/
biu1:load(t1)(a++)->m[10] /*shu(signal) for fft_1B*/ ||r5:preconfig(m[0]);
biu1:load(t1)(a++)->m[11] /*shu(signal) for fft_1A*/ ||r5:writeconf(mfetch)->ki[0-15];
biu1:load(t1)(a++)->m[12] /*shu(signal) for fft_1B*/ ||r0:m[2]->biu0.t0;
biu1:load(t1)(a++)->m[13] /*shu(signal) for fft_2A*/ ||r3:m[3]->biu3.t0 ||ima0:v(0)->ima0.t5;
biu1:load(t1)(a++)->m[14] /*shu(signal) for fft_2B*/ ||r0:m[4]->shu0.t5 ||ima0:vhigh(ttmp,0x0101)->shu0.t2;
biu1:load(t1)(a++)->m[15] /*shu(signal) for fft_3A*/ ||r1:m[5]->biu1.t2;
biu1:load(t1)(a++)->m[16] /*shu(signal) for fft_3B*/ ||r1:m[6]->shu1.t6;
r2:m[7]->shu2.t6;
r3:m[8]->shu3.t6;
biu1:load(t2)(a++)->shu[1,2,3].t0;
biu1:load(t2)(a++)->shu[1,2,3].t1;
r1:preconfig(m[1][0]) ||r3:preconfig(m[1][2]) ||shu0:index(t5,t5,t2)(t7=t2+v(2))->ima0.t0;
r1:writeconf->mc.w0(i) ||r3:writeconf->mc.w2(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima1.t0;
r1:writeconf->mc.r0(i) ||r3:writeconf->mc.r2(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima2.t0 ||ima0:setshiftmode(t0)->shiftmode0;
r1:preconfig(m[1][1]) ||r3:preconfig(m[1][3]) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima3.t0 ||ima1:setshiftmode(t0)->shiftmode0;
r1:writeconf->mc.w1(i) ||r3:writeconf->mc.w3(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima0.t0 ||ima2:setshiftmode(t0)->shiftmode0;
r1:writeconf->mc.r1(i) ||r3:writeconf->mc.r3(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima1.t0 ||ima3:setshiftmode(t0)->shiftmode0;
r1:preconfig(m[1][4]) ||r3:preconfig(m[1][6]) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima2.t0 ||ima0:setshiftmode(t0)->shiftmode1;
r1:writeconf->mc.w4(i) ||r3:writeconf->mc.w6(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima3.t0 ||ima1:setshiftmode(t0)->shiftmode1;
r1:writeconf->mc.r4(i) ||r3:writeconf->mc.r6(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima0.t0 ||ima2:setshiftmode(t0)->shiftmode1 ||ima0:v(0x7fff)->ima0.t2;
r1:preconfig(m[1][5]) ||r3:preconfig(m[1][7]) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima1.t0 ||ima3:setshiftmode(t0)->shiftmode1 ||ima0:vhigh(ttmp,0)->ima0.t2;
r1:writeconf->mc.w5(i) ||r3:writeconf->mc.w7(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima2.t0 ||ima0:setshiftmode(t0)->shiftmode2;
r1:writeconf->mc.r5(i) ||r3:writeconf->mc.r7(i) ||shu0:index(t5,t5,t7)(t7=t7+v(2))->ima3.t0 ||ima1:setshiftmode(t0)->shiftmode2;
shu1:index(t1,t0,t6)->ima1.t2 ||ima2:setshiftmode(t0)->shiftmode2;
shu2:index(t1,t0,t6)->ima2.t2 ||ima3:setshiftmode(t0)->shiftmode2;
shu3:index(t1,t0,t6)->ima3.t2;
r0:m[9]->shu0.t4 ||r1:m[11]->shu1.t4 ||r2:m[13]->shu2.t4 ||r3:m[15]->shu3.t4;
r0:m[10]->shu0.t5 ||r1:m[12]->shu1.t5 ||r2:m[14]->shu2.t5 ||r3:m[16]->shu3.t5;
biu0:wait 0 ||ima0:wait 11 ||shu0:wait 16 ||shu1:wait 20 ||ima1:wait 23 ||shu2:wait 30 ||ima2:wait 33 ||shu3:wait 40 ||ima3:wait 43 ||biu3:wait 49;
mfetch:lpto %cyc_Ant2_FFT_1_4 @(ki3);
mfetch:lpto %cyc_numSym_FFT_1_4 @(ki0);
mfetch:lpto %cyc_FFT_1_4 @(ki1);
biu0:load(t0)(a++)(br)->ima0.t0 ||ima0:t0+t1*t2(shiftmode0)(s)(c)(sss)(l)(p)->shu0.t0 ||shu0:index(t0,t1,t4)->shu1.t0 ||shu1:index(t1,t0,t4)->ima1.t0 ||ima1:t0+t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima1.mr ||shu2:index(t1,t0,t4)->ima2.t0 ||ima2:t0+t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima2.mr ||shu3:index(t1,t0,t4)->ima3.t0 ||ima3:t0+t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima3.mr ||biu3:store(t1,t0)(a++);
biu0:load(t0)(a++)(br)->ima0.t1 ||shu1:index(t1,t0,t5)->ima1.t1 ||ima1:mr+t1*t2(shiftmode0)(c)(ws)(sss)(p)->shu2.t0 ||shu2:index(t1,t0,t5)->ima2.t1 ||ima2:mr+t1*t2(shiftmode0)(c)(ws)(sss)(p)->shu3.t0 ||shu3:index(t1,t0,t5)->ima3.t1 ||ima3:mr+t1*t2(shiftmode0)(c)(ws)(sss)(p)->biu3.t1;
ima0:t0-t1*t2(shiftmode0)(s)(c)(sss)(l)(p)->shu0.t2 ||shu0:index(t2,t3,t4)->shu1.t1 ||ima1:t0-t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima1.mr ||ima2:t0-t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima2.mr ||ima3:t0-t1*t2(shiftmode0)(c)(wf)(sss)(p)->ima3.mr ||biu3:store(t1,t0)(a++);
ima1:mr-t1*t2(shiftmode0)(c)(ws)(sss)(p)->shu2.t1 ||ima2:mr-t1*t2(shiftmode0)(c)(ws)(sss)(p)->shu3.t1 ||ima3:mr-t1*t2(shiftmode0)(c)(ws)(sss)(p)->biu3.t1;
cyc_FFT_1_4:
biu0:t0[11]->t0[0]; //BaseAddr += 4096Words
biu0:t0[11]->t0[1];
biu0:t0[7]+t0[11]->T0[11];
cyc_numSym_FFT_1_4:
biu0:t0[14]->t0[0] ||biu3:t0[11]->t0[0]; //update BaseAddr from io_Addr0/2 to io_Addr1/3
biu0:t0[14]->t0[1] ||biu3:t0[11]->t0[1];
biu0:t0[15]->t0[11] ||biu3:t0[11]->t0[2];
biu3:t0[11]->t0[3];
nop;
cyc_Ant2_FFT_1_4:
biu0:wait 0 ||ima0:wait 0 ||shu0:wait 0 ||shu1:wait 0 ||ima1:wait 0 ||shu2:wait 0 ||ima2:wait 0 ||shu3:wait 0 ||ima3:wait 0 ||biu3:wait 0;
mfetch:repeat @(15);
biu1:load(t1)(a++)->m[17] /*load fft_4 in col, 16 dwords/cow */;
biu1:load(t1)(a++)->m[18] /*store fft_8 in col, 16 dwords/cow */;
biu1:load(t1)(a++)->m[19] /*load Wn_5 */;
biu1:load(t1)(a++)->m[20] /*load Wn_6 */;
biu1:load(t1)(a++)->m[21] /*load Wn_7 */;
biu1:load(t1)(a++)->m[22] /*load Wn_8 */;
biu1:load(t1)(a++)->m[23] /*shu(Wn) for fft_5 */;
biu1:load(t1)(a++)->m[24] /*shu(Wn) for fft_6 */;
biu1:load(t1)(a++)->m[25] /*shu(Wn) for fft_7 */;
biu1:load(t1)(a++)->m[26] /*shu(Wn) for fft_8 */;
biu1:load(t1)(a++)->m[27] /*shu for fft_5A_9A */ ||r0:m[17]->biu0.t2;
biu1:load(t1)(a++)->m[28] /*shu for fft_5B_9B */ ||r3:m[18]->biu3.t2;
biu1:load(t1)(a++)->m[29] /*shu for fft_6A_10A */ ||r0:m[19]->biu0.t3;
biu1:load(t1)(a++)->m[30] /*shu for fft_6B_10B */ ||r1:m[20]->biu1.t3;
biu1:load(t1)(a++)->m[31] /*shu for fft_7A_11A */ ||r2:m[21]->biu2.t3;
biu1:load(t1)(a++)->m[32] /*shu for fft_7B_11B */ ||r3:m[22]->biu3.t3;
biu1:load(t1)(a++)->m[33] /*shu for fft_8A_12A */ ||r0:m[23]->shu0.t2 ||r1:m[23]->shu0.t6;
biu1:load(t1)(a++)->m[34] /*shu for fft_8B_12B */ ||r1:m[24]->shu1.t2;
r2:m[25]->shu2.t2;
r3:m[26]->shu3.t2;
r0:m[27]->shu0.t4;
r0:m[28]->shu0.t5;
r1:m[29]->shu1.t4;
r1:m[30]->shu1.t5;
r2:m[31]->shu2.t4;
r2:m[32]->shu2.t5;
r3:m[33]->shu3.t4;
r3:m[34]->shu3.t5;
biu0:wait 0 ||shu0:wait 10 ||biu1:wait 0 ||shu1:wait 10 ||biu2:wait 0 ||shu2:wait 10 ||biu3:wait 0 ||shu3:wait 10;
biu0:load(t3)(a++)->shu0.t0 ||shu0:index(t0,t0,t2)->m[i++,a++](w0) ||mfetch:repeat @(16);
biu1:load(t3)(a++)->shu1.t0 ||shu1:index(t0,t0,t2)->m[i++,a++](w1) ||mfetch:repeat @(16);
biu2:load(t3)(a++)->shu2.t0 ||shu2:index(t0,t0,t2)->m[i++,a++](w2) ||mfetch:repeat @(16);
biu3:load(t3)(a++)->shu3.t0 ||shu3:index(t0,t0,t2)->m[i++,a++](w3) ||mfetch:repeat @(16);
biu0:wait 0 ||shu0:wait 0 ||biu1:wait 0 ||shu1:wait 0 ||biu2:wait 0 ||shu2:wait 0 ||biu3:wait 0 ||shu3:wait 0;
mfetch:repeat @(12);
biu0:wait 0 ||shu0:wait 11 ||r0:wait 11 ||ima0:wait 14 ||shu1:wait 21 ||r1:wait 21 ||ima1:wait 24 ||shu2:wait 31 ||r2:wait 31 ||ima2:wait 34 ||shu3:wait 41 ||r3:wait 41 ||ima3:wait 44 ||biu3:wait 50;
mfetch:lpto %cyc_Ant2_FFT_5_8 @(ki3);
mfetch:lpto %cyc_numSym_FFT_5_8 @(ki2);
biu0:load(t2)(a++)->shu0.t0 ||shu0:index(t1,t0,t4)->ima0.t0 ||r0:m[i++,a++]->ima0.t2 ||ima0:t0+t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima0.mr ||shu1:index(t1,t0,t4)->ima1.t0 ||r1:m[i++,a++]->ima1.t2 ||ima1:t0+t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima1.mr ||shu2:index(t1,t0,t4)->ima2.t0 ||r2:m[i++,a++]->ima2.t2 ||ima2:t0+t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima2.mr ||shu3:index(t1,t0,t4)->ima3.t0 ||r3:m[i++,a++]->ima3.t2 ||ima3:t0+t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima3.mr ||biu3:store(t1,t2)(a++);
biu0:load(t2)(a++)->shu0.t1 ||shu0:index(t1,t0,t5)->ima0.t1 ||ima0:mr+t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu1.t0 ||shu1:index(t1,t0,t5)->ima1.t1 ||ima1:mr+t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu2.t0 ||shu2:index(t1,t0,t5)->ima2.t1 ||ima2:mr+t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu3.t0 ||shu3:index(t1,t0,t5)->ima3.t1 ||ima3:mr+t1*t2(shiftmode1)(c)(ws)(sss)(p)->biu3.t1;
ima0:t0-t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima0.mr ||ima1:t0-t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima1.mr ||ima2:t0-t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima2.mr ||ima3:t0-t1*t2(shiftmode1)(c)(wf)(sss)(p)->ima3.mr ||biu3:store(t1,t2)(a++);
ima0:mr-t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu1.t1 ||ima1:mr-t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu2.t1 ||ima2:mr-t1*t2(shiftmode1)(c)(ws)(sss)(p)->shu3.t1 ||ima3:mr-t1*t2(shiftmode1)(c)(ws)(sss)(p)->biu3.t1;
cyc_numSym_FFT_5_8:
biu0:t2[11]->t2[0] ||biu3:t2[11]->t2[0]; //update BaseAddr from io_Addr1/3 to io_Addr0/1
biu0:t2[11]->t2[1] ||biu3:t2[11]->t2[1];
biu3:t2[11]->t2[2];
nop;
cyc_Ant2_FFT_5_8:
biu0:wait 0 ||shu0:wait 0 ||r0:wait 0 ||ima0:wait 0 ||shu1:wait 0 ||r1:wait 0 ||ima1:wait 0 ||shu2:wait 0 ||r2:wait 0 ||ima2:wait 0 ||shu3:wait 0 ||r3:wait 0 ||ima3:wait 0 ||biu3:wait 0;
mfetch:repeat @(36);
biu1:load(t1)(a++)->m[35] /*load fft_8 in row, 16 dwords/row */;
biu1:load(t1)(a++)->m[36] /*store fft_12 in row, 16 dwords/row*/;
biu1:load(t1)(a++)->m[37] /*load Wn_9_12_t */;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
r4:m[35]->biu0.t3;
r7:m[36]->biu3.t3;
r5:m[37]->biu1.t3;
nop;
nop;
nop;
biu0:wait 6 ||biu1:wait 0 ||r4:wait 12 ||shu0:wait 15 ||r0:wait 17 ||ima0:wait 20 ||r5:wait 22 ||shu1:wait 25 ||r1:wait 27 ||ima1:wait 30 ||r6:wait 32 ||shu2:wait 35 ||r2:wait 37 ||ima2:wait 40 ||r7:wait 41 ||shu3:wait 45 ||r3:wait 47 ||ima3:wait 50 ||biu3:wait 58;
mfetch:lpto %cyc_Ant2_FFT_9_12 @(ki3);
mfetch:lpto %cyc_numSym_FFT_9_12 @(ki2);
biu0:load(t3)(a++)->shu0.t0 ||biu1:load(t3)(a++)->m[i++,a++](w5) ||r4:m[i++,a++]->shu0.t2 ||shu0:index(t2,t2,t6)->m[128](w0) ||r0:m[128]->ima0.t2 ||ima0:t0+t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima0.mr ||r5:m[i++,a++]->shu1.t2 ||shu1:index(t2,t2,t6)->m[160](w1) ||r1:m[160]->ima1.t2 ||ima1:t0+t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima1.mr ||r6:m[i++,a++]->shu2.t2 ||shu2:index(t2,t2,t6)->m[192](w2) ||r2:m[192]->ima2.t2 ||ima2:t0+t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima2.mr ||r7:m[i++,a++]->shu3.t2 ||shu3:index(t3,t2,t6)->m[224](w3) ||r3:m[224]->ima3.t2 ||ima3:t0+t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima3.mr ||biu3:store(t1,t3)(a++);
biu0:load(t3)(a++)->shu0.t1 ||biu1:load(t3)(a++)->m[i++,a++](w5) ||r4:m[i++,a++]->shu0.t3 ||ima0:mr+t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu1.t0 ||r5:m[i++,a++]->shu1.t3 ||ima1:mr+t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu2.t0 ||r6:m[i++,a++]->shu2.t3 ||ima2:mr+t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu3.t0 ||r7:m[i++,a++]->shu3.t3 ||ima3:mr+t1*t2(shiftmode2)(ws)(c)(sss)(p)->biu3.t1 ||biu3:store(t2,t3)(a++);
shu0:index(t1,t0,t4)->ima0.t0 ||ima0:t0-t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima0.mr ||shu1:index(t1,t0,t4)->ima1.t0 ||ima1:t0-t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima1.mr ||shu2:index(t1,t0,t4)->ima2.t0 ||ima2:t0-t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima2.mr ||shu3:index(t1,t0,t4)->ima3.t0 ||ima3:t0-t1*t2(shiftmode2)(wf)(c)(sss)(p)->ima3.mr;
shu0:index(t1,t0,t5)->ima0.t1 ||ima0:mr-t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu1.t1 ||shu1:index(t1,t0,t5)->ima1.t1 ||ima1:mr-t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu2.t1 ||shu2:index(t1,t0,t5)->ima2.t1 ||ima2:mr-t1*t2(shiftmode2)(ws)(c)(sss)(p)->shu3.t1 ||shu3:index(t1,t0,t5)->ima3.t1 ||ima3:mr-t1*t2(shiftmode2)(ws)(c)(sss)(p)->biu3.t2;
cyc_numSym_FFT_9_12:
biu0:t3[11]->t3[0] ||biu3:t3[11]->t3[0]; //update BaseAddr from io_Addr0/2 to io_Addr1/3
biu0:t3[11]->t3[1] ||biu3:t3[11]->t3[1];
biu0:t3[11]->t3[2] ||biu3:t3[11]->t3[2];
biu0:t3[11]->t3[3] ||biu3:t3[11]->t3[3];
nop;
cyc_Ant2_FFT_9_12:
biu0:wait 0 ||biu1:wait 0 ||r4:wait 0 ||shu0:wait 0 ||r0:wait 0 ||ima0:wait 0 ||r5:wait 0 ||shu1:wait 0 ||r1:wait 0 ||ima1:wait 0 ||r6:wait 0 ||shu2:wait 0 ||r2:wait 0 ||ima2:wait 0 ||r7:wait 0 ||shu3:wait 0 ||r3:wait 0 ||ima3:wait 0 ||biu3:wait 0;
mfetch:repeat @(60);
/**************************************************************************************\
FFT_scale = 13-ceil(log2(double(max(max(abs(real(data_out))),max(abs(imag(data_out))))))) + 6;
= 13 - (31 - min(first1)) + 6 = -(18 - min(first1)) + 6;
FFT_out = fixed.limit(data_out,16, -6 + FFT_scale) = fixed.limit(data_out,16, -(18 - min(first1)));
\**************************************************************************************/
biu1:load(t1)(a++)->m[38] /*load fft_int32_0 in row */ ||ima0:v(0)->ima[0,1,2,3].t5;
biu1:load(t1)(a++)->m[39] /*store 16 MinFirst1_0 in row */ ||ima0:vhigh(ttmp,0x0101)->shu0.t2;
biu1:load(t1)(a++)->m[40] /*load fft_int32_1 in row */ ||ima2:vhigh(t5,0x0101)->shu2.t2;
biu1:load(t1)(a++)->m[41] /*store 16 MinFirst1_1 in row */ ||shu0:t2+v(0)->shu0.t7;
biu1:load(t1)(a++)->m[42] /*load 16 MinFirst1_0 in col */ ||shu2:t2+v(0)->shu2.t7;
biu1:load(t1)(a++)->m[43] /*load 16 MinFirst1_1 in col */;
biu1:load(t1)(a++)->m[44] /*scale = 13 for now */;
biu1:load(t1)(a++)->m[45] /*shu for get fft_int16 */;
biu1:load(t1)(a++)->m[46] /*store fft_int16_0 */;
biu1:load(t1)(a++)->m[47] /*store fft_int16_1 */;
biu1:load(t1)(a++)->m[48] /*copy fft_int16_0 from io_Addr0 */ ||r0:m[38]->biu0.t0;
biu1:load(t1)(a++)->m[49] /*copy fft_int16_0 from io_Addr1 */ ||r1:m[39]->biu1.t0 ||r0:m[38]->biu0.t3;
biu1:load(t1)(a++)->m[50] /*copy fft_int16_0 to io_Addr2 */ ||r2:m[40]->biu2.t0;
biu1:load(t1)(a++)->m[51] /*copy fft_int16_0 to io_Addr3 */ ||r3:m[41]->biu3.t0 ||r2:m[40]->biu2.t3;
biu1:load(t1)(a++)->m[52] /*biu for scale output */ ||r0:m[42]->biu0.t2;
r2:m[43]->biu2.t2;
r0:m[44]->shu0.t0 ||r2:m[44]->shu2.t0;
r1:m[45]->shu1.t2 ||r3:m[45]->shu3.t2;
r1:m[46]->biu1.t3;
r3:m[47]->biu3.t3 ||shu0:index(t0,t0,t2)(T7=T2+V(2))->ima[0,2].t3; //scale for int32 to int16
shu0:index(t0,t0,t7)(T7=T7+V(2))->ima[0,2].t4; //scale for calc output scale
shu0:t2+v(0)->shu0.t7;
biu0:wait 0 ||ima0:wait 10 ||ima1:wait 12 ||biu1:wait 15 ||biu2:wait 0 ||ima2:wait 10 ||ima3:wait 12 ||biu3:wait 15;
mfetch:lpto %cyc_numSym_Min16First1 @(ki0);
biu0:load(t0)(a++)->ima0.t0 ||ima0:first(t0)(w)->ima1.t0 ||ima1:compsel(t0,t5,t0,t5)(w)->ima1.t1 ||biu2:load(t0)(a++)->ima2.t0 ||ima2:first(t0)(w)->ima3.t0 ||ima3:compsel(t0,t5,t0,t5)(w)->ima3.t1;
biu0:load(t0)(a++)->ima0.t0 ||ima0:first(t0)(w)->ima1.t0 ||ima1:compsel(ttmp,t0,t0,ttmp)(w)->ima1.t1 ||biu2:load(t0)(a++)->ima2.t0 ||ima2:first(t0)(w)->ima3.t0 ||ima3:compsel(ttmp,t0,t0,ttmp)(w)->ima3.t1 ||mfetch:repeat @(510);
biu0:load(t0)(a++)->ima0.t0 ||ima0:first(t0)(w)->ima1.t0 ||ima1:compsel(ttmp,t0,t0,ttmp)(w)->biu1.t2 ||biu1:store(t2,t0)(a++) ||biu2:load(t0)(a++)->ima2.t0 ||ima2:first(t0)(w)->ima3.t0 ||ima3:compsel(ttmp,t0,t0,ttmp)(w)->biu3.t2 ||biu3:store(t2,t0)(a++);
cyc_numSym_Min16First1:
biu0:wait 0 ||ima0:wait 0 ||ima1:wait 0 ||biu1:wait 0 ||biu2:wait 0 ||ima2:wait 0 ||ima3:wait 0 ||biu3:wait 0;
mfetch:repeat @(18);
biu0:wait 0 ||ima0:wait 10 ||biu2:wait 0 ||ima2:wait 10;
biu0:load(t2)(a++)->ima0.t0 ||ima0:compsel(t0,t5,t0,t5)(w)->ima0.t2 ||biu2:load(t2)(a++)->ima2.t0 ||ima2:compsel(t0,t5,t0,t5)(w)->ima2.t2;
biu0:load(t2)(a++)->ima0.t0 ||ima0:compsel(t0,ttmp,ttmp,t0)(w)->ima0.t2 ||biu2:load(t2)(a++)->ima2.t0 ||ima2:compsel(t0,ttmp,ttmp,t0)(w)->ima2.t2 ||mfetch:repeat @(15);
ima0:t3-ttmp(w)->shu2.t0 & ima0.t5 ||ima2:t3-ttmp(w)->shu0.t0 & ima2.t5;
biu0:wait 0 ||ima0:wait 0 ||biu2:wait 0 ||ima2:wait 0;
mfetch:repeat @(10);
biu0:wait 0 ||shu2:wait 9 ||ima1:wait 10 ||shu1:wait 12 ||biu1:wait 15 ||biu2:wait 0 ||shu0:wait 9 ||ima3:wait 10 ||shu3:wait 12 ||biu3:wait 15;
mfetch:lpto %cyc_numSym_Scale @(ki0);
shu2:index(t0,t0,t7)(t7=t7+v(2))->ima1.t1 ||shu0:index(t0,t0,t7)(t7=t7+v(2))->ima3.t1;
biu0:load(t3)(a++)->ima1.t0 ||ima1:t0>>t1(w)->shu1.t0 ||shu1:index(t0,t0,t2)->biu1.t2 ||biu1:store(t2,t3)(a++) ||biu2:load(t3)(a++)->ima3.t0 ||ima3:t0>>t1(w)->shu3.t0 ||shu3:index(t0,t0,t2)->biu3.t2 ||biu3:store(t2,t3)(a++) ||mfetch:repeat @(512);
cyc_numSym_Scale:
biu0:wait 0 ||shu2:wait 0 ||ima1:wait 0 ||shu1:wait 0 ||biu1:wait 0 ||biu2:wait 0 ||shu0:wait 0 ||ima3:wait 0 ||shu3:wait 0 ||biu3:wait 0;
mfetch:repeat @(15);
//copy fft_int16 from io_addr0/1 to io_addr2/3
ima0:t4-t5(w)->shu1.t0 ||r0:m[52]->biu0.t3;
ima2:t4-t5(w)->shu3.t0;
shu1:index(t0,t0,t2)->biu0.t1 ||r0:m[48]->biu0.t0 ||r2:m[49]->biu2.t0 ||r1:m[50]->biu1.t0 ||r3:m[51]->biu3.t0;
shu3:index(t0,t0,t2)->biu0.t2;
nop;
biu0:store(t1,t3)(a++); //为下一模块输出标值
biu0:store(t2,t3)(a++);
biu0:wait 0 ||r1:wait 9 ||biu1:wait 13 ||biu2:wait 0 ||r3:wait 9 ||biu3:wait 13;
mfetch:lpto %cyc_numSym_memcpy @(ki0);
biu0:load(t0)(a++)->m[0] ||r1:m[0]->biu1.t1 ||biu1:store(t1,t0)(a++) ||biu2:load(t0)(a++)->m[128]||r3:m[128]->biu3.t1 ||biu3:store(t1,t0)(a++) ||mfetch:repeat @(256);
cyc_numSym_memcpy:
biu0:wait 0 ||r1:wait 0 ||biu1:wait 0 ||biu2:wait 0 ||r3:wait 0 ||biu3:wait 0;
mfetch:repeat @(16);
mfetch:mpu.stop;

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MicroCode/Channel_Equ/src/mpu0/IFFT4096Asm.m0.asm Normal file
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.section .text.m0, "ax"
.file "IFFT4096Asm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global IFFT4096Asm
IFFT4096Asm:
R2:M[0]->BIU2.T3;
NOP;
NOP;
NOP;
BIU2:Load(T3)(A++) -> M[0](Mode0); //ConfigMFetch
BIU2:Load(T3)(A++) -> M[1](Mode0); //BIU0.T0 reset biu0.t2
BIU2:Load(T3)(A++) -> M[2](Mode0); //BIU1.T0 reset biu1.t2
BIU2:Load(T3)(A++) -> M[3](Mode0); //BIU0.T2_input_1@00000
BIU2:Load(T3)(A++) -> M[4](Mode0); //BIU1.T2_input_2@40000
BIU2:Load(T3)(A++) -> M[5](Mode0); //BIU3.T1_output@80000
BIU2:Load(T3)(A++) -> M[6](Mode0); //BIU2.T1_output@82000
BIU2:Load(T3)(A++) -> M[7](Mode0); //BIU3.T2_output@c0000
BIU2:Load(T3)(A++) -> M[8](Mode0); //BIU2.T2_output@c2000
BIU2:Load(T3)(A++) -> M[9](Mode0); //biu1.T1 move_factor_addr0
BIU2:Load(T3)(A++) -> M[10](Mode0); //biu1.T3 move_factor_addr1
BIU2:Load(T3)(A++) -> M[1](Mode0); //index_factor1
BIU2:Load(T3)(A++) -> M[133](Mode0); //index_factor2
BIU2:Load(T3)(A++) -> M[134](Mode0); //index_factor3
BIU2:Load(T3)(A++) -> M[135](Mode0)|| R0:M[1] -> BIU0.T0(Mode0)|| R1:M[2] -> BIU1.T0(Mode0); //index_factor4_1
BIU2:Load(T3)(A++) -> M[136](Mode0)|| R0:M[3] -> BIU0.T2(Mode0)|| R1:M[4] -> BIU1.T2(Mode0)|| R3:M[5] -> BIU3.T1(Mode0); //index_factor4_2
R5:PreConfig(M[0])(Mode0);
BIU2:Load(T3)(A++) -> M[137](Mode0)|| R5:WriteConf(Mfetch)->KI[0-3](Mode0); //index_factor5_1
BIU2:Load(T3)(A++) -> M[138](Mode0)|| R2:M[6] -> BIU2.T1(Mode0)|| R3:M[7] -> BIU3.T2(Mode0); //index_factor5_2
BIU2:Load(T3)(A++) -> M[51](Mode0)|| R2:M[8] -> BIU2.T2(Mode0)|| R1:M[9] -> BIU1.T1(Mode0);
BIU2:Load(T3)(A++) -> M[41](Mode0)|| R1:M[10] -> BIU1.T3(Mode0);
R5:PreConfig(M[0])(Mode0);
BIU2:Load(T3)(A++) -> M[60](Mode0)|| R5:WriteConf(Mfetch)->KI[4-7](Mode0);
BIU2:Load(T3)(A++) -> M[61](Mode0);
BIU2:Load(T3)(A++) -> M[32](Mode0);
BIU2:Load(T3)(A++) -> M[33](Mode0);
BIU2:Load(T3)(A++) -> M[142](Mode0);
BIU2:Load(T3)(A++) -> M[143](Mode0);
MFetch:REPEAT @(8);
R0:M[1] -> SHU0.T2(Mode0);
R0:M[32] -> SHU0.T0(Mode0);
R0:M[133] -> SHU0.T2(Mode0);
R0:M[134] -> SHU0.T2(Mode0);
SHU0:Index(T0,T2) -> M[132](W4) (Mode0)|| R0:M[135] -> SHU0.T2(Mode0);
SHU0:Index(T0,T2) -> M[133](W4) (Mode0)|| R0:M[136] -> SHU0.T2(Mode0)|| R1:M[33] -> SHU1.T1(Mode0);
SHU0:Index(T0,T2) -> M[134](W4) (Mode0)|| R1:M[137] -> SHU1.T2(Mode0);
SHU0:Index(T0,T2) -> M[135](W4) (Mode0)|| R1:M[138] -> SHU1.T2(Mode0);
SHU0:Index(T0,T2) -> M[136](W4) (Mode0);
SHU1:Index(T1,T2) -> M[137] (Mode0);
SHU1:Index(T1,T2) -> M[138] (Mode0);
R0:M[51] -> SHU0.T6(Mode0)|| R1:M[51] -> SHU1.T6(Mode0)|| R2:M[51] -> SHU2.T6(Mode0)|| R3:M[51] -> SHU3.T6(Mode0);
R0:M[41] -> SHU0.T7(Mode0)|| R1:M[41] -> SHU1.T7(Mode0)|| R2:M[41] -> SHU2.T7(Mode0)|| R3:M[41] -> SHU3.T7(Mode0);
R0:M[60] -> SHU0.T4(Mode0)|| R1:M[60] -> SHU1.T4(Mode0)|| R2:M[60] -> SHU2.T4(Mode0)|| R3:M[60] -> SHU3.T4(Mode0);
R0:M[61] -> SHU0.T5(Mode0)|| R1:M[61] -> SHU1.T5(Mode0)|| R2:M[61] -> SHU2.T5(Mode0)|| R3:M[61] -> SHU3.T5(Mode0);
NOP;
MFetch:LPTO %FFT4096AsmCyc0 @(KI2 - 0); //cycle all 64FFT code
BIU1:Load( T1)(A++) -> SHU0.T0(Mode0);
BIU1:Load(T3)(A++) -> SHU1.T0(Mode0);
R0:M[1] -> SHU0.T7||R1:M[1] -> SHU1.T7;
MFetch:REPEAT @(9);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[10](Mode0);
SHU1: T2 -V(1)->M[20](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2-V(1)->M[11](Mode0);
SHU1: T2-V(1)->M[21](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2-V(1)->M[12](Mode0);
SHU1: T2-V(1)->M[22](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2-V(1)->M[13](Mode0);
SHU1: T2-V(1)->M[23](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2-V(1)->M[14](Mode0);
SHU1: T2-V(1)->M[24](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2-V(1)->M[15](Mode0);
SHU1: T2-V(1)->M[25](Mode0);
R0:M[10] -> IMA0.T0(Mode0)|| R2:M[20] -> IMA2.T0(Mode0)|| R1:M[10] -> IMA1.T0(Mode0)|| R3:M[20] -> IMA3.T0(Mode0);
R0:M[11] -> IMA0.T1(Mode0)|| R2:M[21] -> IMA2.T1(Mode0)|| R1:M[11] -> IMA1.T1(Mode0)|| R3:M[21] -> IMA3.T1(Mode0);
R0:M[12] -> IMA0.T2(Mode0)|| R2:M[22] -> IMA2.T2(Mode0)|| R1:M[12] -> IMA1.T2(Mode0)|| R3:M[22] -> IMA3.T2(Mode0);
R0:M[13] -> IMA0.T3(Mode0)|| R2:M[23] -> IMA2.T3(Mode0)|| R1:M[13] -> IMA1.T3(Mode0)|| R3:M[23] -> IMA3.T3(Mode0);
IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
IMA0: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA1: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA2: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA3: SetShiftMode (T2) -> SHIFTMODE2 (Mode0);
IMA0: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA1: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA2: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA3: SetShiftMode (T3) -> SHIFTMODE3 (Mode0);
R0:M[41] -> SHU0.T7(Mode0)|| R1:M[41] -> SHU1.T7||R3:M[132] -> IMA2.T2(Mode0);
//shiftmode
BIU0:Wait 0 || BIU2:Wait 50 || R0:Wait 29 || R4:Wait 14 || R1:Wait 12 || R5:Wait 20 || SHU0:Wait 15 || SHU1:Wait 14 || IMA0:Wait 15 || IMA1:Wait 23 || BIU1:Wait 4 || BIU3:Wait 54 || R2:Wait 33 || R6:Wait 19 || R3:Wait 34 || R7:Wait 24 || SHU2:Wait 18 || SHU3:Wait 19 || IMA2:Wait 21 || IMA3:Wait 27 ;
MFetch:LPTO %FFT4096AsmCyc1 @(KI0 - 0);
//
BIU0:Load(T2)(A++)(BR) -> SHU1.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[32] -> SHU1.T0(Mode0) || R4:M[132] -> IMA0.T2(Mode0) || R1:M[10] -> IMA0.T0(Mode0) || R5:M[10] -> IMA1.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA0.T0(Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[42] -> SHU3.T0(Mode0) || R6:M[133] -> IMA2.T4(Mode0) || R3:M[14] -> IMA2.T0(Mode0) || R7:M[10] -> IMA3.T0(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[33] -> SHU1.T1(Mode0) || R4:M[133] -> IMA0.T4(Mode0) || R1:M[11] -> IMA0.T1(Mode0) || R5:M[11] -> IMA1.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA0.T1 (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[43] -> SHU3.T1(Mode0) || R6:M[134] -> IMA2.T5(Mode0) || R3:M[15] -> IMA2.T1(Mode0) || R7:M[11] -> IMA3.T1(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1(Mode0) || SHU3:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[34] -> SHU1.T2(Mode0) || R4:M[134] -> IMA0.T5(Mode0) || R5:M[132] -> IMA1.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[44] -> SHU3.T2(Mode0) || R7:M[132] -> IMA3.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[35] -> SHU1.T3(Mode0) || R5:M[133] -> IMA1.T4(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[45] -> SHU3.T3(Mode0) || R7:M[133] -> IMA3.T4(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || SHU3:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[134] -> IMA1.T5(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R7:M[134] -> IMA3.T5(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[36] -> SHU0.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA1.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[46] -> SHU2.T0(Mode0) || SHU2:Index(T0, T1, T6) -> IMA3.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[42] (W2) & SHU2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[37] -> SHU0.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[47] -> SHU2.T1(Mode0) || SHU2:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[43] (W2) & SHU2.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T0(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[38] -> SHU0.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA1.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[32] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[36] (W1) & SHU1.T0(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[48] -> SHU2.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[44] (W2) & SHU2.T2(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[46] (W3) & SHU3.T0(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[39] -> SHU0.T3(Mode0) || SHU0:Index(T2, T3, T7) -> IMA1.T1(Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[33] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[37] (W1) & SHU1.T1(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R2:M[49] -> SHU2.T3(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[45] (W2) & SHU2.T3(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[47] (W3) & SHU3.T1(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[34] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[38] (W1) & SHU1.T2(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[48] (W3) & SHU3.T2(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU1.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[35] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[39] (W1) & SHU1.T3(Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[32] -> BIU2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[49] (W3) & SHU3.T3(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T2(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[14] -> IMA1.T2(Mode0) || IMA1: SetShiftMode (T2) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[33] -> BIU2.T0(Mode0) || R3:M[10] -> IMA2.T5(Mode0);
BIU0:Load(T2)(A++)(BR) -> SHU0.T3(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R5:M[15] -> IMA1.T3(Mode0) || IMA1: SetShiftMode (T3) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++)(BR) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[34] -> BIU2.T0(Mode0) || R3:M[11] -> IMA2.T4(Mode0);
R2:M[35] -> BIU2.T0(Mode0) || IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
R1:M[14] -> IMA0.T0(Mode0) || SHU0:Index(T1, T0, T4) -> IMA0.T3(Mode0) || R2:M[42] -> BIU2.T0(Mode0) || R6:M[135] -> IMA2.T4(Mode0) || R7:M[14] -> IMA3.T0(Mode0) || IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
R4:M[135] -> IMA0.T2(Mode0) || R1:M[15] -> IMA0.T1(Mode0) || SHU0:Index(T1, T0, T5) -> IMA0.T1(Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || R2:M[43] -> BIU2.T0(Mode0) || R6:M[136] -> IMA2.T2(Mode0) || R7:M[15] -> IMA3.T1(Mode0) || SHU2:Index(T1, T0, T4) -> IMA2.T0(Mode0) || SHU3:Index(T1, T0, T4) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
R4:M[136] -> IMA0.T4(Mode0) || SHU0:Index(T3, T2, T4) -> IMA0.T3(Mode0) || SHU1:Index(T1, T0, T4) -> IMA0.T0(Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || R2:M[44] -> BIU2.T0(Mode0) || SHU2:Index(T1, T0, T5) -> IMA2.T1(Mode0) || SHU3:Index(T1, T0, T5) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
R5:M[135] -> IMA1.T2(Mode0) || SHU0:Index(T3, T2, T5) -> IMA0.T1(Mode0) || SHU1:Index(T1, T0, T5) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[45] -> BIU2.T0(Mode0) || R7:M[135] -> IMA3.T4(Mode0) || SHU2:Index(T3, T2, T4) -> IMA2.T0(Mode0) || SHU3:Index(T3, T2, T4) -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R5:M[136] -> IMA1.T4(Mode0) || SHU1:Index(T3, T2, T4) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[36] -> BIU2.T0(Mode0) || R6:M[137] -> IMA2.T5(Mode0) || R7:M[136] -> IMA3.T2(Mode0) || SHU2:Index(T3, T2, T5) -> IMA2.T1(Mode0) || SHU3:Index(T3, T2, T5) -> IMA2.T1 (Mode0) || IMA2: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R4:M[137] -> IMA0.T5(Mode0) || SHU1:Index(T3, T2, T5) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[37] -> BIU2.T0(Mode0) || R6:M[138] -> IMA2.T3(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R4:M[138] -> IMA0.T3(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[38] -> BIU2.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0);
R5:M[137] -> IMA1.T5(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[39] -> BIU2.T0(Mode0) || R7:M[137] -> IMA3.T5(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R5:M[138] -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[46] -> BIU2.T0(Mode0) || R6:M[142] -> IMA2.T4(Mode0) || R7:M[138] -> IMA3.T3(Mode0) || SHU3:Index(T1, T0, T4) -> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R4:M[142] -> IMA0.T2(Mode0) || SHU0:Index(T1, T0, T4) -> IMA1.T0(Mode0) || SHU1:Index(T1, T0, T4) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[47] -> BIU2.T0(Mode0) || R6:M[143] -> IMA2.T2(Mode0) || SHU3:Index(T1, T0, T5) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[42] (W2) & SHU2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R4:M[143] -> IMA0.T4(Mode0) || SHU0:Index(T1, T0, T5) -> IMA1.T1(Mode0) || SHU1:Index(T1, T0, T5) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R2:M[48] -> BIU2.T0(Mode0) || SHU2:Index(T1, T0, T4) -> IMA3.T3(Mode0) || SHU3:Index(T3, T2, T4) -> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[43] (W2) & SHU2.T1(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0);
R5:M[142] -> IMA1.T2(Mode0) || SHU0:Index(T3, T2, T4) -> IMA1.T0(Mode0) || SHU1:Index(T3, T2, T4) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[32] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[36] (W1) & SHU1.T0(Mode0) || R2:M[49] -> BIU2.T0(Mode0) || R7:M[142] -> IMA3.T4(Mode0) || SHU2:Index(T1, T0, T5) -> IMA3.T1(Mode0) || SHU3:Index(T3, T2, T5) -> IMA3.T1 (Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[44] (W2) & SHU2.T2(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[46] (W3) & SHU3.T0(Mode0);
R5:M[143] -> IMA1.T5(Mode0) || SHU0:Index(T3, T2, T5) -> IMA1.T1(Mode0) || SHU1:Index(T3, T2, T5) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[33] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[37] (W1) & SHU1.T1(Mode0) || R7:M[143] -> IMA3.T2(Mode0) || SHU2:Index(T3, T2, T4) -> IMA3.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[45] (W2) & SHU2.T3(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[47] (W3) & SHU3.T1(Mode0);
IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[34] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[38] (W1) & SHU1.T2(Mode0) || SHU2:Index(T3, T2, T5) -> IMA3.T1(Mode0) || IMA2: SetShiftMode (T5) -> SHIFTMODE0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[48] (W3) & SHU3.T2(Mode0);
IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[35] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[39] (W1) & SHU1.T3(Mode0) || IMA2: SetShiftMode (T4) -> SHIFTMODE1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[49] (W3) & SHU3.T3(Mode0);
NOP;
R6:M[132] -> IMA2.T2(Mode0);
NOP;
NOP;
SHU0:T0 + V(0)-> BIU3.T0(Mode0);
SHU0:T1 + V(0) -> BIU3.T0(Mode0) || SHU2:T0 + V(0)-> BIU3.T0(Mode0);
SHU0:T2 + V(0) -> BIU3.T0(Mode0) || SHU2:T1 + V(0) -> BIU3.T0(Mode0);
SHU0:T3 + V(0) -> BIU3.T0(Mode0) || SHU2:T2 + V(0) -> BIU3.T0(Mode0);
SHU2:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
NOP;
NOP;
SHU3:T0 + V(0)-> BIU3.T0(Mode0);
SHU1:T0 + V(0)-> BIU3.T0(Mode0) || SHU3:T1 + V(0) -> BIU3.T0(Mode0);
SHU1:T1 + V(0) -> BIU3.T0(Mode0) || SHU3:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:T2 + V(0) -> BIU3.T0(Mode0) || SHU3:T3 + V(0) -> BIU3.T0(Mode0);
SHU1:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
FFT4096AsmCyc1:
BIU2:Wait 0 || BIU3:Wait 0 || BIU0:Wait 0 || BIU1:Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || IMA2: Wait 0 || IMA3: Wait 0 || R0:Wait 0 || R1:Wait 0 || R2:Wait 0 || R3:Wait 0 || R4:Wait 0 || R5:Wait 0 || R6:Wait 0 || R7:Wait 0 || SHU0:Wait 0 || SHU1:Wait 0 || SHU2:Wait 0 || SHU3:Wait 0 ;
MFetch:REPEAT @(60);
BIU0:T0[0]+T0[1]-> T2[0](Mode0)|| BIU1:T0[0]+T0[1]-> T2[0](Mode0);
BIU0:T0[0]+T0[1]-> T2[1](Mode0)|| BIU1:T0[0]+T0[1]-> T2[1](Mode0);
BIU0:T0[0]+T0[1]-> T2[2](Mode0)|| BIU1:T0[0]+T0[1]-> T2[2](Mode0);
BIU0:T0[0]+T0[1]-> T0[0](Mode0)|| BIU1:T0[0]+T0[1]-> T0[0](Mode0);
FFT4096AsmCyc0:
////////////////////////////////////////////////////////////////////
BIU2:Load(T3)(A++) -> M[0](Mode0); //BIU2.T1_output
BIU2:Load(T3)(A++) -> M[1](Mode0); //BIU2.T2_output
BIU2:Load(T3)(A++) -> M[2](Mode0); //BIU3.T1_output
BIU2:Load(T3)(A++) -> M[3](Mode0); //BIU3.T2_output
BIU2:Load(T3)(A++) -> M[4](Mode0); //BIU0.T2_input
BIU2:Load(T3)(A++) -> M[5](Mode0); //BIU1.T2_input
BIU2:Load(T3)(A++) -> M[6](Mode0); //BIU0.T0_input
BIU2:Load(T3)(A++) -> M[7](Mode0); //BIU1.T0_input
BIU2:Load(T3)(A++) -> M[8](Mode0); //BIU0.T3_butterfly
BIU2:Load(T3)(A++) -> M[9](Mode0); //BIU0.T1_butterfly
BIU2:Load(T3)(A++) -> M[10](Mode0); //biu1.T1 move_factor_addr
BIU2:Load(T3)(A++) -> M[11](Mode0); //biu1.T3 move_factor_addr
BIU2:Load(T3)(A++) -> M[60](Mode0);
BIU2:Load(T3)(A++) -> M[61](Mode0);
BIU2:Load(T3)(A++) -> M[62](Mode0);
BIU2:Load(T3)(A++) -> M[63](Mode0);
BIU2:Load(T3)(A++) -> M[140](Mode0)|| R2:M[0] -> BIU2.T1(Mode0)|| R3:M[2] -> BIU3.T1(Mode0); //index_factor7_1
BIU2:Load(T3)(A++) -> M[141](Mode0)|| R2:M[1] -> BIU2.T2(Mode0)|| R3:M[3] -> BIU3.T2(Mode0); //index_factor7_2
BIU2:Load(T3)(A++) -> M[142](Mode0)|| R0:M[4] -> BIU0.T2(Mode0)|| R1:M[5] -> BIU1.T2(Mode0); //index_factor8_1
BIU2:Load(T3)(A++) -> M[143](Mode0)|| R0:M[6] -> BIU0.T0(Mode0)|| R1:M[7] -> BIU1.T0(Mode0); //index_factor8_2
BIU2:Load(T3)(A++) -> M[144](Mode0)|| R0:M[8] -> BIU0.T3(Mode0); //index_factor9_1
BIU2:Load(T3)(A++) -> M[145](Mode0)|| R0:M[9] -> BIU0.T1(Mode0); //index_factor9_2
BIU2:Load(T3)(A++) -> M[146](Mode0)|| R1:M[10] -> BIU1.T1(Mode0); //index_factor10_1
BIU2:Load(T3)(A++) -> M[147](Mode0)|| R1:M[11] -> BIU1.T3(Mode0); //index_factor10_2
BIU2:Load(T3)(A++) -> M[50](Mode0); //index_factor10_3
BIU2:Load(T3)(A++) -> M[149](Mode0); //index_factor10_4
BIU2:Load(T3)(A++) -> M[152](Mode0); //index_factor11_1
BIU2:Load(T3)(A++) -> M[153](Mode0); //index_factor11_2
R0:M[60] -> SHU0.T6(Mode0)|| R2:M[60] -> SHU2.T6(Mode0)|| R3:M[60] -> SHU3.T6(Mode0);
R0:M[61] -> SHU0.T7(Mode0)|| R2:M[61] -> SHU2.T7(Mode0)|| R3:M[61] -> SHU3.T7(Mode0);
MFetch:LPTO %FFT4096AsmCyc4 @(KI4 - 0); //symbol
BIU1:Load(T1)(A++) -> SHU0.T0(Mode0);
BIU1:Load(T3)(A++) -> SHU1.T0(Mode0);
R0:M[140] -> SHU0.T7(Mode0)||R1:M[140] -> SHU1.T7(Mode0);
MFetch:REPEAT @(9);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[20](Mode0);
SHU1: T2 -V(1)->M[8](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[21](Mode0);
SHU1: T2 -V(1)->M[9](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[12](Mode0);
SHU1: T2 -V(1)->M[18](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[13](Mode0);
SHU1: T2 -V(1)->M[19](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[30](Mode0);
SHU1: T2 -V(1)->M[58](Mode0);
SHU0: Index(T0 ,T7) (T7 = T7+V(4) )->SHU0.T2(Mode0);
SHU1: Index(T0 ,T7) (T7 = T7+V(4) )->SHU1.T2(Mode0);
SHU0: T2 -V(1)->M[31](Mode0);
SHU1: T2 -V(1)->M[59](Mode0);
R0:M[20] -> IMA0.T0(Mode0)|| R2:M[8] -> IMA2.T0(Mode0)|| R1:M[20] -> IMA1.T0(Mode0)|| R3:M[8] -> IMA3.T0(Mode0);
R0:M[21] -> IMA0.T1(Mode0)|| R2:M[9] -> IMA2.T1(Mode0)|| R1:M[21] -> IMA1.T1(Mode0)|| R3:M[9] -> IMA3.T1(Mode0);
R0:M[12] -> IMA0.T2(Mode0)|| R2:M[18] -> IMA2.T2(Mode0)|| R1:M[12] -> IMA1.T2(Mode0)|| R3:M[18] -> IMA3.T2(Mode0);
R0:M[13] -> IMA0.T3(Mode0)|| R2:M[19] -> IMA2.T3(Mode0)|| R1:M[13] -> IMA1.T3(Mode0)|| R3:M[19] -> IMA3.T3(Mode0);
IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0)|| IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
IMA0: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA1: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA2: SetShiftMode (T2) -> SHIFTMODE2 (Mode0)|| IMA3: SetShiftMode (T2) -> SHIFTMODE2 (Mode0);
IMA0: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA1: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA2: SetShiftMode (T3) -> SHIFTMODE3 (Mode0)|| IMA3: SetShiftMode (T3) -> SHIFTMODE3 (Mode0);
R2:M[8] -> SHU2.T3(Mode0)|| R3:M[8] -> SHU3.T4(Mode0);
R2:M[9] -> SHU2.T5(Mode0)|| R3:M[9] -> SHU3.T5(Mode0);
R0:M[61] -> SHU0.T7;
MFetch:LPTO %FFT4096AsmCyc2 @(KI3 - 0); //cyle all 64FFT
BIU0:Wait 0 || BIU2:Wait 56 || R0:Wait 23 || R4:Wait 15 || R1:Wait 14 || R5:Wait 26 || SHU0:Wait 21 || SHU1:Wait 18 || IMA0:Wait 21 || IMA1:Wait 29 || BIU1:Wait 6 || BIU3:Wait 56 || R2:Wait 36 || R6:Wait 32 || R3:Wait 34 || R7:Wait 44 || SHU2:Wait 18 || SHU3:Wait 20 || IMA3:Wait 21 || IMA2:Wait 29 ;
MFetch:LPTO %FFT4096AsmCyc3 @(KI1 - 0); //64FFT cycle
//cycle_64fft
//
BIU0:Load(T3)(A++) -> M[172](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[173] -> SHU0.T4(Mode0) || R4:M[20] -> IMA0.T0(Mode0) || R1:M[172] -> SHU1.T4(Mode0) || R5:M[20] -> IMA1.T0(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T4,T2)-> IMA[0,3].T2 (Mode0) || IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++) -> SHU3.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[40] -> SHU2.T2(Mode0) || R7:M[155] -> IMA3.T5(Mode0) || R2:M[62] -> SHU2.T6(Mode0) || R6:M[58] -> SHU3.T4(Mode0) || SHU2:T3 + V(0) ->IMA3.T0(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T0 (Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T3)(A++) -> M[173](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[140] -> SHU0.T2(Mode0) || R4:M[21] -> IMA0.T1(Mode0) || R1:M[140] -> SHU1.T2(Mode0) || R5:M[21] -> IMA1.T1(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T4,T2)-> IMA[0,3].T4 (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || BIU1:Load(T2)(A++) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[41] -> SHU2.T3(Mode0) || R7:M[156] -> IMA3.T4(Mode0) || R2:M[63] -> SHU2.T7(Mode0) || R6:M[59] -> SHU3.T5(Mode0) || SHU2:T5 + V(0) ->IMA3.T1(Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA2: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T3)(A++) -> M[174](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[141] -> SHU0.T2(Mode0) || R4:M[60] -> SHU1.T6(Mode0) || R1:M[141] -> SHU1.T2(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA0.T0 (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[42] -> SHU2.T4(Mode0) || R7:M[190] -> IMA3.T5(Mode0) || R6:M[62] -> SHU3.T6(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T0 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[175](W4)(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R4:M[61] -> SHU1.T7(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || SHU1:Index(T0, T1, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[43] -> SHU2.T5(Mode0) || R7:M[91] -> IMA3.T3(Mode0) || R6:M[63] -> SHU3.T7(Mode0) || SHU2:Index(T0, T1, T6) -> IMA3.T3(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA3: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T2 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[176](W4)(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T2(Mode0) || R7:M[92] -> IMA3.T2(Mode0) || SHU2:Index(T0, T1, T7) -> IMA3.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[177](W4)(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R7:M[93] -> IMA3.T4(Mode0) || R2:M[128] -> IMA3.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T3(Mode0) || IMA3: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T4 (ShiftMode0) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || SHU0:Index(T4,T2)-> IMA[1,2].T2 (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T5 (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[30] -> SHU2.T3(Mode0) || R7:M[60] -> SHU2.T6(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || SHU3:T4 + V(0) ->IMA2.T0(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[142] -> SHU0.T0(Mode0) || R1:M[142] -> SHU1.T3(Mode0) || R5:M[62] -> SHU0.T6(Mode0) || SHU0:Index(T4,T2)-> IMA[1,2].T4 (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T2 (Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[31] -> SHU2.T5(Mode0) || R7:M[61] -> SHU2.T7(Mode0) || R6:M[58] -> IMA2.T3(Mode0) || SHU3:T5 + V(0) ->IMA2.T1(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[143] -> SHU0.T5(Mode0) || R1:M[143] -> SHU1.T3(Mode0) || R5:M[63] -> SHU0.T7(Mode0) || SHU0:Index(T0, T1, T6) -> IMA1.T3(Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T4(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T0(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R3:M[44] -> SHU3.T5(Mode0) || R6:M[59] -> IMA2.T4(Mode0) || SHU3:Index(T0, T1, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T1(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[144] -> SHU0.T6(Mode0) || R1:M[144] -> SHU1.T3(Mode0) || R5:M[62] -> SHU1.T6(Mode0) || SHU0:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || SHU1:Index(T4,T3)-> IMA[0,3].T3 (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[45] -> SHU3.T3(Mode0) || SHU3:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T2(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[145] -> SHU0.T7(Mode0) || R1:M[145] -> SHU1.T3(Mode0) || R5:M[63] -> SHU1.T7(Mode0) || SHU0:Index(T2, T3, T6) -> IMA1.T3(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[0] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[4] (W1) & SHU1.T0(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T0(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || SHU3:Index(T2, T3, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[40] (W3) & SHU3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[44] (W2) & SHU2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T3(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || SHU0:Index(T2, T3, T7) -> IMA1.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[1] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[5] (W1) & SHU1.T1(Mode0) || BIU1:Load(T2)(A++) -> SHU2.T1(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[46] -> SHU3.T4(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T3 (Mode0) || SHU3:Index(T2, T3, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode2) (IndexMode0)-> M[41] (W3) & SHU3.T1(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode2) (IndexMode0)-> M[45] (W2) & SHU2.T1(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T2(Mode0) || BIU2:Store(T0,T1)(A++)(Mode0) || R0:M[0] -> SHU1.T2(Mode0) || SHU0:Index(T4,T0)-> IMA[1,2].T5 (Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T0(Mode0) || IMA0: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[2] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[6] (W1) & SHU1.T2(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T2(Mode0) || BIU3:Store(T0,T1)(A++)(Mode0) || R3:M[47] -> SHU3.T5(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[42] (W3) & SHU3.T2(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[46] (W2) & SHU2.T2(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T3(Mode0) || R0:M[1] -> SHU1.T3(Mode0) || R1:M[174] -> SHU1.T1(Mode0) || SHU0:Index(T4,T5)-> IMA[1,2].T3 (Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[3] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[7] (W1) & SHU1.T3(Mode0) || BIU1:Load(T2)(A++) -> SHU3.T3(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T3 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode2) (IndexMode0)-> M[43] (W3) & SHU3.T3(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode2) (IndexMode0)-> M[47] (W2) & SHU2.T3(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[2] -> SHU1.T4(Mode0) || R1:M[146] -> SHU1.T4(Mode0) || SHU0:Index(T4,T6)-> IMA[1,2].T5 (Mode0) || SHU1:Index(T1,T4)-> IMA[0,3].T2 (Mode0) || IMA0: SetShiftMode (T5) -> SHIFTMODE0 (Mode0) || BIU1:Load(T2)(A++) -> SHU2.T2(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1(Mode0) || IMA2: SetShiftMode (T3) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++) -> SHU1.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R0:M[3] -> SHU1.T5(Mode0) || R1:M[147] -> SHU1.T5(Mode0) || SHU0:Index(T4,T7)-> IMA[1,2].T2 (Mode0) || SHU1:Index(T1,T5)-> IMA[0,3].T4 (Mode0) || BIU1:Load(T2)(A++) -> SHU2.T3(Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || IMA2: SetShiftMode (T4) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++) -> SHU0.T0(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R1:M[50] -> SHU1.T4(Mode0) || SHU1:Index(T1,T4)-> IMA[0,3].T5 (Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || SHU3:T4 + V(0) ->IMA3.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T1(Mode0) || BIU2:Store(T0,T2)(A++)(Mode0) || R4:M[30] -> IMA0.T5(Mode0) || R1:M[149] -> SHU1.T5(Mode0) || SHU0:Index(T0, T1, T6) -> IMA0.T3(Mode0) || SHU1:Index(T1,T5) -> M[128] (Mode0) || BIU3:Store(T0,T2)(A++)(Mode0) || R2:M[8] -> SHU3.T4(Mode0) || R6:M[157] -> IMA2.T4(Mode0) || SHU3:T5 + V(0) ->IMA3.T1(Mode0);
BIU0:Load(T2)(A++) -> SHU1.T2(Mode0) || R0:M[128] -> IMA0.T2(Mode0) || R1:M[177] -> SHU1.T3(Mode0) || SHU0:Index(T0, T1, T7) -> IMA0.T1(Mode0) || SHU1:Index(T3,T4) -> M[155] (Mode0) || IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0) || R2:M[9] -> SHU3.T5(Mode0) || R6:M[60] -> SHU3.T6(Mode0) || SHU3:Index(T0, T1, T6) -> IMA3.T3 (Mode0) || IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Load(T2)(A++) -> SHU1.T3(Mode0) || R1:M[152] -> SHU1.T4(Mode0) || SHU0:Index(T2, T3, T6) -> IMA0.T3(Mode0) || SHU1:Index(T3,T5) -> M[156] (Mode0) || IMA0: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || IMA1: SetShiftMode (T1) -> SHIFTMODE1 (Mode0) || R6:M[61] -> SHU3.T7(Mode0) || SHU3:Index(T0, T1, T7) -> IMA3.T1 (Mode0) || IMA3: SetShiftMode (T1) -> SHIFTMODE1 (Mode0);
BIU0:Load(T2)(A++) -> SHU0.T2(Mode0) || R0:M[4] -> SHU0.T5(Mode0) || R1:M[153] -> SHU1.T5(Mode0) || SHU0:Index(T2, T3, T7) -> IMA0.T1(Mode0) || IMA0: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || SHU3:Index(T2, T3, T6) -> IMA3.T3 (Mode0) || IMA3: T3 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T2)(A++) -> SHU0.T3(Mode0) || R0:M[5] -> SHU0.T3(Mode0) || SHU1:Index(T2, T3, T6) -> IMA0.T0 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[0] -> BIU2.T0(Mode0) || R6:M[194] -> IMA2.T2(Mode0) || SHU2:Index(T2, T3, T6) -> IMA3.T0(Mode0) || SHU3:Index(T2, T3, T7) -> IMA3.T1 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[178](W6)(Mode0) || R0:M[6] -> SHU0.T4(Mode0) || SHU0:Index(T0,T2)-> IMA[1,2].T4 (Mode0) || SHU1:Index(T2, T3, T7) -> IMA0.T1 (Mode0) || IMA0: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R2:M[1] -> BIU2.T0(Mode0) || R6:M[195] -> IMA2.T5(Mode0) || SHU2:Index(T2, T3, T7) -> IMA3.T1(Mode0) || IMA3: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T3 AS T1*T5 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T3)(A++) -> M[179](W6)(Mode0) || R0:M[7] -> SHU0.T5(Mode0) || R4:M[175] -> SHU0.T0(Mode0) || R1:M[31] -> IMA0.T1(Mode0) || SHU0:Index(T0,T3)-> IMA[1,2].T2 (Mode0) || SHU1:Index(T4, T5, T6) -> IMA0.T0(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA1.T0(Mode0) || R3:M[40] -> BIU3.T0(Mode0) || R2:M[2] -> BIU2.T0(Mode0) || R6:M[196] -> IMA2.T4(Mode0) || SHU2:Index(T4, T5, T6) -> IMA3.T0(Mode0) || IMA3: T0 AS T1*T2 (ShiftMode3) (IndexMode2)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode3) (IndexMode2)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[190](W6)(Mode0) || R0:M[178] -> SHU1.T0(Mode0) || R4:M[146] -> SHU0.T2(Mode0) || SHU0:Index(T0,T2)-> IMA[1,2].T5 (Mode0) || SHU1:Index(T4, T5, T7) -> IMA0.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[41] -> BIU3.T0(Mode0) || R2:M[3] -> BIU2.T0(Mode0) || R6:M[197] -> IMA2.T3(Mode0) || SHU2:Index(T4, T5, T7) -> IMA3.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[91](W6)(Mode0) || R0:M[152] -> SHU1.T2(Mode0) || R4:M[147] -> SHU0.T3(Mode0) || R1:M[176] -> SHU1.T3(Mode0) || R5:M[60] -> SHU0.T6(Mode0) || SHU0:Index(T0,T3) -> M[157] (Mode0) || SHU1:Index(T3,T4)-> IMA[0,3].T4 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[42] -> BIU3.T0(Mode0) || SHU2:T3 + V(0) ->IMA1.T0(Mode0) || IMA3: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[92](W6)(Mode0) || R0:M[153] -> SHU1.T3(Mode0) || R4:M[50] -> SHU0.T2(Mode0) || R1:M[152] -> SHU1.T4(Mode0) || R5:M[61] -> SHU0.T7(Mode0) || SHU0:Index(T5, T3, T6) -> IMA1.T0(Mode0) || SHU1:Index(T3,T5)-> IMA[0,3].T3 (Mode0) || IMA0: T0 AS T1*T2 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || R3:M[43] -> BIU3.T0(Mode0) || SHU2:T5 + V(0) ->IMA1.T1(Mode0) || IMA3: T0 AS T1*T5 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[93](W6)(Mode0) || R0:M[179] -> SHU1.T4(Mode0) || R4:M[149] -> SHU0.T3(Mode0) || R1:M[153] -> SHU1.T5(Mode0) || SHU0:Index(T5, T3, T7) -> IMA1.T1(Mode0) || IMA0: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA0.T0(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA1.T0(Mode0) || SHU3:Index(T5, T3, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T4 (ShiftMode0) (IndexMode3)-> IMA3.T0(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode0) (IndexMode3)-> IMA2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[194](W6)(Mode0) || R5:M[194] -> IMA1.T2(Mode0) || SHU0:Index(T4, T5, T6) -> IMA1.T0(Mode0) || SHU1:Index(T0, T1, T6) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[0] (W0) & SHU0.T0(Mode0) || IMA1: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[4] (W1) & SHU1.T0(Mode0) || R2:M[8] -> SHU2.T3(Mode0) || SHU2:Index(T0, T1, T6) -> IMA2.T3(Mode0) || SHU3:Index(T5, T3, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[40] (W3) & SHU3.T0(Mode0) || IMA2: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[44] (W2) & SHU2.T0(Mode0);
BIU0:Load(T1)(A++) -> M[195](W6)(Mode0) || R4:M[155] -> IMA0.T2(Mode0) || R5:M[195] -> IMA1.T5(Mode0) || SHU0:Index(T4, T5, T7) -> IMA1.T1(Mode0) || SHU1:Index(T0, T1, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[1] (W0) & SHU0.T1(Mode0) || IMA1: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[5] (W1) & SHU1.T1(Mode0) || R2:M[9] -> SHU2.T5(Mode0) || SHU2:Index(T0, T1, T7) -> IMA2.T1(Mode0) || SHU3:Index(T4, T5, T6) -> IMA2.T0 (Mode0) || IMA3: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[41] (W3) & SHU3.T1(Mode0) || IMA2: T0 AS T1*T5 (ShiftMode1) (IndexMode0)-> M[45] (W2) & SHU2.T1(Mode0);
BIU0:Load(T1)(A++) -> M[196](W6)(Mode0) || R4:M[156] -> IMA0.T4(Mode0) || R5:M[196] -> IMA1.T4(Mode0) || SHU1:Index(T2, T3, T6) -> IMA1.T3(Mode0) || IMA0: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[2] (W0) & SHU0.T2(Mode0) || IMA1: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[6] (W1) & SHU1.T2(Mode0) || R2:M[4] -> BIU2.T0(Mode0) || SHU2:Index(T2, T3, T6) -> IMA2.T3(Mode0) || SHU3:Index(T4, T5, T7) -> IMA2.T1 (Mode0) || IMA3: T0 AS T1*T2 (ShiftMode1) (IndexMode0)-> M[42] (W3) & SHU3.T2(Mode0) || IMA2: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[46] (W2) & SHU2.T2(Mode0);
BIU0:Load(T1)(A++) -> M[197](W6)(Mode0) || R4:M[190] -> IMA0.T5(Mode0) || R5:M[197] -> IMA1.T3(Mode0) || SHU1:Index(T2, T3, T7) -> IMA1.T1 (Mode0) || IMA0: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[3] (W0) & SHU0.T3(Mode0) || IMA1: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[7] (W1) & SHU1.T3(Mode0) || R2:M[5] -> BIU2.T0(Mode0) || SHU2:Index(T2, T3, T7) -> IMA2.T1(Mode0) || IMA3: T0 AS T1*T4 (ShiftMode1) (IndexMode0)-> M[43] (W3) & SHU3.T3(Mode0) || IMA2: T0 AS T1*T3 (ShiftMode1) (IndexMode0)-> M[47] (W2) & SHU2.T3(Mode0);
R4:M[91] -> IMA0.T3(Mode0) || SHU0:T0 + V(0)-> BIU2.T0(Mode0) || R3:M[44] -> BIU3.T0(Mode0) || R2:M[6] -> BIU2.T0(Mode0);
R4:M[92] -> IMA0.T2(Mode0) || SHU0:T1 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T0,T2)-> IMA[1,2].T2 (Mode0) || R3:M[45] -> BIU3.T0(Mode0) || R2:M[7] -> BIU2.T0(Mode0) || SHU3:T0 + V(0) -> BIU3.T0(Mode0);
R4:M[93] -> IMA0.T4(Mode0) || SHU0:T2 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T0,T3)-> IMA[1,2].T5 (Mode0) || R3:M[46] -> BIU3.T0(Mode0) || SHU3:T1 + V(0) -> BIU3.T0(Mode0);
R1:M[157] -> IMA1.T4(Mode0) || SHU0:T3 + V(0) -> BIU2.T0(Mode0) || SHU1:Index(T4,T2)-> IMA[1,2].T4 (Mode0) || R3:M[47] -> BIU3.T0(Mode0) || SHU3:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:Index(T4,T3)-> IMA[1,2].T3 (Mode0) || SHU3:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
SHU1:T0 + V(0)-> BIU2.T0(Mode0) || SHU2:T0 + V(0)-> BIU3.T0(Mode0);
SHU1:T1 + V(0) -> BIU2.T0(Mode0) || SHU2:T1 + V(0) -> BIU3.T0(Mode0);
SHU1:T2 + V(0) -> BIU2.T0(Mode0) || SHU2:T2 + V(0) -> BIU3.T0(Mode0);
SHU1:T3 + V(0) -> BIU2.T0(Mode0) || SHU2:T3 + V(0) -> BIU3.T0(Mode0);
NOP;
//
FFT4096AsmCyc3:
BIU2:Wait 0 || BIU3:Wait 0 || BIU0:Wait 0 || BIU1:Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || IMA2: Wait 0 || IMA3: Wait 0 || R0:Wait 0 || R1:Wait 0 || R2:Wait 0 || R3:Wait 0 || R4:Wait 0 || R5:Wait 0 || R6:Wait 0 || R7:Wait 0 || SHU0:Wait 0 || SHU1:Wait 0 || SHU2:Wait 0 || SHU3:Wait 0 ;
MFetch:REPEAT @(60);
BIU0:4 -> T2[11](Mode0)|| BIU1:4 -> T2[11](Mode0);
BIU0:T0[0]+T0[1]-> T2[0](Mode0)|| BIU1:T0[0]+T0[1]-> T2[0](Mode0);
BIU0:T0[0]+T0[1]-> T2[1](Mode0)|| BIU1:T0[0]+T0[1]-> T2[1](Mode0);
BIU0:T0[0]+T0[1]-> T2[2](Mode0)|| BIU1:T0[0]+T0[1]-> T2[2](Mode0);
BIU0:T0[0]+T0[1]-> T2[3](Mode0)|| BIU1:T0[0]+T0[1]-> T2[3](Mode0);
BIU0:T2[0](S)(L)-> T0[0](L)(Mode0)|| BIU1:T2[0](S)(L)-> T0[0](L)(Mode0);
BIU0:T2[0](S)(MH)-> T0[0](MH)(Mode0)|| BIU1:T2[0](S)(MH)-> T0[0](MH)(Mode0);
FFT4096AsmCyc2:
FFT4096AsmCyc4:
MFetch:REPEAT @(10);
MFetch:MPU.STOP;

41
MicroCode/Channel_Equ/src/mpu0/IFFT4096DataTurnAsm.m0.asm Normal file
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.section .text.m0,"ax",@progbits
.file "IFFT4096DataTurnAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global IFFT4096DataTurnAsm
IFFT4096DataTurnAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0); //ConfigMFetch
BIU1:Load(T0)(A++) -> M[1](Mode0); //BIU0.T0_input
BIU1:Load(T0)(A++) -> M[2](Mode0); //BIU1.T0_input
BIU1:Load(T0)(A++) -> M[3](Mode0); //BIU2.T2_output
BIU1:Load(T0)(A++) -> M[4](Mode0); //BIU3.T2_output
BIU1:Load(T0)(A++) -> M[5](Mode0);
BIU1:Load(T0)(A++) -> M[6](Mode0);
NOP;
NOP;
NOP;
R5:PreConfig(M[0])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R0:M[1] -> BIU0.T0(Mode0);
R1:M[2] -> BIU1.T0(Mode0);
R2:M[3] -> BIU2.T2(Mode0);
R3:M[4] -> BIU3.T2(Mode0);
R1:M[5] -> IMA1.T2(Mode0)|| R2:M[5] -> IMA2.T2(Mode0) ;
R0:M[6] -> IMA0.T0(Mode0)|| R1:M[6] -> IMA1.T0(Mode0)|| R2:M[6] -> IMA2.T0(Mode0)|| R3:M[6] -> IMA3.T0(Mode0);
NOP;
NOP;
IMA0: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA1: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA2: SetShiftMode (T0) -> SHIFTMODE0 (Mode0)|| IMA3: SetShiftMode (T0) -> SHIFTMODE0 (Mode0);
BIU0:Wait 0 || IMA1: Wait 10 || BIU2:Wait 15 || BIU1:Wait 0 || IMA2: Wait 10 || BIU3:Wait 15 ;
MFetch:LPTO %IFFT4096DataTurnAsmCyc0 @(KI0 - 0); //dm2 cycle
MFetch:LPTO %IFFT4096DataTurnAsmCyc1 @(KI2 - 0); //4096 cycle
BIU0:Load(T0)(A++) -> IMA1.T0(Mode0)|| IMA1: 0+T0*T2(SHIFTMODE0)(C) (S) (SSS)(P) -> BIU2.T0 (Mode0)|| BIU2:Store(T0,T2)(A++)(Mode0)|| BIU1:Load(T0)(A++) -> IMA2.T0(Mode0)|| IMA2: 0+T0*T2(SHIFTMODE0) (C)(S) (SSS)(P) -> BIU3.T0 (Mode0)|| BIU3:Store(T0,T2)(A++)(Mode0);
IFFT4096DataTurnAsmCyc1:
IFFT4096DataTurnAsmCyc0:
BIU0:Wait 0 || BIU1:Wait 0 || BIU2:Wait 0 || BIU3:Wait 0 || IMA0: Wait 0 || IMA1: Wait 0 || IMA2: Wait 0 || IMA3: Wait 0 || R0:Wait 0 || R1:Wait 0 || R2:Wait 0 || R3:Wait 0 || SHU0:Wait 0 || SHU1:Wait 0 || SHU2:Wait 0 || SHU3:Wait 0 ;
MFetch:REPEAT @(17);
MFetch:MPU.STOP;

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MicroCode/Channel_Equ/src/spu/AddCP.s.c Normal file
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#include <AddCP.h>
void AddCP(int ConfigBaseAddr,int Nport,int Nsymbol,int CPLength0,int CPLength1,int InputAddr0,int InputAddr1,int OutputAddr0,int OutputAddr1,int CalAddr){
if (Nsymbol*Nport==1)
{Nsymbol=2;}
//cycle
const unsigned int addr_move_base = ConfigBaseAddr;
volatile unsigned int *addr_move = (volatile unsigned int *)addr_move_base;
int KI0=((Nsymbol*Nport+1)>>1)-1;
addr_move[0] = KI0;
addr_move[1] = 0x100;//4096
int CPcycle1=CPLength0>>4;//352/16
int CPcycle2=CPLength1>>4;//288/16
addr_move[2] = CPcycle1>>1;
addr_move[3] = CPcycle2>>1;
if (Nport==1)
addr_move[4] = CPcycle2>>1;
else
addr_move[4] = CPcycle1>>1;
//BIU
const unsigned int addr_biu_base1 = ConfigBaseAddr+0x40;
volatile unsigned int *addr_biu1 = (volatile unsigned int *)addr_biu_base1;
//BIU0.T0
addr_biu1[0] = InputAddr0;
addr_biu1[1] = InputAddr0;
addr_biu1[2] = InputAddr0;
addr_biu1[3] = InputAddr0;
//BIU1.T0
addr_biu1[0+16] = InputAddr1;
addr_biu1[1+16] = InputAddr1;
addr_biu1[2+16] = InputAddr1;
addr_biu1[3+16] = InputAddr1;
//BIU2.T1 symbol1
int output_data_addr_cp1=OutputAddr0+CPLength0*4;
addr_biu1[0+16*2] = output_data_addr_cp1;
addr_biu1[1+16*2] = output_data_addr_cp1;
addr_biu1[2+16*2] = output_data_addr_cp1;
addr_biu1[3+16*2] = output_data_addr_cp1;
//BIU2.T2 symbol2-4 dm0
int output_data_addr_cp2=OutputAddr0+0x4000+CPLength0*4+CPLength1*4;
addr_biu1[0+16*3] = output_data_addr_cp2;
addr_biu1[1+16*3] = output_data_addr_cp2;
addr_biu1[2+16*3] = output_data_addr_cp2;
addr_biu1[3+16*3] = output_data_addr_cp2;
addr_biu1[5+16*3] = 0x4000+CPLength1*4;
if (Nport==1){
output_data_addr_cp1=OutputAddr1+CPLength1*4;
output_data_addr_cp2=OutputAddr1+0x4000+CPLength1*2*4;
}
else
{
output_data_addr_cp1=OutputAddr1+CPLength0*4;
output_data_addr_cp2=OutputAddr1+0x4000+CPLength0*4+CPLength1*4;
}
//BIU3.T1 symbol1 dm1
addr_biu1[0+16*4] = output_data_addr_cp1;
addr_biu1[1+16*4] = output_data_addr_cp1;
addr_biu1[2+16*4] = output_data_addr_cp1;
addr_biu1[3+16*4] = output_data_addr_cp1;
//BIU3.T2 symbol2-7 dm1
addr_biu1[0+16*5] = output_data_addr_cp2;
addr_biu1[1+16*5] = output_data_addr_cp2;
addr_biu1[2+16*5] = output_data_addr_cp2;
addr_biu1[3+16*5] = output_data_addr_cp2;
addr_biu1[5+16*5] = 0x4000+CPLength1*4;
//add cp
//BIU0.T1 cp1
int take_addr_cp1=OutputAddr0+0x4000;
addr_biu1[0+16*6] = take_addr_cp1;
addr_biu1[1+16*6] = take_addr_cp1;
addr_biu1[2+16*6] = take_addr_cp1;
addr_biu1[3+16*6] = take_addr_cp1;
//BIU0.T2 cp2-4 dm0
int take_addr_cp2=OutputAddr0+0x8000+(CPLength0<<2);
addr_biu1[0+16*7] = take_addr_cp2;
addr_biu1[1+16*7] = take_addr_cp2;
addr_biu1[2+16*7] = take_addr_cp2;
addr_biu1[3+16*7] = take_addr_cp2;
addr_biu1[5+16*7] = 0x4000+CPLength1*4;
addr_biu1[8+16*7] = CPcycle2+(CPcycle2<<16);
if (Nport==1){
take_addr_cp1=OutputAddr1+0x4000;
take_addr_cp2=OutputAddr1+0x8000+(CPLength1<<2);
}
else
{
take_addr_cp1=OutputAddr1+0x4000;
take_addr_cp2=OutputAddr1+0x8000+(CPLength0<<2);
}
//BIU1.T1 cp1 dm1
addr_biu1[0+16*8] = take_addr_cp1;
addr_biu1[1+16*8] = take_addr_cp1;
addr_biu1[2+16*8] = take_addr_cp1;
addr_biu1[3+16*8] = take_addr_cp1;
//BIU1.T2 cp5-7 dm1
addr_biu1[0+16*9] = take_addr_cp2;
addr_biu1[1+16*9] = take_addr_cp2;
addr_biu1[2+16*9] = take_addr_cp2;
addr_biu1[3+16*9] = take_addr_cp2;
addr_biu1[5+16*9] = 0x4000+CPLength1*4;
addr_biu1[8+16*9] = CPcycle2+(CPcycle2<<16);
//output cp
//BIU2.T1 cp1
int output_addr_cp1=OutputAddr0;
addr_biu1[0+16*10] = output_addr_cp1;
addr_biu1[1+16*10] = output_addr_cp1;
addr_biu1[2+16*10] = output_addr_cp1;
addr_biu1[3+16*10] = output_addr_cp1;
//BIU2.T2 cp2-7
int output_addr_cp2=OutputAddr0+0x4000+CPLength0*4;
addr_biu1[0+16*11] = output_addr_cp2;
addr_biu1[1+16*11] = output_addr_cp2;
addr_biu1[2+16*11] = output_addr_cp2;
addr_biu1[3+16*11] = output_addr_cp2;
addr_biu1[5+16*11] = 0x4000+CPLength1*4;
addr_biu1[8+16*11] = CPcycle2+(CPcycle2<<16);
if (Nport==1){
output_addr_cp1=OutputAddr1;
output_addr_cp2=OutputAddr1+0x4000+CPLength1*4;
}
else
{
output_addr_cp1=OutputAddr1;
output_addr_cp2=OutputAddr1+0x4000+CPLength0*4;
}
//BIU3.T1
addr_biu1[0+16*12] = output_addr_cp1;
addr_biu1[1+16*12] = output_addr_cp1;
addr_biu1[2+16*12] = output_addr_cp1;
addr_biu1[3+16*12] = output_addr_cp1;
//BIU3.T2
addr_biu1[0+16*13] = output_addr_cp2;
addr_biu1[1+16*13] = output_addr_cp2;
addr_biu1[2+16*13] = output_addr_cp2;
addr_biu1[3+16*13] = output_addr_cp2;
addr_biu1[5+16*11] = 0x4000+CPLength1*4;
addr_biu1[8+16*11] = CPcycle2+(CPcycle2<<16);
//input phasefactor
addr_biu1[0+16*14] = CalAddr;
addr_biu1[1+16*14] = CalAddr;
addr_biu1[2+16*14] = CalAddr;
addr_biu1[3+16*14] = CalAddr;
if (Nport==1){
addr_biu1[4+16*14] = 0x40;
}
else
{
addr_biu1[4+16*14] = 0;
}
}

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MicroCode/Channel_Equ/src/spu/Equalizer_1port.s.c Normal file
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#include <Equalizer_1port.h>
#include "ucps2.h"
#include "ucpm2.h"
void EQ21Part1(int* ConfigBaseAddr,int NRE,int Nsymbol,int InputAddr0,int InputAddr1,int InputAddr2,int OutputAddr0,int OutputAddr1,int OutputAddr2,int OutputAddr3){
int *addr_move = ConfigBaseAddr;
//data cycle
int cycle=((NRE+15)>>4)*Nsymbol;
addr_move[0] = cycle;
int KBNum = (((NRE + 15) >> 4) << 6)* (Nsymbol - 1) + NRE*4;
int SymbolStep = ((NRE+15)>>4) << 6;//NRE*4;
int KI = (NRE+15)>>4;
//intput h
addr_move[0+16] = InputAddr0;
addr_move[1+16] = InputAddr0;
addr_move[2+16] = InputAddr0;
addr_move[4+16] = NRE * 4;
addr_move[6+16] = NRE * 4 * 2;
addr_move[9+16] = (KI<<16)+KI;
addr_move[10+16] = (Nsymbol<<16)+Nsymbol;
//input noise
addr_move[0+16*2] = InputAddr1;
addr_move[1+16*2] = InputAddr1;
addr_move[8+16*2] = (KI<<16)+KI;
//intput y
addr_move[0+16*3] = InputAddr2;
addr_move[1+16*3] = InputAddr2;
addr_move[2+16*3] = InputAddr2;
addr_move[4+16*3] = NRE<<2;
addr_move[6+16*3] = NRE*4*2;
addr_move[9+16*3] = (KI<<16)+KI;
addr_move[10+16*3] = (Nsymbol<<16)+Nsymbol;
//output invHH'
addr_move[0+16*4] = OutputAddr1;
addr_move[1+16*4] = OutputAddr1;
addr_move[5+16*4] = NRE<<2;
addr_move[8+16*4] = (KI<<16)+KI;
addr_move[9+16*4] = (Nsymbol<<16)+Nsymbol;
addr_move[12+16*4] = KBNum;
//output MF
addr_move[0+16*5] = OutputAddr2;
addr_move[1+16*5] = OutputAddr2;
addr_move[5+16*5] = NRE<<2;
addr_move[8+16*5] = (KI<<16)+KI;
addr_move[9+16*5] = (Nsymbol<<16)+Nsymbol;
addr_move[12+16*5] = KBNum;
//output Qtemp QMF
addr_move[0+16*6] = OutputAddr3;
addr_move[1+16*6] = OutputAddr3;
addr_move[2+16*6] = OutputAddr3;
addr_move[4+16*6] = SymbolStep;
addr_move[6+16*6] = SymbolStep * 2;
addr_move[9+16*6] = (KI<<16)+KI;
addr_move[10+16*6] = (Nsymbol<<16)+Nsymbol;
//output H'H>>13
addr_move[0+16*7] = OutputAddr0;
addr_move[1+16*7] = OutputAddr0;
addr_move[5+16*7] = NRE<<2;
addr_move[8+16*7] = (KI<<16)+KI;
addr_move[9+16*7] = (Nsymbol<<16)+Nsymbol;
addr_move[12+16*7] = KBNum;
return;
}
void EQ1Part2(int* ConfigBaseAddr,int NRE,int Nsymbol,int InputAddr0,int InputAddr1,int InputAddr2,int InputAddr3,int OutputAddr0,int OutputAddr1){
int *addr_move = ConfigBaseAddr;
//data cycle
int cycle=((NRE+15)>>4)*Nsymbol;
addr_move[0] = cycle;
int KBNum_EQ = (((NRE + 15) >> 4) << 4)*4 * (Nsymbol - 1) + NRE*4;
int KBNum_MMSE = (((NRE + 15) >> 4) << 4)*2 * (Nsymbol - 1) + NRE*2;
int SymbolStep = ((NRE+15)>>4) << 6;//NRE*4;
int KI = (NRE+15)>>4;
//input invh'h
addr_move[0+16] = InputAddr1;
addr_move[1+16] = InputAddr1;
addr_move[5+16] = NRE<<2;
addr_move[8+16] = (KI<<16)+KI;
addr_move[9+16] = (Nsymbol<<16)+Nsymbol;
//addr_move[12+16] = KBNum;
//input MF
addr_move[0+16*2] = InputAddr2;
addr_move[1+16*2] = InputAddr2;
addr_move[5+16*2] = NRE<<2;
addr_move[8+16*2] = (KI<<16)+KI;
addr_move[9+16*2] = (Nsymbol<<16)+Nsymbol;
//addr_move[12+16*2] = KBNum;
//input Qtemp0 QMF
addr_move[0+16*3] = InputAddr3;
addr_move[1+16*3] = InputAddr3;
addr_move[2+16*3] = InputAddr3;
addr_move[4+16*3] = SymbolStep;
addr_move[6+16*3] = SymbolStep * 2;
addr_move[9+16*3] = (KI<<16)+KI;
addr_move[10+16*3] = (Nsymbol<<16)+Nsymbol;
//addr_move[12+16*3] = KBNum;
//input H'H >> 13
addr_move[0+16*4] = InputAddr0;
addr_move[1+16*4] = InputAddr0;
addr_move[5+16*4] = NRE<<2;
addr_move[8+16*4] = (KI<<16)+KI;
addr_move[9+16*4] = (Nsymbol<<16)+Nsymbol;
//addr_move[12+16*4] = KBNum;
//out EQ
addr_move[0+16*5] = OutputAddr0;
addr_move[1+16*5] = OutputAddr0;
addr_move[5+16*5] = NRE<<2;
addr_move[8+16*5] = (KI<<16)+KI;
addr_move[9+16*5] = (Nsymbol<<16)+Nsymbol;
addr_move[12+16*5] = KBNum_EQ;
//output gainMMSE
addr_move[0+16*6] = OutputAddr1;
addr_move[1+16*6] = OutputAddr1;
addr_move[5+16*6] = NRE*2;
addr_move[8+16*6] = (KI<<16)+KI;
addr_move[9+16*6] = (Nsymbol<<16)+Nsymbol;
addr_move[12+16*6] = KBNum_MMSE;
return;
}

197
MicroCode/Channel_Equ/src/spu/Fft4096Int32.s.c Normal file
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void Fft4096Int32(
int Config,
int numSym,
int Scale,
int *ShiftFactor,
int in_WnAddr,
int io_Addr0,
int io_Addr1,
int io_Addr2,
int io_Addr3,
int out_ScaleAddr0,
int out_ScaleAddr1
)
{
volatile int *Para = (volatile int *)Config;
//m[00]:KIs
Para[0 * 16 + 0] = numSym;
Para[0 * 16 + 1] = 256;
Para[0 * 16 + 2] = numSym * 256;
Para[0 * 16 + 3] = 2;
//m[01]:load(ASI)
//m[02]:load(signal)(br)
Para[2 * 16 + 0] = io_Addr0; //for ant0
Para[2 * 16 + 1] = io_Addr0;
Para[2 * 16 + 10]= (numSym << 16) | numSym;
Para[2 * 16 + 11]= io_Addr0 + 0x4000; //BaseAddr += 4096Words
Para[2 * 16 + 14]= io_Addr1; //for ant1
Para[2 * 16 + 15]= io_Addr1 + 0x4000;
//m[03]:store(fft_1_4)
Para[3 * 16 + 0] = io_Addr2; //for ant0
Para[3 * 16 + 1] = io_Addr2;
Para[3 * 16 + 2] = io_Addr2;
Para[3 * 16 + 3] = io_Addr2;
Para[3 * 16 + 11]= io_Addr3; //for ant1
//m[04]:factors
Para[4 * 16 + 0] = (0x3f - ShiftFactor[0]) & 0x3f;
Para[4 * 16 + 1] = (- ShiftFactor[1]) & 0x3f;
Para[4 * 16 + 2] = (- ShiftFactor[2]) & 0x3f;
Para[4 * 16 + 3] = (- ShiftFactor[3]) & 0x3f;
Para[4 * 16 + 4] = (- ShiftFactor[4]) & 0x3f;
Para[4 * 16 + 5] = (- ShiftFactor[5]) & 0x3f;
Para[4 * 16 + 6] = (- ShiftFactor[6]) & 0x3f;
Para[4 * 16 + 7] = (- ShiftFactor[7]) & 0x3f;
Para[4 * 16 + 8] = (- ShiftFactor[8]) & 0x3f;
Para[4 * 16 + 9] = (- ShiftFactor[9]) & 0x3f;
Para[4 * 16 +10] = (- ShiftFactor[10]) & 0x3f;
Para[4 * 16 +11] = (- ShiftFactor[11]) & 0x3f;
//m[05]:load(Wn_1-4)
Para[5 * 16 + 0] = in_WnAddr;
//m[06]:shu(Wn) for fft_2
//m[07]:shu(Wn) for fft_3
//m[08]:shu(Wn) for fft_4
/*m[09]:shu(signal) for fft_1A*/
/*m[10]:shu(signal) for fft_1B*/
/*m[11]:shu(signal) for fft_1A*/
/*m[12]:shu(signal) for fft_1B*/
/*m[13]:shu(signal) for fft_2A*/
/*m[14]:shu(signal) for fft_2B*/
/*m[15]:shu(signal) for fft_3A*/
/*m[16]:shu(signal) for fft_3A*/
/*m[17]:load fft_4 in col, 16 dwords/cow */
Para[17 * 16 + 0] = io_Addr2; //for ant0
Para[17 * 16 + 1] = io_Addr2;
Para[17 * 16 + 9] = (numSym << 16) | numSym;
Para[17 * 16 + 10]= 0x00020002; //for 2 ants
Para[17 * 16 + 11]= io_Addr3; //for ant1
/*m[18]:store fft_8 in col, 16 dwords/cow */
Para[18 * 16 + 0] = io_Addr0; //for ant0
Para[18 * 16 + 1] = io_Addr0;
Para[18 * 16 + 2] = io_Addr0;
Para[18 * 16 + 10] = (numSym << 16) | numSym;
Para[18 * 16 + 11]= io_Addr1; //for ant1
/*m[19]:load Wn_5 */
/*m[20]:load Wn_6 */
/*m[21]:load Wn_7 */
/*m[22]:load Wn_8 */
Para[19 * 16 + 0] = in_WnAddr + 15 * 8;
Para[20 * 16 + 0] = in_WnAddr + 31 * 8;
Para[21 * 16 + 0] = in_WnAddr + 63 * 8;
Para[22 * 16 + 0] = in_WnAddr + 127 * 8;
/*m[23]:shu(Wn) for fft_5 */
/*m[24]:shu(Wn) for fft_6 */
/*m[25]:shu(Wn) for fft_7 */
/*m[26]:shu(Wn) for fft_8 */
/*m[27]:shu for fft_5A_9A */
/*m[28]:shu for fft_5B_9B */
/*m[29]:shu for fft_6A_10A */
/*m[30]:shu for fft_6B_10B */
/*m[31]:shu for fft_7A_11A */
/*m[32]:shu for fft_7B_11B */
/*m[33]:shu for fft_8A_12A */
/*m[34]:shu for fft_8B_12B */
/*m[35]:load fft_8 in row, 16 dwords/row */
Para[35 * 16 + 0] = io_Addr0; //for ant0
Para[35 * 16 + 1] = io_Addr0;
Para[35 * 16 + 2] = io_Addr0;
Para[35 * 16 + 3] = io_Addr0;
Para[35 * 16 + 11]= io_Addr1; //for ant1
/*m[36]:store fft_12 in row, 16 dwords/row */
Para[36 * 16 + 0] = io_Addr2; //for ant0
Para[36 * 16 + 1] = io_Addr2;
Para[36 * 16 + 2] = io_Addr2;
Para[36 * 16 +10] = (numSym << 16) | numSym;
Para[36 * 16 + 11]= io_Addr3; //for ant1
/*m[37]:load Wn_9_12_t */
Para[37 * 16 + 0] = in_WnAddr + 255 * 8;
Para[37 * 16 + 1] = in_WnAddr + 255 * 8;
Para[37 * 16 + 2] = in_WnAddr + 255 * 8;
//m[38]:load fft_int32_0 in row
Para[38 * 16 + 0] = io_Addr2; //for ant0
Para[38 * 16 + 1] = io_Addr2;
Para[38 * 16 + 9] = (numSym << 16) | numSym;
//m[39]:store 16 MinFirst1_0 in row
Para[39 * 16 + 0] = io_Addr0; //for ant0
Para[39 * 16 + 8] = (numSym << 16) | numSym;
//m[40]:load fft_int32_1 in row
Para[40 * 16 + 0] = io_Addr3; //for ant1
Para[40 * 16 + 1] = io_Addr3;
Para[40 * 16 + 9] = (numSym << 16) | numSym;
//m[41]:store 16 MinFirst1_1 in row
Para[41 * 16 + 0] = io_Addr1; //for ant1
Para[41 * 16 + 8] = (numSym << 16) | numSym;
//m[42]:load 16 MinFirst1_0 in col
Para[42 * 16 + 0] = io_Addr0; //for ant0
//m[43]:load 16 MinFirst1_1 in col
Para[43 * 16 + 0] = io_Addr1; //for ant1
//m[44]:scale = 13 for now
Para[44 * 16 + 0] = 31 - Scale;
Para[44 * 16 + 1] = ShiftFactor[0] + 6; //标值输出偏置
/****************************************************************************************\
FFT_scale = Scale-ceil(log2(double(max(max(abs(real(data_out))),max(abs(imag(data_out)))))))+6+ShiftFactor[0];
FFT_scale = 13-ceil(log2(double(max(max(abs(real(data_out))),max(abs(imag(data_out))))))) + 6 + ShiftFactor[0]
= 13 - (31 - min(first1)) + 6 + ShiftFactor[0]
= 6 + ShiftFactor[0] - (18 - min(first1));
\****************************************************************************************/
//m[45]:shu for get fft_int16,scale extraction
//m[46]:store fft_int16_0
Para[46 * 16 + 0] = io_Addr0; //for ant0
Para[46 * 16 + 1] = io_Addr0;
Para[46 * 16 + 9] = (numSym << 16) | numSym;
//m[47]:store fft_int16_1
Para[47 * 16 + 0] = io_Addr1; //for ant1
Para[47 * 16 + 1] = io_Addr1;
Para[47 * 16 + 9] = (numSym << 16) | numSym;
//m[48]:copy fft_int16_0 from io_Addr0
Para[48 * 16 + 0] = io_Addr0; //for ant0
Para[48 * 16 + 1] = io_Addr0;
Para[48 * 16 + 9] = (numSym << 16) | numSym;
//m[49]:copy fft_int16_1 from io_Addr1
Para[49 * 16 + 0] = io_Addr1; //for ant1
Para[49 * 16 + 1] = io_Addr1;
Para[49 * 16 + 9] = (numSym << 16) | numSym;
//m[50]:copy fft_int16_0 to io_Addr2
Para[50 * 16 + 0] = io_Addr2; //for ant0
Para[50 * 16 + 1] = io_Addr2;
Para[50 * 16 + 9] = (numSym << 16) | numSym;
//m[51]:copy fft_int16_1 to io_Addr3
Para[51 * 16 + 0] = io_Addr3; //for ant1
Para[51 * 16 + 1] = io_Addr3;
Para[51 * 16 + 9] = (numSym << 16) | numSym;
//m[52]:scale output
Para[52 * 16 + 0] = out_ScaleAddr0; //for ant0
Para[52 * 16 + 1] = out_ScaleAddr1; //for ant1
}

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MicroCode/Channel_Equ/src/spu/IFFT4096.s.c Normal file
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#include <IFFT4096.h>
void IFFT4096(int ConfigBaseAddr,int Nsymbol,int Temp0,int Temp1,int InOutAddr0,int InOutAddr1,int CalAddr0,int CalAddr1,int CalAddr2){
int addr_move1 = (int)ConfigBaseAddr;
int *addr_move = (int *)addr_move1;
int a=Nsymbol;
addr_move[2] = a;
addr_move[4] = a;
//reset BIU0 1
addr_move[0+16*1] = InOutAddr0;
addr_move[0+16*2] = InOutAddr1;
//BIU0.T2 1
addr_move[0+16*3] = InOutAddr0;
addr_move[1+16*3] = InOutAddr0;
addr_move[2+16*3] = InOutAddr0;
//BIU1.T2 2
addr_move[0+16*4] = InOutAddr1;
addr_move[1+16*4] = InOutAddr1;
addr_move[2+16*4] = InOutAddr1;
//BIU2.T1 3
addr_move[0+16*5] = Temp0;
addr_move[1+16*5] = Temp0;
addr_move[2+16*5] = Temp0;
//BIU2.T2 4
addr_move[0+16*6] = Temp0+0x2000;
addr_move[1+16*6] = Temp0+0x2000;
addr_move[2+16*6] = Temp0+0x2000;
//BIU3.T1 5
addr_move[0+16*7] = Temp1+0x400;
addr_move[1+16*7] = Temp1+0x400;
addr_move[2+16*7] = Temp1+0x400;
//BIU3.T2 6
addr_move[0+16*8] = Temp1+0x2400;
addr_move[1+16*8] = Temp1+0x2400;
addr_move[2+16*8] = Temp1+0x2400;
//shiftmode 1-6
addr_move[0+16*9] = CalAddr2;
addr_move[1+16*9] = CalAddr2;
addr_move[2+16*9] = CalAddr2;
addr_move[3+16*9] = CalAddr2;
//shiftmode 1-6
addr_move[0+16*10] = CalAddr2;
addr_move[1+16*10] = CalAddr2;
addr_move[2+16*10] = CalAddr2;
addr_move[3+16*10] = CalAddr2;
//prog 6-12
unsigned int addr_biu_base2 = (int)ConfigBaseAddr+0x680;
unsigned int *addr_biu2 = (unsigned int *)addr_biu_base2;
//BIU2.T1
addr_biu2[0] = InOutAddr0;
addr_biu2[1] = InOutAddr0;
addr_biu2[2] = InOutAddr0;
addr_biu2[3] = InOutAddr0;
//BIU2.T2
addr_biu2[0+16] = InOutAddr0+0x2000;
addr_biu2[1+16] = InOutAddr0+0x2000;
addr_biu2[2+16] = InOutAddr0+0x2000;
addr_biu2[3+16] = InOutAddr0+0x2000;
//BIU3.T1
addr_biu2[0+16*2] = InOutAddr1;
addr_biu2[1+16*2] = InOutAddr1;
addr_biu2[2+16*2] = InOutAddr1;
addr_biu2[3+16*2] = InOutAddr1;
//BIU3.T2
addr_biu2[0+16*3] = InOutAddr1+0x2000;
addr_biu2[1+16*3] = InOutAddr1+0x2000;
addr_biu2[2+16*3] = InOutAddr1+0x2000;
addr_biu2[3+16*3] = InOutAddr1+0x2000;
//BIU0.T2
addr_biu2[0+16*4] = Temp0;
addr_biu2[1+16*4] = Temp0;
addr_biu2[2+16*4] = Temp0;
addr_biu2[3+16*4] = Temp0;
//BIU1.T2
addr_biu2[0+16*5] = Temp1+0x400;
addr_biu2[1+16*5] = Temp1+0x400;
addr_biu2[2+16*5] = Temp1+0x400;
addr_biu2[3+16*5] = Temp1+0x400;
//biu0.T0
addr_biu2[0+16*6] = Temp0;
//biu1.T0
addr_biu2[0+16*7] = Temp1+0x400;
//butterfly1
addr_biu2[0+16*8] = CalAddr0;
addr_biu2[1+16*8] = CalAddr0;
//butterfly2
addr_biu2[0+16*9] = CalAddr1;
addr_biu2[1+16*9] = CalAddr1;
//shiftmode 7-12
addr_biu2[0+16*10] = CalAddr2+0x18;
addr_biu2[1+16*10] = CalAddr2+0x18;
//shiftmode 7-12
addr_biu2[0+16*11] = CalAddr2+0x18;
addr_biu2[1+16*11] = CalAddr2+0x18;
}

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MicroCode/Channel_Equ/src/spu/IFFT4096DataTurn.s.c Normal file
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#include "IFFT4096DataTurn.h"
void IFFT4096DataTurn(int ConfigBaseAddr,int Nsymbol,int Nport,int InputAddr0,int InputAddr1,int OutputAddr0,int OutputAddr1){
//KI2
const unsigned int addr_move_base = ConfigBaseAddr;
volatile unsigned int *addr_move = (volatile unsigned int *)addr_move_base;
int a=Nsymbol;//+1;
int KSize;
int FFTSize=4096;
addr_move[0] = a;//>>1;
if (FFTSize==2048)
{
addr_move[2] = 128;
addr_move[3] = 128;
KSize=3;
}
else
{
addr_move[2] = 256;
addr_move[3] = 256;
KSize=4;
}
//prog 1-6 BIU
const unsigned int addr_biu_base1 = ConfigBaseAddr+0x40;
volatile unsigned int *addr_biu1 = (volatile unsigned int *)addr_biu_base1;
//BIU0.T0
addr_biu1[0] = InputAddr0;
addr_biu1[1] = InputAddr0;
addr_biu1[2] = InputAddr0;
addr_biu1[3] = InputAddr0;
//BIU1.T0
addr_biu1[0+16*1] = InputAddr1;
addr_biu1[1+16*1] = InputAddr1;
addr_biu1[2+16*1] = InputAddr1;
addr_biu1[3+16*1] = InputAddr1;
//BIU2.T2
addr_biu1[0+16*2] = OutputAddr0;
addr_biu1[1+16*2] = OutputAddr0;
addr_biu1[2+16*2] = OutputAddr0;
addr_biu1[3+16*2] = OutputAddr0;
addr_biu1[14+16*2] = KSize;
//BIU2.T3
addr_biu1[0+16*3] = OutputAddr1;
addr_biu1[1+16*3] = OutputAddr1;
addr_biu1[2+16*3] = OutputAddr1;
addr_biu1[3+16*3] = OutputAddr1;
addr_biu1[14+16*3] = KSize;
addr_biu1[0+16*3] = OutputAddr1;
addr_biu1[1+16*3] = OutputAddr1;
addr_biu1[2+16*3] = OutputAddr1;
addr_biu1[3+16*3] = OutputAddr1;
addr_biu1[14+16*3] = KSize;
int FRF;
if (Nport==1){
FRF=5792;//11585;
}
else{
FRF=8192;//16384;
}
addr_biu1[0+16*4] = FRF;
addr_biu1[1+16*4] = FRF;
addr_biu1[2+16*4] = FRF;
addr_biu1[3+16*4] = FRF;
addr_biu1[4+16*4] = FRF;
addr_biu1[5+16*4] = FRF;
addr_biu1[6+16*4] = FRF;
addr_biu1[7+16*4] = FRF;
addr_biu1[8+16*4] = FRF;
addr_biu1[9+16*4] = FRF;
addr_biu1[10+16*4] = FRF;
addr_biu1[11+16*4] = FRF;
addr_biu1[12+16*4] = FRF;
addr_biu1[13+16*4] = FRF;
addr_biu1[14+16*4] = FRF;
addr_biu1[15+16*4] = FRF;
}

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MicroCode/Channel_Est/inc/ChannelEst.h Normal file
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#ifndef CHANNELEST_H_
#define CHANNELEST_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void channelEstAsm(v16u32 src);
void ChannelEst(int *ConfigAddr, int InAddr1, int InAddr2, int OutAddr);
#endif /* MATRIX_H_ */

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MicroCode/Channel_Est/inc/ConfigMatrix.dat Normal file
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//ShiftMode
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
0x0000020f,
//InputA
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0x04000400,
0x00200020,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//InputB
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000004,
0x00000000,
0x00000000,
0x04000400,
0x00200020,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//Output
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000004,
0x00000000,
0x00000000,
0x00000000,
0x00000020,
0x00000000,
0x00000000,
0x00000000,
0x003fffff,
0x0000000e,
0x00000000,
0x00000000,
//ki
0x00000400,
0x00000020,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,

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MicroCode/Channel_Est/inc/Pilot_orig_hex.dat Normal file
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113
MicroCode/Channel_Est/src/mpu0/channelEstAsm.m0.asm Normal file
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.section .text.m0, "ax"
.file "channelEstAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global channelEstAsm
channelEstAsm:
R1:M[0]->BIU1.T0;
NOP;
NOP;
NOP;
NOP;
NOP;
BIU1:Load(T0)(A++) -> M[0](Mode0);
BIU1:Load(T0)(A++) -> M[1](Mode0);//InputA
BIU1:Load(T0)(A++) -> M[2](Mode0);//InputB
BIU1:Load(T0)(A++) -> M[3](Mode0);//Output
BIU1:Load(T0)(A++) -> M[63](Mode0);//ki
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
R0:M[0] -> IMA0.T0(Mode0);
R0:M[0] -> IMA1.T0(Mode0);
R3:M[1] -> BIU3.T1(Mode0);
R3:M[2] -> BIU3.T2(Mode0) || R2:M[0] -> IMA2.T0(Mode0);
R2:M[3] -> BIU2.T0(Mode0);//output1
R1:M[4] -> BIU1.T0(Mode0);//output2
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
IMA0:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA1:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
IMA2:SetShiftMode(T0) -> SHIFTMODE0(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
R5:PreConfig(M[63])(Mode0);
R5:WriteConf(Mfetch)->KI[0-3](Mode0);
R5:WriteConf(Mfetch)->KI[4-7](Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
MFetch:LPTO %Double @(KI1 - 0);
IMA0:0+0*0(ShiftMode0)(C)(B)(SSS)(T) -> IMA0.MR(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
MFetch:LPTO %ComplexMult_Loop @(KI0 - 0);
BIU3:Load(T1)(A++)-> IMA0.T1(Mode0); // 向量A元素
BIU3:Load(T2)(A++)-> IMA0.T2(Mode0); // 向量B元素
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// 进行复数乘法
IMA0: MR+T1*T2(ShiftMode0)(C)(S)(SSS)(T) -> IMA0.MR(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
//IMA1: T2 + T3(S)(T) -> IMA1.T3(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
ComplexMult_Loop:
IMA0: MR + 0*0(ShiftMode0)(C)(S)(SSS)(T) -> BIU2.T1(Mode0);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
BIU2:Store(T1,T0)(Mode0)(A++);
NOP;
Double:
MFetch:Repeat @(10);
MFetch:MPU.STOP;

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MicroCode/Channel_Est/src/spu/ChannelEst.s.c Normal file
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#include <ChannelEst.h>
#include "ucps2.h"
#include "ucpm2.h"
void ChannelEst(int *ConfigAddr, int InAddr1, int InAddr2, int OutAddr)
{
int *Para = ConfigAddr;
Para[16*1+0] = InAddr1;
Para[16*1+1] = InAddr1;
Para[16*2+0] = InAddr2;
Para[16*2+1] = InAddr2;
Para[16*3+0] = OutAddr;
return ;
}

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MicroCode/Fre_comp/inc/cordicSC.h Normal file
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#ifndef CORDICSC_H_
#define CORDICSC_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void cordicSCAsm(v16u32 src);
void cordicSC(int* ConfigBaseAddr,int InputAddr0,int OutputAddr0,int increment,int count);
#endif

11
MicroCode/Fre_comp/inc/freOffComp.h Normal file
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#if 1
#ifndef FREOFFCOMP_H_
#define FREOFFCOMP_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void freOffCompAsm(v16u32 src);
void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1, int OutputAddr0);
#endif
#endif /* FREQOFFSETEST_H_ */

109
MicroCode/Fre_comp/src/mpu0/cordicSCAsm.m0.asm Normal file
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.section .text.m0, "ax"
.file "cordicSCAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global cordicSCAsm
cordicSCAsm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
NOP;
BIU1: Load(T0)(A++) -> M[20]; //K
BIU1: Load(T0)(A++) -> M[1]; // input freOffEstValue
BIU1: Load(T0)(A++) -> M[2]; // Index T6
BIU1: Load(T0)(A++) -> M[3]; // Theta
BIU1: Load(T0)(A++) -> M[4]; // INdex T7
BIU1: Load(T0)(A++) -> M[5]; // PI
BIU1: Load(T0)(A++) -> M[6]; // Output
MFetch: REPEAT @(5);
R5: PreConfig(M[20]);
R5: WriteConf(Mfetch) -> KI[0-15](Mode0);
MFetch: REPEAT @(10);
R4: M[1] -> BIU0.T0(Mode0);
R5: M[2] -> SHU1.T6(Mode0);
R0: M[3] -> SHU0.T1(Mode0);
R1: M[4] -> SHU0.T7(Mode0);
R2: M[6] -> BIU2.T1(Mode0);
R5: M[20] -> IMA0.T4(Mode0);
IMA1: V(0) -> IMA1.T0 || IMA2: V(0) -> IMA2.T0;
IMA3: V(0) -> IMA3.T0; // y0
IMA1: VHigh(T0,0x8000) -> IMA1.T3 || IMA2: VHigh(T0,0x4000) -> IMA1.T1;
IMA3: VHigh(T0,0xc000) -> IMA1.T2;
IMA3: V(1024) -> IMA3.T1;NOP; // x0
IMA3: VHigh(T1,0) -> IMA3.T1;NOP;
BIU0: Load(T0) -> IMA1.T0;
MFetch: REPEAT @(10);
IMA1: T0 -> IMA0.T3;NOP;
MFetch: Lpto %ENDCORDIC @(KI1);
IMA0: T3 + T4(W)(U)(T) -> IMA1.T0;NOP;NOP;
// IMA1: T0 + T0(W)(U)(T) -> IMA1.T0;NOP;
IMA1: T0 -> IMA0.T3; NOP;
IMA1: T0 + T3(W)(U)(T) -> IMA1.T4;NOP;
IMA1: T0 - T3(W)(U)(T) -> IMA1.T5;NOP;
IMA1: CompSel(T0,T1,T5,T0)(W) -> IMA1.T0;NOP;
IMA1: CompSel(T0,T2,T0,T4)(W) -> IMA1.T0;NOP;
IMA1: T0 -> IMA0.T1;
SHU1: VImm(0) -> SHU1.T0;
Mfetch: Lpto %END_ITERATIONS_16 @(KI2);
IMA0: T1 >> 8(W) -> IMA0.T2;NOP;
IMA0: T2 -> M[19];
R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0);
SHU1: T0 | T0 -> IMA3.T4 || SHU0: Index(T1,T7)(T7 = T7 + V(4)) -> IMA0.T0;
MFetch: REPEAT @(6);
IMA3: T1 >> T4(W) -> IMA3.T2;
IMA3: T0 >> T4(W) -> IMA3.T3;
MFetch: IF(KI3<KI11) JUMP %IFELSE_0;
IMA3: 0 - T2(W) -> IMA3.T2;
IMA0: 0 - T0(W) -> IMA0.T0;
IMA3: 0 - T3(W) -> IMA3.T3;
NOP;NOP;
IFELSE_0:
IMA0: T1 - T0(W) -> IMA0.T1;
IMA3: T0 + T2(W) -> IMA3.T0 || SHU1: T0 + V(1) -> SHU1.T0;
IMA3: T1 - T3(W) -> IMA3.T1;
NOP;NOP;
END_ITERATIONS_16:
IMA0: T3 -> BIU0.T2;
IMA3: CPRS(T0)(CprsMode1) -> IMA2.T0;
IMA3: CPRS(T1)(CprsMode1) -> IMA2.T1;
IMA2: T0 << 16(W)(U) -> IMA2.T0 || IMA3: V(0) -> IMA3.T0;
BIU0: Store(T2,T0);
IMA2: T0 + T1(W) -> BIU2.T0 || IMA3: V(1024) -> IMA3.T1;
NOP;NOP;
IMA3: VHigh(T1,0) -> IMA3.T1;
BIU2: Store(T0,T1)(A++);
ENDCORDIC:
MFetch: REPEAT @(10);
MFetch:MPU.STOP;

57
MicroCode/Fre_comp/src/mpu0/freOffCompAsm.m0.asm Normal file
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.section .text.m0, "ax"
.file "freOffCompAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global freOffCompAsm
freOffCompAsm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
NOP;
BIU1: Load(T0)(A++) -> M[20];
BIU1: Load(T0)(A++) -> M[1]; // input signal
BIU1: Load(T0)(A++) -> M[2]; // fre_offfset_est
BIU1: Load(T0)(A++) -> M[3]; // outputAddr
IMA0: V(512) -> IMA0.T0(Mode0);NOP;
IMA0: VHigh(T0,0) -> IMA0.T0(Mode0);NOP;
IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0);NOP;
R5: PreConfig(M[20]);
R5: WriteConf(Mfetch) -> KI[0-15](Mode0);
R4: M[1] -> BIU0.T0(Mode0);
R5: M[2] -> BIU1.T1(Mode0);
R3: M[3] -> BIU3.T3(Mode0);
NOP;NOP;NOP;
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
MFetch: REPEAT @(10);
MFetch: Lpto %ENDFRECOMP @(KI0);
IMA0: 0 + T2*T3(ShiftMode0)(C)(S)(SSS) -> IMA0.MR;
MFetch: REPEAT @(15);
BIU0: Load(T0) -> IMA0.T3(Mode0);
BIU1: Load(T1) -> IMA0.T2(Mode0);
IMA0: ReadMR(L) -> IMA1.T0; // real
IMA0: ReadMR(H) -> IMA2.T0; // imag
MFetch: REPEAT @(4);
IMA1: T0 >> 10(W) -> IMA0.T1 || IMA2: T0 >> 10(W) -> IMA2.T1;
MFetch: REPEAT @(2);
IMA0: CPRS(T1)(CprsMode1) -> IMA2.T2 || IMA2: CPRS(T1)(CprsMode1) -> IMA2.T3;
MFetch: REPEAT @(4);
IMA2: T3 << 16(W)(U) -> IMA2.T3;
NOP;NOP;
IMA2: T2 + T3(W) -> BIU3.T1;
NOP;NOP;
BIU3: Store(T1,T3)(A++);
ENDFRECOMP:
MFetch: REPEAT @(10);
MFetch:MPU.STOP;

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MicroCode/Fre_comp/src/spu/cordicSC.s.c Normal file
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#include <cordicSC.h>
#include "ucps2.h"
#include "ucpm2.h"
void cordicSC(int* ConfigBaseAddr,int InputAddr0,int OutputAddr0, int increment, int count){
int *Para = ConfigBaseAddr;
Para[16*0+0] = increment;
Para[16*0+1] = count;
Para[16*0+2] = 16;
//input Signal
Para[16*1+0] = InputAddr0;
Para[16*1+1] = InputAddr0;
Para[16*1+2] = InputAddr0;
//Output
Para[16*6+0] = OutputAddr0;
}

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MicroCode/Fre_comp/src/spu/freOffComp.s.c Normal file
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#include <freOffComp.h>
#include "ucps2.h"
#include "ucpm2.h"
void freOffComp(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int OutputAddr0){
int *Para = ConfigBaseAddr;
Para[16*0+0] = 480;
//input Signal
Para[16*1+0] = InputAddr0;
Para[16*1+1] = InputAddr0;
Para[16*1+2] = InputAddr0;
//input EST
Para[16*2+0] = InputAddr1;
Para[16*2+1] = InputAddr1;
Para[16*2+2] = InputAddr1;
//Output
Para[16*3+0] = OutputAddr0;
return;
}

13
MicroCode/Fre_est/inc/freOffEst.h Normal file
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#ifndef FREOFFEST_H_
#define FREOFFEST_H_
#include "ucps2.h"
#include "ucpm2.h"
MPU_ENTRY void freOffEstAsm(v16u32 src);
void freOffEst(int* ConfigBaseAddr,int InputAddr0,int InputAddr1, int freEstOutAddr);
#endif /* FREQOFFSETEST_H_ */

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MicroCode/Fre_est/src/mpu0/freOffEstAsm.m0.asm Normal file
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.section .text.m0, "ax"
.file "freOffEstAsm.m0.asm"
// DO NOT MODIFY THE CONTENT ABOVE
.global freOffEstAsm
freOffEstAsm:
R1: M[0] -> BIU1.T0;
NOP;
NOP;
NOP;
NOP;
BIU1: Load(T0)(A++) -> M[20] || IMA0: V(512) -> IMA0.T0(Mode0);
BIU1: Load(T0)(A++) -> M[1]; // sym1
BIU1: Load(T0)(A++) -> M[2]; // sym2
BIU1: Load(T0)(A++) -> M[3] || IMA0: VHigh(T0,0) -> IMA0.T0(Mode0); // Index T6
BIU1: Load(T0)(A++) -> M[4]; // Theta
BIU1: Load(T0)(A++) -> M[5] || IMA0: SetShiftMode(T0)-> ShiftMode0(Mode0); //OUT
BIU1: Load(T0)(A++) -> M[6];
BIU1: Load(T0)(A++) -> M[7]; //INDEX7
NOP;
R5: PreConfig(M[20]);
R5: WriteConf(Mfetch) -> KI[0-15](Mode0);
R4: M[1] -> BIU0.T0(Mode0);
R5: M[2] -> BIU1.T1(Mode0);
R0: M[3] -> SHU0.T6(Mode0);
R0: M[3] -> SHU1.T6(Mode0);
R4: M[4] -> SHU0.T1(Mode0);
R2: M[5] -> BIU2.T1(Mode0);
R0: M[7] -> SHU0.T7(Mode0);
IMA0: SetMR(0)(L);
IMA0: SetMR(0)(H);
NOP;
NOP;
Mfetch: Lpto %MFA @(KI0);
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 11 ;
BIU0: Load(T0)(A++) -> IMA0.T0(Mode0) || IMA0: MR + T1*T0(ShiftMode0)(C)(S)(SSS) -> IMA0.MR(Mode0);
BIU1: Load(T1)(A++) -> IMA0.T1(Mode0);
MFA:
BIU0: Wait 0 || BIU1: Wait 0 || IMA0: Wait 0 ;
MFetch: REPEAT @(15);
IMA0: ReadMR(L) -> IMA0.T0; // real
IMA0: ReadMR(H) -> IMA1.T0; // imag
NOP;NOP;NOP;NOP;
IMA0: T0 >> 12(W) -> IMA0.T0 || IMA1: T0 >> 12(W) -> IMA1.T0;
NOP;NOP;
IMA0: RAdd(T0)(W)(SlipMode1) -> SHU0.T2;
IMA1: RAdd(T0)(W)(SlipMode1) -> SHU1.T2;
SHU1: VImm(0) -> SHU1.T0;
IMA0: V(0) -> IMA0.T1;
NOP;
SHU0: Index(T2,T6) -> IMA3.T1;
SHU1: Index(T2,T6) -> IMA3.T0;
NOP;NOP;
IMA3: RAdd(T0)(W)(SlipMode1) -> IMA3.T0;
IMA3: RAdd(T1)(W)(SlipMode1) -> IMA3.T1;
MFetch: REPEAT @(5);
IMA3: T0 -> IMA2.T0;
IMA3: T1 -> IMA2.T1;
MFetch: REPEAT @(5);
//CORDIC ATAN2
Mfetch: Lpto %ENDCORDIC @(KI1);
IMA3: T0 -> M[19];
NOP;
R5: PreConfig(M[19][0]);
R5: WriteConf(Mfetch) -> KI[3](Mode0);
SHU1: T0 | T0 -> IMA3.T4 || SHU0: INdex(T1,T7)(T7 = T7 + V(4)) -> IMA0.T0;
NOP;NOP;NOP;NOP;
IMA3: T1 >> T4(W) -> IMA3.T2;
IMA3: T0 >> T4(W) -> IMA3.T3;
NOP;
MFetch: IF(KI3>=KI11) JUMP %IFFI;
IMA3: 0 - T2(W) -> IMA3.T2;
IMA0: 0 - T0(W) -> IMA0.T0;
IMA3: 0 - T3(W) -> IMA3.T3;
NOP;
IFFI:
IMA0: T1 - T0(W) -> IMA0.T1;
IMA3: T0 + T2(W) -> IMA3.T0 || SHU1: T0 + V(1) -> SHU1.T0;
IMA3: T1 - T3(W) -> IMA3.T1;
NOP;NOP;
ENDCORDIC:
MFetch: REPEAT @(10);
IMA0: T1 -> BIU2.T0(Mode0);
NOP;NOP;NOP;NOP;
BIU2: Store(T0,T1)(A++);
MFetch:MPU.STOP;

27
MicroCode/Fre_est/src/spu/freOffEst.s.c Normal file
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#include "ucps2.h"
#include "ucpm2.h"
#include <freOffEst.h>
void freOffEst(int* ConfigBaseAddr,int InputAddr0,int InputAddr1,int freEstOutAddr){
int *Para = ConfigBaseAddr;
//input Symbol0
Para[16*1+0] = InputAddr0;
Para[16*1+1] = InputAddr0;
Para[16*1+2] = InputAddr0;
//input Symbol1
Para[16*2+0] = InputAddr1;
Para[16*2+1] = InputAddr1;
Para[16*2+2] = InputAddr1;
//Output
Para[16*5+0] = freEstOutAddr;
return;
}