[root] type=Root children=system eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=System children=apc clk_domain dvfs_handler membus memdev cache_line_size=64 eventq_index=0 exit_on_work_items=false init_param=0 m5ops_base=0 mem_mode=atomic mem_ranges= memories=system.apc.DM0 system.apc.DM1 system.apc.DM2 system.apc.DM3 system.apc.DM4 system.apc.DM5 system.apc.DM6 system.apc.DM7 system.apc.ape0.mpu0.IM system.apc.ape0.spu.Stack system.apc.ape0.spu.virtmem system.apc.ddr system.apc.sharemem mmap_using_noreserve=false multi_thread=false num_work_ids=16 readfile= redirect_paths= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 workload=Null system_port=system.membus.slave[0] [system.apc] type=SubSystem children=DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 ape0 ape0_to_dev csu dbus ddr dev io_bus sharemem sysctrl timer0 timer1 eventq_index=0 thermal_domain=Null [system.apc.DM0] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM0.power_state range=2097152:2359296 port=system.apc.dbus.master[0] [system.apc.DM0.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM1] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM1.power_state range=2359296:2621440 port=system.apc.dbus.master[1] [system.apc.DM1.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM2] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM2.power_state range=2621440:2883584 port=system.apc.dbus.master[2] [system.apc.DM2.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM3] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM3.power_state range=2883584:3145728 port=system.apc.dbus.master[3] [system.apc.DM3.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM4] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM4.power_state range=3145728:3407872 port=system.apc.dbus.master[4] [system.apc.DM4.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM5] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM5.power_state range=3407872:3670016 port=system.apc.dbus.master[5] [system.apc.DM5.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM6] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM6.power_state range=3670016:3932160 port=system.apc.dbus.master[6] [system.apc.DM6.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.DM7] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=true kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.DM7.power_state range=3932160:4194304 port=system.apc.dbus.master[7] [system.apc.DM7.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0] type=MaPUAPE children=mpu0 printer spu terminal vio ELF=/home/ittc/WorkSpace/transmitter_prj/APE0/APE0.out IMHex= eventq_index=0 load_elf_sections=true mpus=system.apc.ape0.mpu0 spu=system.apc.ape0.spu start_after_load=true system=system [system.apc.ape0.mpu0] type=UCP2MPU children=IM biu_bus biu_to_DM ibus power_state DMBase=2097152 2359296 2621440 2883584 3145728 3407872 3670016 3932160 MIMBase=21474836480 check_tests=false clk_domain=system.clk_domain conflict=false core_id=0 dir_name=/home/ittc/WorkSpace/transmitter_prj/APE0/ eventq_index=0 llvm_mc_path=/home/ittc/Software/mcstudio/toolchain mreg_data_file= oupreg=false pipeline=false pipeline_path=./m5out/APC0/APE0/ power_model= power_state=system.apc.ape0.mpu0.power_state randreg=true system=system timing_mode=false trace_data_file= DataPort=system.apc.ape0.mpu0.biu_bus.slave[0] system.apc.ape0.mpu0.biu_bus.slave[1] system.apc.ape0.mpu0.biu_bus.slave[2] system.apc.ape0.mpu0.biu_bus.slave[3] FetchPort=system.apc.ape0.mpu0.ibus.slave[0] [system.apc.ape0.mpu0.IM] type=SimpleMemory children=power_state bandwidth=7.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=false kvm_map=true latency=2000 latency_var=0 null=false power_model= power_state=system.apc.ape0.mpu0.IM.power_state range=21474836480:21475098624 port=system.apc.ape0.mpu0.ibus.master[0] [system.apc.ape0.mpu0.IM.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.mpu0.biu_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.ape0.mpu0.biu_bus.power_state response_latency=1 use_default_range=false width=64 master=system.apc.ape0.mpu0.biu_to_DM.slave slave=system.apc.ape0.mpu0.DataPort[0] system.apc.ape0.mpu0.DataPort[1] system.apc.ape0.mpu0.DataPort[2] system.apc.ape0.mpu0.DataPort[3] [system.apc.ape0.mpu0.biu_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.mpu0.biu_to_DM] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.mpu0.biu_to_DM.power_state ranges=2097152:2359296 2359296:2621440 2621440:2883584 2883584:3145728 3145728:3407872 3407872:3670016 3670016:3932160 3932160:4194304 req_size=16 resp_size=16 master=system.apc.dbus.slave[1] slave=system.apc.ape0.mpu0.biu_bus.master[0] [system.apc.ape0.mpu0.biu_to_DM.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.mpu0.ibus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.ape0.mpu0.ibus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.mpu0.IM.port slave=system.apc.ape0.mpu0.FetchPort system.apc.csu.MIMPort[0] [system.apc.ape0.mpu0.ibus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.mpu0.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.printer] type=SimpleUart children=power_state big_endian=false clk_domain=system.clk_domain device=system.apc.ape0.terminal end_on_eot=false eventq_index=0 pio_addr=4294967295 pio_latency=100000 pio_size=4 platform=Null power_model= power_state=system.apc.ape0.printer.power_state system=system pio=system.apc.ape0.spu.io_bus.master[0] [system.apc.ape0.printer.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu] type=PipelinedSPU children=Stack agu0_bus agu0_to_DM agu0_to_dev agu0_to_stack agu0_to_virt agu1_bus agu1_to_DM agu1_to_dev agu1_to_stack agu1_to_virt ibus imem_bridge inst_timing00 inst_timing01 inst_timing02 inst_timing03 inst_timing04 inst_timing05 inst_timing06 inst_timing07 inst_timing08 inst_timing09 inst_timing10 inst_timing11 inst_timing12 inst_timing13 inst_timing14 inst_timing15 inst_timing16 inst_timing17 inst_timing18 inst_timing19 inst_timing20 inst_timing21 inst_timing22 inst_timing23 inst_timing24 inst_timing25 inst_timing26 inst_timing27 inst_timing28 inst_timing29 inst_timing30 inst_timing31 inst_timing32 inst_timing33 inst_timing34 inst_timing35 inst_timing36 inst_timing37 io_bus power_state stack_mem_bus virtmem virtmem_bus IMData= IMHex= IntRegInit=1 1013272124 2 4077551244 3 3089076320 4 2498267951 5 3443537879 6 3656993406 7 1371975265 8 1799229021 9 880805338 10 3865734503 11 2660174498 12 665723222 13 1547086473 14 876022786 15 2914160084 16 3949784328 17 3882833008 18 1352515433 19 2308720036 20 1850960689 21 2760904863 22 2813687224 23 2866826831 24 1108116884 25 366827863 26 1198510591 27 4264621472 28 2875440132 29 872243203 30 3571315687 31 3768156890 VecRegInit=0 274904902 2671583728 3257520761 942150128 1978258353 962212618 1233662778 4223915246 3219969477 1559075495 1549177944 178643550 3585816884 808094900 2458347933 1581535902 1 330180219 1695360684 3071915058 2966607697 314707911 1205089776 4036194335 366177179 2363179490 2984469273 461908613 1154554194 3726976857 4081542734 2654556147 449986678 2 2998759155 922276489 1662808479 939748993 3530345066 484954765 678144766 889129195 3747940522 3016198369 3901649753 3277719760 2531996829 764358190 1679070792 4056985478 3 639795586 706983084 3408223029 205952979 2990625419 2905133546 39154170 182155708 1083112638 4135956477 1524376579 371966898 2239717235 3196867487 3148603801 2592865513 blockOnMemorySwitch=false bypassCycleLimit=1 bypassOutput=false check_memory_error=false clk_domain=system.clk_domain core_id=0 dmem_base=0 eventq_index=0 executeBranchDelay=1 exit_on_test_error=false fetchBufferSize=4 fetchSize=0 flushBufferOnBranch=false flush_on_pc_events=false icache_size=65536 imem_base=0 inst_timing=system.apc.ape0.spu.inst_timing00 system.apc.ape0.spu.inst_timing01 system.apc.ape0.spu.inst_timing02 system.apc.ape0.spu.inst_timing03 system.apc.ape0.spu.inst_timing04 system.apc.ape0.spu.inst_timing05 system.apc.ape0.spu.inst_timing06 system.apc.ape0.spu.inst_timing07 system.apc.ape0.spu.inst_timing08 system.apc.ape0.spu.inst_timing09 system.apc.ape0.spu.inst_timing10 system.apc.ape0.spu.inst_timing11 system.apc.ape0.spu.inst_timing12 system.apc.ape0.spu.inst_timing13 system.apc.ape0.spu.inst_timing14 system.apc.ape0.spu.inst_timing15 system.apc.ape0.spu.inst_timing16 system.apc.ape0.spu.inst_timing17 system.apc.ape0.spu.inst_timing18 system.apc.ape0.spu.inst_timing19 system.apc.ape0.spu.inst_timing20 system.apc.ape0.spu.inst_timing21 system.apc.ape0.spu.inst_timing22 system.apc.ape0.spu.inst_timing23 system.apc.ape0.spu.inst_timing24 system.apc.ape0.spu.inst_timing25 system.apc.ape0.spu.inst_timing26 system.apc.ape0.spu.inst_timing27 system.apc.ape0.spu.inst_timing28 system.apc.ape0.spu.inst_timing29 system.apc.ape0.spu.inst_timing30 system.apc.ape0.spu.inst_timing31 system.apc.ape0.spu.inst_timing32 system.apc.ape0.spu.inst_timing33 system.apc.ape0.spu.inst_timing34 system.apc.ape0.spu.inst_timing35 system.apc.ape0.spu.inst_timing36 system.apc.ape0.spu.inst_timing37 jumpUpCacheSize=3 lsqSize=32 maxLoad=16 mpu=system.apc.ape0.mpu0 numJumpUpCaches=2 pipeline=false pipelinePath=./m5out/APC0/APE0/ power_model= power_state=system.apc.ape0.spu.power_state splitLSQ=true stack_reserved=128 system=system test_cases= wait_for_remote_gdb=true ifetch=system.apc.ape0.spu.ibus.slave[0] mem_side=system.apc.ape0.spu.agu0_bus.slave[0] system.apc.ape0.spu.agu1_bus.slave[0] [system.apc.ape0.spu.Stack] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=false kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.ape0.spu.Stack.power_state range=0:262144 port=system.apc.ape0.spu.stack_mem_bus.master[0] [system.apc.ape0.spu.Stack.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu0_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=2 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.agu0_bus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.spu.agu0_to_DM.slave system.apc.ape0.spu.agu0_to_dev.slave system.apc.ape0.spu.agu0_to_stack.slave system.apc.ape0.spu.agu0_to_virt.slave slave=system.apc.ape0.spu.mem_side[0] [system.apc.ape0.spu.agu0_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu0_to_DM] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu0_to_DM.power_state ranges=2097152:2359296 2359296:2621440 2621440:2883584 2883584:3145728 3145728:3407872 3407872:3670016 3670016:3932160 3932160:4194304 req_size=16 resp_size=16 master=system.apc.dbus.slave[2] slave=system.apc.ape0.spu.agu0_bus.master[0] [system.apc.ape0.spu.agu0_to_DM.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu0_to_dev] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu0_to_dev.power_state ranges=80904192:80936960 80936960:80969728 4194304:4456448 164626432:173015040 4294967295:4294967296 4294967248:4294967256 268435456:4294967231 72744960:72746480 req_size=16 resp_size=16 master=system.apc.ape0.spu.io_bus.slave[0] slave=system.apc.ape0.spu.agu0_bus.master[1] [system.apc.ape0.spu.agu0_to_dev.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu0_to_stack] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu0_to_stack.power_state ranges=0:262144 req_size=16 resp_size=16 master=system.apc.ape0.spu.stack_mem_bus.slave[0] slave=system.apc.ape0.spu.agu0_bus.master[2] [system.apc.ape0.spu.agu0_to_stack.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu0_to_virt] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu0_to_virt.power_state ranges=67108864:71303168 req_size=16 resp_size=16 master=system.apc.ape0.spu.virtmem_bus.slave[0] slave=system.apc.ape0.spu.agu0_bus.master[3] [system.apc.ape0.spu.agu0_to_virt.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu1_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=2 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.agu1_bus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.spu.agu1_to_DM.slave system.apc.ape0.spu.agu1_to_dev.slave system.apc.ape0.spu.agu1_to_stack.slave system.apc.ape0.spu.agu1_to_virt.slave slave=system.apc.ape0.spu.mem_side[1] [system.apc.ape0.spu.agu1_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu1_to_DM] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu1_to_DM.power_state ranges=2097152:2359296 2359296:2621440 2621440:2883584 2883584:3145728 3145728:3407872 3407872:3670016 3670016:3932160 3932160:4194304 req_size=16 resp_size=16 master=system.apc.dbus.slave[3] slave=system.apc.ape0.spu.agu1_bus.master[0] [system.apc.ape0.spu.agu1_to_DM.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu1_to_dev] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu1_to_dev.power_state ranges=80904192:80936960 80936960:80969728 4194304:4456448 164626432:173015040 4294967295:4294967296 4294967248:4294967256 268435456:4294967231 72744960:72746480 req_size=16 resp_size=16 master=system.apc.ape0.spu.io_bus.slave[1] slave=system.apc.ape0.spu.agu1_bus.master[1] [system.apc.ape0.spu.agu1_to_dev.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu1_to_stack] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu1_to_stack.power_state ranges=0:262144 req_size=16 resp_size=16 master=system.apc.ape0.spu.stack_mem_bus.slave[1] slave=system.apc.ape0.spu.agu1_bus.master[2] [system.apc.ape0.spu.agu1_to_stack.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.agu1_to_virt] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.agu1_to_virt.power_state ranges=67108864:71303168 req_size=16 resp_size=16 master=system.apc.ape0.spu.virtmem_bus.slave[1] slave=system.apc.ape0.spu.agu1_bus.master[3] [system.apc.ape0.spu.agu1_to_virt.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.ibus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.ibus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.spu.imem_bridge.slave slave=system.apc.ape0.spu.ifetch [system.apc.ape0.spu.ibus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.imem_bridge] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0.spu.imem_bridge.power_state ranges=268435456:4294967231 req_size=16 resp_size=16 master=system.apc.io_bus.slave[3] slave=system.apc.ape0.spu.ibus.master[0] [system.apc.ape0.spu.imem_bridge.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.inst_timing00] type=SPUInstTiming eventq_index=0 latency=1 0 0 0 mask=2114387968 value=1107296256 [system.apc.ape0.spu.inst_timing01] type=SPUInstTiming eventq_index=0 latency=2 mask=2114387968 value=1073741824 [system.apc.ape0.spu.inst_timing02] type=SPUInstTiming eventq_index=0 latency=2 1 mask=2080833536 value=1073807360 [system.apc.ape0.spu.inst_timing03] type=SPUInstTiming eventq_index=0 latency=2 mask=2080866304 value=1073872896 [system.apc.ape0.spu.inst_timing04] type=SPUInstTiming eventq_index=0 latency=2 mask=2114420736 value=1107558400 [system.apc.ape0.spu.inst_timing05] type=SPUInstTiming eventq_index=0 latency=3 mask=2114420736 value=1074003968 [system.apc.ape0.spu.inst_timing06] type=SPUInstTiming eventq_index=0 latency=2 mask=2080866304 value=1074102272 [system.apc.ape0.spu.inst_timing07] type=SPUInstTiming eventq_index=0 latency=0 mask=2118615040 value=1145143296 [system.apc.ape0.spu.inst_timing08] type=SPUInstTiming eventq_index=0 latency=1 0 mask=2114158592 value=1174536192 [system.apc.ape0.spu.inst_timing09] type=SPUInstTiming eventq_index=0 latency=18 mask=2080866304 value=1074233344 [system.apc.ape0.spu.inst_timing10] type=SPUInstTiming eventq_index=0 latency=1 mask=1879048192 value=1073741824 [system.apc.ape0.spu.inst_timing11] type=SPUInstTiming eventq_index=0 latency=1 mask=1614348288 value=3145728 [system.apc.ape0.spu.inst_timing12] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1611202560 value=0 [system.apc.ape0.spu.inst_timing13] type=SPUInstTiming eventq_index=0 latency=1 mask=1614348288 value=3670016 [system.apc.ape0.spu.inst_timing14] type=SPUInstTiming eventq_index=0 latency=1 mask=1611203072 value=524288 [system.apc.ape0.spu.inst_timing15] type=SPUInstTiming eventq_index=0 latency=1 mask=1886388224 value=808452096 [system.apc.ape0.spu.inst_timing16] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1883242496 value=805306368 [system.apc.ape0.spu.inst_timing17] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1611203584 value=589824 [system.apc.ape0.spu.inst_timing18] type=SPUInstTiming eventq_index=0 latency=1 mask=1073741824 value=0 [system.apc.ape0.spu.inst_timing19] type=SPUInstTiming eventq_index=0 latency=1 0 0 0 mask=2114387968 value=1912602624 [system.apc.ape0.spu.inst_timing20] type=SPUInstTiming eventq_index=0 latency=2 mask=2114387968 value=1879048192 [system.apc.ape0.spu.inst_timing21] type=SPUInstTiming eventq_index=0 latency=2 1 mask=2080833536 value=1879113728 [system.apc.ape0.spu.inst_timing22] type=SPUInstTiming eventq_index=0 latency=2 mask=2080866304 value=1879179264 [system.apc.ape0.spu.inst_timing23] type=SPUInstTiming eventq_index=0 latency=2 mask=2114420736 value=1912864768 [system.apc.ape0.spu.inst_timing24] type=SPUInstTiming eventq_index=0 latency=3 mask=2114420736 value=1879310336 [system.apc.ape0.spu.inst_timing25] type=SPUInstTiming eventq_index=0 latency=2 mask=2080866304 value=1879408640 [system.apc.ape0.spu.inst_timing26] type=SPUInstTiming eventq_index=0 latency=0 mask=2118615040 value=1950449664 [system.apc.ape0.spu.inst_timing27] type=SPUInstTiming eventq_index=0 latency=1 0 mask=2114158592 value=1979842560 [system.apc.ape0.spu.inst_timing28] type=SPUInstTiming eventq_index=0 latency=18 mask=2080866304 value=1879539712 [system.apc.ape0.spu.inst_timing29] type=SPUInstTiming eventq_index=0 latency=1 mask=1879048192 value=1879048192 [system.apc.ape0.spu.inst_timing30] type=SPUInstTiming eventq_index=0 latency=1 mask=1614348288 value=3145728 [system.apc.ape0.spu.inst_timing31] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1611202560 value=0 [system.apc.ape0.spu.inst_timing32] type=SPUInstTiming eventq_index=0 latency=1 mask=1614348288 value=3670016 [system.apc.ape0.spu.inst_timing33] type=SPUInstTiming eventq_index=0 latency=1 mask=1611203072 value=524288 [system.apc.ape0.spu.inst_timing34] type=SPUInstTiming eventq_index=0 latency=1 mask=1886388224 value=808452096 [system.apc.ape0.spu.inst_timing35] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1883242496 value=805306368 [system.apc.ape0.spu.inst_timing36] type=SPUInstTiming eventq_index=0 latency=1 1 mask=1611203584 value=589824 [system.apc.ape0.spu.inst_timing37] type=SPUInstTiming eventq_index=0 latency=1 mask=1073741824 value=0 [system.apc.ape0.spu.io_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=0 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.io_bus.power_state response_latency=0 use_default_range=false width=128 master=system.apc.ape0.printer.pio system.apc.ape0.vio.pio system.apc.ape0_to_dev.slave slave=system.apc.ape0.spu.agu0_to_dev.master system.apc.ape0.spu.agu1_to_dev.master [system.apc.ape0.spu.io_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.stack_mem_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.stack_mem_bus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.spu.Stack.port slave=system.apc.ape0.spu.agu0_to_stack.master system.apc.ape0.spu.agu1_to_stack.master system.apc.csu.IMPort[0] [system.apc.ape0.spu.stack_mem_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.virtmem] type=SimpleMemory children=power_state bandwidth=7.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=false kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.ape0.spu.virtmem.power_state range=67108864:71303168 port=system.apc.ape0.spu.virtmem_bus.master[0] [system.apc.ape0.spu.virtmem.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.spu.virtmem_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.ape0.spu.virtmem_bus.power_state response_latency=1 use_default_range=false width=128 master=system.apc.ape0.spu.virtmem.port slave=system.apc.ape0.spu.agu0_to_virt.master system.apc.ape0.spu.agu1_to_virt.master [system.apc.ape0.spu.virtmem_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0.terminal] type=Terminal eventq_index=0 number=0 outfile=stdoutput port=40337 [system.apc.ape0.vio] type=Ucp2Vio children=power_state clk_domain=system.clk_domain eventq_index=0 pio_addr=4294967248 pio_latency=100000 power_model= power_state=system.apc.ape0.vio.power_state size_bytes=8 system=system pio=system.apc.ape0.spu.io_bus.master[1] [system.apc.ape0.vio.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ape0_to_dev] type=Bridge children=power_state clk_domain=system.clk_domain delay=0 eventq_index=0 power_model= power_state=system.apc.ape0_to_dev.power_state ranges=80904192:80936960 80936960:80969728 4194304:4456448 164626432:173015040 268435456:4294967231 72744960:72746480 req_size=16 resp_size=16 master=system.apc.io_bus.slave[2] slave=system.apc.ape0.spu.io_bus.master[2] [system.apc.ape0_to_dev.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.csu] type=Ucp2Csu children=power_state DDRBase=268435456 DMBase=2097152 2359296 2621440 2883584 3145728 3407872 3670016 3932160 IMBase=0 MIMBase=21474836480 ShareMemBase=164626432 clk_domain=system.clk_domain csu_mode=APE csu_size_bytes=262144 enable=false eventq_index=0 pio_addr=4194304 pio_latency=100000 power_model= power_state=system.apc.csu.power_state spu0=system.apc.ape0.spu spu1=Null system=system DDRPort=system.apc.io_bus.slave[1] DMPort=system.apc.dbus.slave[0] IMPort=system.apc.ape0.spu.stack_mem_bus.slave[2] MIMPort=system.apc.ape0.mpu0.ibus.slave[1] ShareMemPort=system.apc.io_bus.slave[0] pio=system.apc.io_bus.master[4] [system.apc.csu.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.dbus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=0 power_model= power_state=system.apc.dbus.power_state response_latency=4 use_default_range=false width=128 master=system.apc.DM0.port system.apc.DM1.port system.apc.DM2.port system.apc.DM3.port system.apc.DM4.port system.apc.DM5.port system.apc.DM6.port system.apc.DM7.port slave=system.apc.csu.DMPort[0] system.apc.ape0.mpu0.biu_to_DM.master system.apc.ape0.spu.agu0_to_DM.master system.apc.ape0.spu.agu1_to_DM.master [system.apc.dbus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.ddr] type=SimpleMemory children=power_state bandwidth=15.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=false kvm_map=true latency=1000 latency_var=0 null=false power_model= power_state=system.apc.ddr.power_state range=268435456:4294967231 port=system.apc.io_bus.master[0] [system.apc.ddr.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.dev] type=DevController children=power_state APCNum=0 FullSys=false clk_domain=system.clk_domain csu=system.apc.csu eventq_index=0 ip=127.0.0.1 port=8888 power_model= power_state=system.apc.dev.power_state timer0=system.apc.timer0 timer1=system.apc.timer1 [system.apc.dev.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.io_bus] type=InternalBus children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=0 frontend_latency=0 power_model= power_state=system.apc.io_bus.power_state response_latency=0 use_default_range=false width=128 master=system.apc.ddr.port system.apc.sharemem.port system.apc.timer0.pio system.apc.timer1.pio system.apc.csu.pio system.apc.sysctrl.pio slave=system.apc.csu.ShareMemPort[0] system.apc.csu.DDRPort[0] system.apc.ape0_to_dev.master system.apc.ape0.spu.imem_bridge.master [system.apc.io_bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.sharemem] type=SimpleMemory children=power_state bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true eventq_index=0 hex8_file= image_file= in_addr_map=true init_randomized=false kvm_map=true latency=30000 latency_var=0 null=false power_model= power_state=system.apc.sharemem.power_state range=164626432:173015040 port=system.apc.io_bus.master[1] [system.apc.sharemem.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.sysctrl] type=Ucp2SysCtrl children=power_state apc_id=0 clk_domain=system.clk_domain csu=system.apc.csu enable=false eventq_index=0 pio_addr=72744960 pio_latency=100000 power_model= power_state=system.apc.sysctrl.power_state soc_link=Null sysctrl_len=1520 system=system pio=system.apc.io_bus.master[5] [system.apc.sysctrl.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.timer0] type=Ucp2Timer children=power_state clk_domain=system.clk_domain cycles_trigger_timer=1 enable=false eventq_index=0 pio_addr=80904192 pio_latency=100000 power_model= power_state=system.apc.timer0.power_state soc_link=Null sysctrl=system.apc.sysctrl system=system timer_id=0 timer_size_bytes=32768 pio=system.apc.io_bus.master[2] [system.apc.timer0.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.apc.timer1] type=Ucp2Timer children=power_state clk_domain=system.clk_domain cycles_trigger_timer=1 enable=false eventq_index=0 pio_addr=80936960 pio_latency=100000 power_model= power_state=system.apc.timer1.power_state soc_link=Null sysctrl=system.apc.sysctrl system=system timer_id=1 timer_size_bytes=32768 pio=system.apc.io_bus.master[3] [system.apc.timer1.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.clk_domain] type=SrcClockDomain children=voltage_domain clock=1000 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.clk_domain.voltage_domain [system.clk_domain.voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.0 [system.dvfs_handler] type=DVFSHandler domains= enable=false eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000000 [system.membus] type=CoherentXBar children=power_state snoop_filter clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=true point_of_unification=true power_model= power_state=system.membus.power_state response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16 master=system.memdev.pio slave=system.system_port [system.membus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=1 max_capacity=8388608 system=system [system.memdev] type=IsaFake children=power_state clk_domain=system.clk_domain eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 pio_size=8 power_model= power_state=system.memdev.power_state ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.membus.master[0] [system.memdev.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=