81 lines
4.7 KiB
C
81 lines
4.7 KiB
C
/******************************************************************
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* @file ucp_mem_def.h
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* @brief: 两片UCP的内存分布头文件
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* @author: xuekun.zhang
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* @Date 2021年1月5日
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* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
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* Change_date Owner Change_content
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* 2021年1月5日 xuekun.zhang create file
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*****************************************************************/
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#ifndef UCP_MEM_DEF_H
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#define UCP_MEM_DEF_H
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//！命名宏定义时需要注意UCP使用的地址
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/*********************************UCP************************************************/
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#define SM0_BASE (0x09D00000)//1M
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#define SM1_BASE (0x09E00000)//1M
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#define SM2_BASE (0x09F00000)//1.5M
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#define SM3_BASE (0x0A080000)//1.5M
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#define SM4_BASE (0x0A200000)//1.5M
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#define SM5_BASE (0x0A380000)//1.5M
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//len define
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//SM0
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#define SM0_RECEIVER_CFG_LEN 0x00000400 //1K
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#define SM0_TRACE_LEN 0x00000400 //1K
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//SM1
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#define TIME_DATA_SLOT_LEN 0x0003c000 //61440*4byte = 240k
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//SM3
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#define SM3_NR_PUCCH_LUT_LEN 0x00040000 //256K
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#define SM3_PHY_MSG_BUFFER_LEN 0x00000400 //1K
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//DDR
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#define TRACE_GRP_LEN 0x00000200 //128Word
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/************************************SM0--1M*************************************************/
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#define RECEIVER_SYNC_CFG_BASE (SM0_BASE)
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#define RECEIVER_SYMB_CFG_BASE (RECEIVER_SYNC_CFG_BASE + 0x100)
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#define RECEIVER_BIT_CFG_BASE (RECEIVER_SYMB_CFG_BASE + 0x100)
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/************************************SM1---1M ***********************************************/
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#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (SM1_BASE)
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#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
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/************************************SM2--1.5M***********************************************/
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/************************************SM3--1.5M***********************************************/
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#define SM3_NR_PUCCH_LUT_ADDR (SM3_BASE)
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#define SM3_PHY_MSG_BUFFER_ADDR (SM3_NR_PUCCH_LUT_ADDR + SM3_NR_PUCCH_LUT_LEN)
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#define SM3_PHY_TASKS_MGR_ADDR (SM3_PHY_MSG_BUFFER_ADDR + SM3_PHY_MSG_BUFFER_LEN)
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/************************************SM4--1.5M***********************************************/
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//TODO:地址规划（暂时没用）
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#define RECEIVER_OUT1 (SM4_BASE)
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#define RECEIVER_OUT2 (SM4_BASE + 0x4000)
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#define RECEIVER_OUT3 (SM4_BASE + 0x8000)
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/************************************SM5--1.5M***********************************************/
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#define RECEIVER_BASE (SM5_BASE) //4k对齐
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/**************************************DDR***************************************************/
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#define DDR_PHY_BASE (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
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#define DDR_ERROR_RECORD_CNT_ADDR (0x79FF8000)
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#define DDR_STATE_RECORD_CNT_ADDR (0x79FFc000)
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//
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#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000) //!!!DDR_PHY_BASE 0x1E0000
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#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000) // 0x1E0000
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#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR (0x6BFC0000) // 0x1E0000 用于暂存数据供first_sync处理
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#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6C1A0000) // 0x1E0000 用于暂存数据供first_sync处理
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#define TRACE_RECEIVER_ADDR (0x88700000)
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#define TRACE_INIT_ADDR (TRACE_RECEIVER_ADDR) //0x88700000
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#define TRACE_SLOTIND_ADDR (TRACE_INIT_ADDR + TRACE_GRP_LEN) //0x88700200
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#define TRACE_RECEIVER_SYNC_ADDR (TRACE_SLOTIND_ADDR + TRACE_GRP_LEN) // 0x88700400
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#define TRACE_RECEIVER_SYMB_ADDR (TRACE_RECEIVER_SYNC_ADDR + TRACE_GRP_LEN)// 0x88700600
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#define TRACE_RECEIVER_BIT_ADDR (TRACE_RECEIVER_SYMB_ADDR + TRACE_GRP_LEN)// 0x88700800
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#define TRACE_TESTTASK_ADDR (TRACE_RECEIVER_BIT_ADDR + TRACE_GRP_LEN) // 0x88700a00
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#define TRACE_RECEIVER_SYNC_FIRST_ADDR (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700c00
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#define TRACE_RECEIVER_SYNC_FINE_ADDR (TRACE_RECEIVER_SYNC_FIRST_ADDR + TRACE_GRP_LEN) // 0x88700e00
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#endif
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