182 lines
10 KiB
C
182 lines
10 KiB
C
/******************************************************************
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* @file ucp_mem_def.h
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* @brief: 两片UCP的内存分布头文件
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* @author: xuekun.zhang
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* @Date 2021年1月5日
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* COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
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* Change_date Owner Change_content
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* 2021年1月5日 xuekun.zhang create file
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*****************************************************************/
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#ifndef UCP_MEM_DEF_H
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#define UCP_MEM_DEF_H
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#include "test_macro.h"
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//！命名宏定义时需要注意UCP使用的地址
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/*********************************UCP************************************************/
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#define SM0_BASE (0x09D00000)//1M
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#define SM1_BASE (0x09E00000)//1M
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#define SM2_BASE (0x09F00000)//1.5M
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#define SM3_BASE (0x0A080000)//1.5M
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#define SM4_BASE (0x0A200000)//1.5M
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#define SM5_BASE (0x0A380000)//1.5M
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//空间规划：
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/*
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SM0:（）
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SM1：(1M)用于recv_symb双核任务处理的数据临时存放空间
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SM5:（1201/1024KB）用于存放RECV_SYNC后给RECV_SYMB的数据
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SM2:（/1536KB）用于存放Transmitter的输出结果
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*/
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//len define
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//SM0
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//SM1
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#define TIME_DATA_SLOT_LEN (0x0003c000) //61440*4byte = 240k
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//SM2
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#define TRANSMITTER_OUT_LEN (0x0003c000) //TODO:确定实际长度
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//SM3
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#define SM3_NR_PUCCH_LUT_LEN (0x00040000) //256K
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#define SM3_PHY_MSG_BUFFER_LEN (0x00000400) //1K
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//SM5
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#define SM5_SYMB2_BIT_LEN (0x00038000)
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//DDR
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#define TRACE_GRP_LEN (0x00000200) //128Word
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/************************************SM0--1M*************************************************/
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#define RECEIVER_BIT_CFG_BASE (SM0_BASE)
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/************************************SM1---1M ***********************************************/
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#define RECEIVER_SYMB_OUT (SM1_BASE)
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#define RECEIVER_SYMB_OUT_ODD (RECEIVER_SYMB_OUT + 0x80000) //512KB each
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#ifdef CORE_ODD
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// CORE_ODD 的地址
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#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
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#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000)
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#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD + 0x3c000 + 0x8000)
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#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT_ODD)
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#else
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// 非CORE_ODD 的地址
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#define COMPENSATED_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
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#define CHANNELEST_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000)
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#define CHANNELEQU_DATA_DDR_PTR (RECEIVER_SYMB_OUT + 0x3c000 + 0x8000)
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#define TRANSFORMER_DATA_DDR_PTR (RECEIVER_SYMB_OUT)
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#endif
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/************************************SM2--1.5M***********************************************/
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#define TRANSMITTER_OUT (SM2_BASE) //4k对齐
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//#define TRANSMITTER_BEFORE_INTERP_EVEN (SM2_BASE+TIME_DATA_SLOT_LEN)
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//#define TRANSMITTER_BEFORE_INTERP_ODD (TRANSMITTER_BEFORE_INTERP_EVEN+TIME_DATA_SLOT_LEN)
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#define TRANSMITTER_BEFORE_INTERP_EVEN (0x70300000)
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#define TRANSMITTER_BEFORE_INTERP_ODD (0x70400000)
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/************************************SM3--1.5M***********************************************/
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#define SM3_PHY_MSG_BUFFER_ADDR (SM3_BASE)
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#define SM3_PHY_TASKS_MGR_ADDR (SM3_PHY_MSG_BUFFER_ADDR + SM3_PHY_MSG_BUFFER_LEN)
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#define RECEIVER_OUT3 (SM3_BASE + 0x4000)
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/************************************SM4--1.5M***********************************************/
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#define RECEIVER_BASE (0x71000000) //4k对齐
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#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
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#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
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#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)//0x0a278000
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#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)//0xa2b4000
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#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
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/*
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#define RECEIVER_BASE (SM4_BASE) //4k对齐
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#define RECEIVER_SYNC2SYMB_BUFFER0_ADDR (RECEIVER_BASE) //0x0a200000
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#define RECEIVER_SYNC2SYMB_BUFFER1_ADDR (RECEIVER_SYNC2SYMB_BUFFER0_ADDR + TIME_DATA_SLOT_LEN)//0x0a23c0000
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#define RECEIVER_SYNC2SYMB_BUFFER2_ADDR (RECEIVER_SYNC2SYMB_BUFFER1_ADDR + TIME_DATA_SLOT_LEN)//0x0a278000
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#define RECEIVER_SYNC2SYMB_BUFFER3_ADDR (RECEIVER_SYNC2SYMB_BUFFER2_ADDR + TIME_DATA_SLOT_LEN)//0xa2b4000
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#define RECEIVER_SYNC2SYMB_BUFFER4_ADDR (RECEIVER_SYNC2SYMB_BUFFER3_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER5_ADDR (RECEIVER_SYNC2SYMB_BUFFER4_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR (RECEIVER_SYNC2SYMB_BUFFER5_ADDR + TIME_DATA_SLOT_LEN)
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#define RECEIVER_SYNC2SYNC_FIRST_INF_ADDR (RECEIVER_SYNC2SYMB_BUFFER_REV_ADDR + TIME_DATA_SLOT_LEN) //LEN: sizeof(receiver_sync_status_t)
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*/
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/************************************SM5--1.5M***********************************************/
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#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (SM5_BASE)
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//#define RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR (RECEIVER_SYNC2SYNC_FIRST_INF_ADDR + 0x1000) //LEN: sizeof(receiver_sync_status_t)
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#ifdef CORE_ODD
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#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 0*SM5_SYMB2_BIT_LEN)
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#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 1*SM5_SYMB2_BIT_LEN)
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#else
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#define RECEIVER_SYMB2BIT_BUFFER0_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 2*SM5_SYMB2_BIT_LEN)
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#define RECEIVER_SYMB2BIT_BUFFER1_ADDR (RECEIVER_SYMB2BIT_BUFFER_BASE_ADDR + 3*SM5_SYMB2_BIT_LEN)
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#endif
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/**************************************DDR***************************************************/
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//1.93GB可用0x14400000-0x8FFFFFFF
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#define DDR_PHY_BASE (0x14400000)
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#define DDR_ERROR_RECORD_CNT_ADDR (0x79FF8000)
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#define DDR_STATE_RECORD_CNT_ADDR (0x79FFc000)
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//接收端数据来源选择
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//---------------TX RX JESD地址接口---------------------------------------------------------
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//#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (0x60F00000) //0x1E0000
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//#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (0x610E0000) //0x1E0000
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#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR (SM4_BASE) //0x1E0000
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#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR (SM4_BASE+0x78000) //0x1E0000
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#ifdef TX_RX_LOOP
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#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR)
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#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR)
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#else
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#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR (0x6BC00000)
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#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR (0x6BDE0000)
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#endif
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#define JESD_NRFDD_RX_SLOT_EVEN_DATA_DOWN_SAMP_ADDR (0x70000000) //!!!DDR_PHY_BASE 0x1E0000
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#define JESD_NRFDD_RX_SLOT_ODD_DATA_DOWN_SAMP_ADDR (0x70200000) // 0x1E0000
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#define JESD_NRFDD_RX_SLOT_SRC0_DATA_ADDR (0x6BFC0000) // 61440*4 用于暂存数据供first_sync处理
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#define JESD_NRFDD_RX_SLOT_SRC1_DATA_ADDR (0x6BFFC000) // 2048*4 用于暂存数据供first_sync处理
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//---------------APE4 RECV START FIRSTSYNC FLAG---------------------------------------------
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#define RECV_FIRST_SYNC_START_FLAG (0x82000000) //通过手动输入来开始接收端第一次同步 devmem 0x82000000 0xa5a55a5a 32
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//---------------APE7 PCIE TO APE4 sync_proc
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#define TRANSFORM_REF_PARA_PCIE2SYNC_ADDR (0x83000000)
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//---------------ARM Transmitter比特存放地址，大小SOURCE_DATA_BYTE_LENGTH*SOURCE_DATA_BUFFER_NUM = 313KB
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#define SOURCE_DATA_FLAG_DDR_ADDR (0x84000000) // SPU READ FLAG
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#define SOURCE_DATA_DDR_ADDR (0x84C00000)
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#define SOURCE_DATA_BUFFER_NUM (20)
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#define SOURCE_DATA_BYTE_LENGTH (16016)
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#define SOURCE_DATA_DDR_ADDR_END (SOURCE_DATA_DDR_ADDR + SOURCE_DATA_BUFFER_NUM*SOURCE_DATA_BYTE_LENGTH + 0x100)
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//--------------ARM RECV data存放地址，大小
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#define RECV_BIT_OUT_DATA_FLAG_DDR_ADDR (0x85000000) // SPU READ FLAG
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#define RECV_BIT_OUT_DATA_DDR_ADDR (0x85001000)
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#define RECV_BIT_OUT_DATA_BUFFER_NUM (8)
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#define RECV_BIT_OUT_DATA_BYTE_LENGTH (16016)
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#define RECV_BIT_OUT_DATA_DDR_ADDR_END (RECV_BIT_OUT_DATA_DDR_ADDR + RECV_BIT_OUT_DATA_BUFFER_NUM*RECV_BIT_OUT_DATA_BYTE_LENGTH + 0x100)
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//-----------------------------TRACE打点相关空间-----------------------------------------------------------------
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#define TRACE_RECEIVER_ADDR (0x88700000)
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#define TRACE_RECV_INIT_ADDR (TRACE_RECEIVER_ADDR) //0x88700000
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#define TRACE_SLOTIND_ADDR (TRACE_RECV_INIT_ADDR + TRACE_GRP_LEN) //0x88700200
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#define TRACE_RECEIVER_SYNC_ADDR (TRACE_SLOTIND_ADDR + TRACE_GRP_LEN) // 0x88700400
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#ifdef CORE_ODD
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#define TRACE_RECEIVER_SYMB_ADDR (TRACE_RECEIVER_SYNC_ADDR + TRACE_GRP_LEN)// 0x88700600
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#else
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#define TRACE_RECEIVER_SYMB_ADDR (TRACE_RECEIVER_SYNC_ADDR + 2*TRACE_GRP_LEN)// 0x88700800
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#endif
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#define TRACE_RECEIVER_BIT_ADDR (TRACE_RECEIVER_SYNC_ADDR + 3*TRACE_GRP_LEN)// 0x88700a00
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#define TRACE_TESTTASK_ADDR (TRACE_RECEIVER_BIT_ADDR + TRACE_GRP_LEN) // 0x88700c00
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#define TRACE_RECEIVER_SYNC_FIRST_ADDR (TRACE_TESTTASK_ADDR + TRACE_GRP_LEN) // 0x88700e00
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#define TRACE_RECEIVER_SYNC_FINE_ADDR (TRACE_RECEIVER_SYNC_FIRST_ADDR + TRACE_GRP_LEN) // 0x88701000
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#define TRACE_PCIE_ADDR (TRACE_RECEIVER_SYNC_FINE_ADDR + TRACE_GRP_LEN) //0x88701200
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#define TRACE_TRANSMITTER_ADDR (TRACE_PCIE_ADDR + TRACE_GRP_LEN) // 0x88701400
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#define TRACE_TRANS_INIT_ADDR (TRACE_TRANSMITTER_ADDR + TRACE_GRP_LEN) // 0x88701600
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#define TRACE_RECEIVER_SYNC_INIT_ADDR (TRACE_TRANS_INIT_ADDR + TRACE_GRP_LEN) // 0x88701800
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#endif
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