/dts-v1/;

#include <dt-bindings/clock/ucp4008.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/ucp4008.h>
#include <dt-bindings/memory/ucp4008-mc.h>
#include <dt-bindings/iio/frequency/ad9528.h>

/ {
	compatible = "smartlogic,ucp2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &serial_0;
		serial1 = &serial_1;
		serial2 = &serial_2;
		serial3 = &serial_3;
	};
        chosen {
                stdout-path = &serial_0;
        };

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		//dma-ranges = <0xe0000000 0 0 0x10000000>;
		//ranges = <0 0xe0000000 0 0x10000000>;
		apb-pclk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "apb-pclk";
		};

		gic: interrupt-controller@02181000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x01800000 0x10000>,	/* GICD */
				<0x01900000 0x00F60000>,	/* GICR */
				<0x04200000 0x00010000>,	/* GICC */
				<0x01820000 0x00010000>,	/* GICH */
				<0x01830000 0x00010000>;	/* GICV */
			interrupt-parent = <&gic>;
		};

		serial_0: serial@04440000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x04440000 0x8000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "baudclk";
			clocks = <&clock_reset UART0_SCLK>;	
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "okay";		
		};
		serial_1: serial@04448000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x04448000 0x8000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "baudclk";
			clocks = <&clock_reset UART1_SCLK>;	
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";		
		};		
		serial_2: serial@04d00000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x04d00000 0x8000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "baudclk";
			clocks = <&clock_reset UART2_SCLK>;	
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "okay";
		};
		serial_3: serial@04d08000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x04d08000 0x8000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "baudclk";
			clocks = <&clock_reset UART3_SCLK>;	
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};
		stc: stc-controller@08568000 {
			compatible = "smartlogic,stc";
			reg = <0x08568000 0x8000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
			status = "okay";
		};		
		timer {
			compatible = "arm,armv8-timer";
			interrupts =<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
						<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
						<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
						<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
//			clock-frequency = <50000000>;  /* 50M */
		};
        
//        pet:pet@{
//            compatible = "smartlogic,pet";
//            reg = <0x091d0000 0x10000>,
//                  <0x091f0000 0x10000>;
//
//        };

		smmu: mmu@042b8000 {
			compatible = "arm,mmu-500";
			reg = <0x042b8000 0x20000>;
			#global-interrupts = <1>;
			#iommu-cells = <1>;
			interrupts = <GIC_PPI 147 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
					<GIC_PPI 148 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		clock_reset: clock-controller@04550000  {
			compatible = "smartlogic,ucp2-clock";
			reg = <0x04550000  0x10000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pcie: pcie@091e0000 {
			compatible = "smartlogic,pcie-ucp4008evb";
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "sys", "perst";
			reg = <0x091e0000  0x10000>,		/* pcie-app */		  
				<0x0c000000  0x500000>,		/* pcie-dbi */
				<0x04550000  0x1000>,		/* pcie-crg */
				<0x04560000  0x1000>,		/* pcie-syscfg */
				<0x091d0000  0x1000>,		/* pet-ctrl */
				<0x091f0000  0x1000>,		/* pet-crg */
				<0x09204000  0x100000>;		/* pet-pma3 */
			reg-names =  "pcie-app", "pcie-dbi", "pcie-crg", "pcie-syscfg", "pet-ctrl", "pet-crg", "pet-pma3";
			ep-id = <0>;
			status = "disabled";
		};

	pvt: pvt@4708000 {
        compatible = "ucp4008pvt";
        reg = <0x4708000 0x1000>;
        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
        status = "okay";
		
        tsa_hytrs = <0>;
        tsa_alarm = <100000>;
        
        tsb_hytrs = <0>;
        tsb_alarm = <95000>;

    	vma_hytrs = <700>;
        vma_alarm = <850>;

        vmb_hytrs = <690>;
        vmb_alarm = <870>;
    };

	i2c_0: i2c@04420000{    /* AT24CM01 */
		#address-cells = <1>;
		#size-cells = <0>;			
		compatible = "snps,designware-i2c";
		reg = <0x04420000 0x8000>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;				
		clock-frequency = <400000>;
		clocks = <&clock_reset I2C0_CLK>;
		status = "okay";		
        eeprom@50 {
                compatible = "atmel,24c1024";
                reg = <0x50>;
        };		
	};
		
	i2c_1: i2c@04428000{   /* i2c switch */
		#address-cells = <1>;
		#size-cells = <0>;			
		compatible = "snps,designware-i2c";
		reg = <0x04428000 0x8000>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;				
		clock-frequency = <100000>;   //400000
		clocks = <&clock_reset I2C1_CLK>;
		status = "okay";
		
		i2c-switch@70 {
			compatible = "nxp,pca9548";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x70>;
			
			sfp0_i2c: i2c@3 {   	/* TMAC SFP */
			    #address-cells = <1>;
			    #size-cells = <0>;
			   	reg = <0x3>;
			};
			
			i2c@4 {
				#address-cells = <1>;
      			#size-cells = <0>;				
            	reg = <0x4>;
					
				sensor@49 {
				  compatible = "ti,tmp468";
				  reg = <0x49>;
	  			  #address-cells = <1>;
	  			  #size-cells = <0>;
				
				  channel@0 {
					reg = <0x0>;
					label = "local";
				  };				
				  channel@1 {
					reg = <0x1>;
					label = "external-ch1";
				  };				
				  channel@2 {
					reg = <0x2>;
					label = "external-ch2";
				  };
				  channel@3 {
					reg = <0x3>;
					label = "external-ch3";
				  };
				channel@4 {
				  reg = <0x4>;
				  label = "external-ch4";
				};				
				channel@5 {
				  reg = <0x5>;
				  label = "external-ch5";
				};				
				channel@6 {
				  reg = <0x6>;
				  label = "external-ch6";
				};
				channel@7 {
				  reg = <0x7>;
				  label = "external-ch7";
				};				
				channel@8 {
				  reg = <0x8>;
				  label = "external-ch8";
				};				  
				};
			};

			i2c@5 {
				#address-cells = <1>;
			    #size-cells = <0>;
			   	reg = <0x5>;
				ltm4677@40{
                	compatible = "lltc,ltm4677";
					reg = <0x40>;
				};				
				ltm4677@42{
                	compatible = "lltc,ltm4677";
					reg = <0x42>;
				};
			};

			i2c@6 {
				#address-cells = <1>;
			    #size-cells = <0>;
				reg = <0x6>;
				ltm4675@42{
                	compatible = "lltc,ltm4675";
                	reg = <0x42>;
				};								
			};			
									
		};

	};

        sfp0: sfp-0 {
                compatible = "sff,sfp";
                i2c-bus = <&sfp0_i2c>;
                maximum-power-milliwatt = <2000>;
        };
		
		pinctrl: pinctrl@04458000 {
			compatible = "ucp2,pinctrl";
			
			leds_gpio: leds_gpio {
				ucp2,pins = <PD5>;     /* GPIO0B18 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT0>;
			};
			phy0_reset_gpio:phy0_reset_gpio{
				ucp2,pins = <LVDS_RF_D00_P>;   /* GPIO1B5 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			phy1_reset_gpio:phy1_reset_gpio{
				ucp2,pins = <LVDS_RF_D00_N>;   /* GPIO1B4 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			usb_reset_gpio:usb_reset_gpio{
				ucp2,pins = <LVDS_RF_D01_P>;	/* GPIO1B7 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			i2c_mux_reset_gpio:i2c_mux_reset_gpio{
				ucp2,pins = <LVDS_RF_D01_N>;	/* GPIO1B6 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			reset_8A34002_gpio:reset_8A34002_gpio{
				ucp2,pins = <LVDS_RF_D02_N>;	/* GPIO1B8 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			pcie_reset_gpio:pcie_reset_gpio{
				ucp2,pins = <LVDS_RF_D04_P>;	/* input ??? GPIO0B13  */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			gps_reset_gpio:gps_reset_gpio{
				ucp2,pins = <LVDS_RF_DATACK_P>;	/* GPIO1-B29 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			
			qspi0_cs_gpio:qspi0_cs_gpio{
				ucp2,pins = <PD10>;         /* GPIO0-B23 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};	
			qspi0_gpios:qspi0_gpios{
				ucp2,pins = <PD11 PD12 PD13 PD14 PD15>;
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT1>;
			};
			
			spi1_gpios:spi1_gpios{
				ucp2,pins = <PA7  PA8  PA9>;
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT0>;
			};			
			spi2_gpios:spi2_gpios{
				ucp2,pins = <PA12  PA13  PA14>;
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT1>;
			};		
			spi2_cs_8A34002:spi2_cs_8A34002{   
				ucp2,pins = <PA11>;            /* GPIO0A11 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};

			// by daya 1
			AD9026_reset_gpio:AD9026_reset_gpio{
				ucp2,pins = <LVDS_RF_D02_P>;	/* GPIO1B9 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_tx1_gpio:AD9026_tx1_gpio{
				ucp2,pins = <LVDS_RF_D04_P>;	/* GPIO1B13 */      
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_tx2_gpio:AD9026_tx2_gpio{
				ucp2,pins = <LVDS_RF_D04_N>;	/* GPIO1B12 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_tx3_gpio:AD9026_tx3_gpio{
				ucp2,pins = <LVDS_RF_D05_P>;	/* GPIO1B15 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_tx4_gpio:AD9026_tx4_gpio{
				ucp2,pins = <LVDS_RF_D05_N>;	/* GPIO1B14 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_rx1_gpio:AD9026_rx1_gpio{
				ucp2,pins = <LVDS_RF_D10_P>;	/* GPIO1B17 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_rx2_gpio:AD9026_rx2_gpio{
				ucp2,pins = <LVDS_RF_D10_N>;	/* GPIO1B16 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_rx3_gpio:AD9026_rx3_gpio{
				ucp2,pins = <LVDS_RF_D11_P>;	/* GPIO1B19 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9026_rx4_gpio:AD9026_rx4_gpio{
				ucp2,pins = <LVDS_RF_D11_N>;	/* GPIO1B18 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9528_reset_gpio:AD9528_reset_gpio{
				ucp2,pins = <LVDS_RF_D03_P>;	/* GPIO1B11 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9528_sysrefRequest_gpio:AD9528_sysrefRequest_gpio{
				ucp2,pins = <LVDS_RF_D03_N>;	/* GPIO1B10 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9528_status0_gpio:AD9528_status0_gpio{
				ucp2,pins = <LVDS_RF_D15_P>;	/* GPIO1B27 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			AD9528_status1_gpio:AD9528_status1_gpio{
				ucp2,pins = <LVDS_RF_D15_N>;	/* GPIO1B26 */ 
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};
			spi1_cs_AD9026:spi1_cs_AD9026{   
				ucp2,pins = <PA6>;            /* GPIO0A6 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT3>;
			};		
			spi1_cs_AD9528:spi1_cs_AD9528{   
				ucp2,pins = <PD6>;            /* GPIO0B19 */
				ucp2,pull = <UCP2_PUD_UP>;
				ucp2,function = <UCP2_FSEL_ALT0>;
			};			
			// end 1				

		};				

		gpio0: gpio@04450000 { 
			compatible = "snps,dw-apb-gpio";
			reg = <0x04450000 0x8000>;
			#address-cells = <1>;
			#size-cells = <0>;
			port0a: gpio@0 { 
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
//				interrupt-controller;
//				interrupt-parent = <&gic>;
//				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 
			};
			port0b: gpio@1 { 
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <1>; 
			}; 
		}; 

		gpio1: gpio@04D10000 { 
			compatible = "snps,dw-apb-gpio";
			reg = <0x04D10000 0x8000>;
			#address-cells = <1>;
			#size-cells = <0>;
			port1a: gpio@0 { 
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <15>;  /* GPIO1A0-GPIO1A14 */
				reg = <0>;
//				interrupt-controller;
//				interrupt-parent = <&gic>;
//				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 
			};
			port1b: gpio@1 { 
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>; /* GPIO1B0-GPIO1B31 */
				reg = <1>; 
			}; 

			/* GPIO1A17-GPIO1A31 only used in LVDS mode disable */
		};
			
		leds {
			compatible = "gpio-leds";
			pinctrl-names = "default";
			pinctrl-0 = <&leds_gpio>;
			status = "okay";
			heartbeat {
				label = "Heartbeat";
				gpios = <&port0b 18 GPIO_ACTIVE_LOW>;  /* GPIO0B18 */
				linux,default-trigger = "heartbeat";
			};
		};

		usbphy_reset {
			compatible = "smartlogic,usbphy_reset";				
			pinctrl-names = "default";				
			pinctrl-0 = <&usb_reset_gpio>; 			
			status = "okay";						
			pin = <&port1b 7 GPIO_ACTIVE_LOW>;  /* GPIO1B7 */				
		};
		i2c_reset {
			compatible = "smartlogic,i2c_reset";				
			pinctrl-names = "default";				
			pinctrl-0 = <&i2c_mux_reset_gpio>; 			
			status = "okay";						
			pin = <&port1b 6 GPIO_ACTIVE_LOW>;  /* GPIO1B6 */				
		};
		ad9026_reset {
			compatible = "smartlogic,ad9026_reset";				
			pinctrl-names = "default";				
			pinctrl-0 = <&AD9026_reset_gpio>; 			
			status = "okay";						
			pin = <&port1b 9 GPIO_ACTIVE_LOW>;  /* GPIO1B9 */				
		};
		reset_8A34002 {
			compatible = "smartlogic,reset_8A34002";				
			pinctrl-names = "default";				
			pinctrl-0 = <&reset_8A34002_gpio>; 			
			status = "okay";						
			pin = <&port1b 8 GPIO_ACTIVE_LOW>;  /* GPIO1B8 */				
		};
		ad9528_reset {
			compatible = "smartlogic,AD9528_reset";				
			pinctrl-names = "default";				
			pinctrl-0 = <&AD9528_reset_gpio>; 			
			status = "okay";						
			pin = <&port1b 11 GPIO_ACTIVE_LOW>;  /* GPIO1B11 */				
		};

		ethernet0: ethernet0@01a40000 {
			compatible = "smartlogic,dwmac-5.10a";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "tx", "ptp_ref";
			clocks = <&clock_reset GMAC0_TX_CLK>,
				<&clock_reset GMAC0_PTP_REF_CLK>;
			reg = <0x01a40000 0x4000>;
			phy-handle = <&ethphy0>;
			phy-mode = "rgmii";
			ethernet= <0>;
			snps,en-tx-lpi-clockgating;
			snps,en-lpi;
			snps,write-requests = <4>;
			snps,read-requests = <4>;
			snps,burst-map = <0x4>;
			snps,txpbl = <16>;
			snps,rxpbl = <16>;
			snps,aal;
			snps,tso;
			sph_disable;
			smartlogic,mac-delay = <0x0303>;
			status = "okay";

			mdio0: mdio0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				compatible = "snps,dwmac-mdio";
			};
		};

		ethernet1: ethernet1@01a50000 {
			compatible = "smartlogic,dwmac-5.10a";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "tx", "ptp_ref";
			clocks = <&clock_reset GMAC1_TX_CLK>,
				<&clock_reset GMAC1_PTP_REF_CLK>;
			reg = <0x01a50000 0x4000>;
			phy-handle = <&ethphy1>;
			phy-mode = "rgmii";
			ethernet= <1>;
			snps,en-tx-lpi-clockgating;
			snps,en-lpi;
			snps,write-requests = <4>;
			snps,read-requests = <4>;
			snps,burst-map = <0x4>;
			snps,txpbl = <16>;
			snps,rxpbl = <16>;
			snps,aal;
			snps,tso;
			sph_disable;
			smartlogic,mac-delay = <0x0303>;
			status = "okay";

			/*fixed-link {
				speed = <1000>;
				full-duplex;
			};*/

			mdio1: mdio1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				compatible = "snps,dwmac-mdio";
			};
		};

		ethernet2: ethernet2@08524000 {
			compatible = "smartlogic,dwmac-5.10a";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 568 IRQ_TYPE_LEVEL_HIGH>;
//			clock-names = "tx";
//			clocks = <&clock_reset GMAC2_TX_CLK>;
			reg = <0x08524000 0x1FFFF>;
//			phy-handle = <&ethphy0>;
			phy-mode = "gmii";
			ethernet= <2>;
			snps,en-tx-lpi-clockgating;
			snps,en-lpi;
			snps,write-requests = <4>;
			snps,read-requests = <4>;
			snps,burst-map = <0x4>;
			snps,txpbl = <16>;
			snps,rxpbl = <16>;
			snps,aal;
			snps,tso;
			sph_disable;
			smartlogic,mac-delay = <0x0101>;
			status = "okay";

			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};

		ethernet3: ethernet3@09090000 {
			compatible = "smartlogic,dwxgmac";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "tx", "ptp_ref";
			clocks = <&clock_reset TMAC_PTP_REF_CLK>,
				<&clock_reset TMAC_PTP_REF_CLK>;
			reg = <0x09090000 0x100000>;
//			phy-handle = <&ethphy0>;
			phy-mode = "xlgmii";
			sfp = <&sfp0>;
			ethernet= <3>;
			snps,en-tx-lpi-clockgating;
			snps,en-lpi;
			snps,write-requests = <4>;
			snps,read-requests = <4>;
			snps,burst-map = <0x4>;
			snps,txpbl = <16>;
			snps,rxpbl = <16>;
			max-frame-size = <16368>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			snps,axi-config = <&stmmac_axi_setup>;
			snps,mtl-rx-config = <&mtl_rx_setup>;
			snps,mtl-tx-config = <&mtl_tx_setup>;
			rx-fifo-depth = <16384>;
			tx-fifo-depth = <16384>;
			snps,aal;
			snps,tso;
			sph_disable;
//			smartlogic,mac-delay = <0x0101>;
			//max-speed = <10000>;
			sfp-max-speed = <10000>;
			managed = "in-band-status";
			status = "okay";
			/*fixed-link {
				speed = <10000>;
				full-duplex;
			};*/
			
		};

		stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <0xf>;
			snps,rd_osr_lmt = <0xf>;
			snps,blen = <256 128 64 32 0 0 0>;
		};

		mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <1>;
			snps,rx-sched-sp;
			queue0 {
				snps,dcb-algorithm;
				snps,map-to-dma-channel = <0x0>;
				snps,priority = <0x0>;
			};
		};

		mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <1>;
			snps,tx-sched-wrr;
			queue0 {
				snps,weight = <0x10>;
				snps,dcb-algorithm;
				snps,priority = <0x0>;
			};
			/*queue1 {
				snps,avb-algorithm;
				snps,send_slope = <0x1000>;
				snps,idle_slope = <0x1000>;
				snps,high_credit = <0x3E800>;
				snps,low_credit = <0xFFC18000>;
				snps,priority = <0x1>;
			};*/
		};

//		sysctrl: sysctrl@04560000 {
//			compatible = "smartlogic,ucp4008-sysctrl";
//			reg = <0x04560000 0x10000>;
//			#reset-cells = <1>;
//		};

		usb: usb@045c0000 {
			compatible = "smartlogic,ucp4008-usb", "snps,dwc2";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x045c0000 0x40000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			
			pinctrl-names = "default";				
			pinctrl-0 = <&usb_reset_gpio>; 	
			reset-gpios = <&port1b 7 GPIO_ACTIVE_HIGH>; 

			dr_mode = "host";
			//dr_mode = "peripheral";
			//dr_mode = "otg";

			status = "disable";
		};

      mmcsd: mmcsd@01a60000 {
		compatible = "snps,dw-mshc";
		reg = <0x01a60000 0x1000>;
		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock_reset CIU_CCLK>,<&clock_reset CIU_CCLK_DIV>,<&clock_reset SDIO_TUNING_CLK_DIV>;
		clock-names = "biu","ciu","ciu_div1";			
		fifo-depth = <512>;
		card-detect-delay = <200>;
		bus-width = <8>;	
		max-frequency   = <40000000>;   /* 40M */
		clock-frequency = <62500000>;   /* 62.5M */
		smartlogic,clock-frequency-div1 = <250000000>; /* 250M */
		status = "okay";
		cap-mmc-highspeed;
		cap-sd-highspeed;
		non-removable;		
	};

	eip0: eip@01060000 {
		#adress-cells = <1>;
		#size-cells = <1>;
		compatible = "smartlogic, eip-197";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x01060000 0x200000>;
	};

	eip1: eip@01260000 {
		#adress-cells = <1>;
		#size-cells = <1>;
		compatible = "smartlogic, eip-197-pdcp";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 
                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x01260000 0x200000>;
	};

	com_module{
		compatible = "smartlogic,com";
		status = "okay";
		//reg = <0x30000000 0x1fb0>;	
		//mem_block_size = <4096>;
		com_header_addr = <0x931fc00>;
	};

	qspi_0: spi@04430000 {			 /* spi0 MT25QU02G */
		compatible = "snps,dw-apb-ssi";
		reg = <0x04430000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock_reset SSI0_CLK>;
		pinctrl-names = "default";
		pinctrl-0 = <&qspi0_cs_gpio &qspi0_gpios>;
//		resets = <&clock_reset SSI1_DEV_SWRSTREQ>;
		reset-names = "spi0";
		bus-num = <0x0>; 
		reg-io-width = <4>;
		num-cs = <1>;
		cs-gpios = <&port0b 23 GPIO_ACTIVE_HIGH>;
		reg-shift = <2>;					
	    status = "okay";
	};

	// by daya 2
	spi_1: spi@04438000 {            /* spi1 ADRV9026 AD9528 */
		compatible = "snps,dw-apb-ssi";
		reg = <0x04438000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock_reset SSI1_CLK>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_cs_AD9026>,<&AD9026_reset_gpio>,<&spi1_cs_AD9528>,<&AD9528_reset_gpio>,<&AD9528_sysrefRequest_gpio>,
					<&AD9026_tx1_gpio>,<&AD9026_tx2_gpio>,<&AD9026_tx3_gpio>,<&AD9026_tx4_gpio>,
					<&AD9026_rx1_gpio>,<&AD9026_rx2_gpio>,<&AD9026_rx3_gpio>,<&AD9026_rx4_gpio>,
					<&leds_gpio>,<&AD9528_status0_gpio>,<&AD9528_status1_gpio>; 
//		resets = <&clock_reset SSI1_DEV_SWRSTREQ>;
		reset-names = "spi1";
		bus-num = <1>;
		reg-io-width = <4>;
		// daya num-cs = <2>;
		// daya cs-gpios = <&port0a 6 GPIO_ACTIVE_HIGH>, <&port0b 19 GPIO_ACTIVE_HIGH>;
		reg-shift = <2>;					
		status =  "okay";
	};

	spi2: spi@04d18000 {                     /* spi2 8A34002 */
//		compatible = "snps,dwc-ssi-1.01a";
		compatible = "snps,dw-apb-ssi";
		reg = <0x04d18000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
//		clocks = <&clock_reset SSI2_CLK>,
//		         <&clock_reset SSI2_CLK_DIV>;
 		clocks = <&clock_reset SSI2_CLK>;
		clock-names = "ssi_clk","pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&spi2_cs_8A34002>,<&spi2_gpios>; 	
		//resets = <&clock_reset SSI2_DEV_SWRSTREQ>;
		reset-names = "spi";
		bus-num = <0x2>;
		/* Could possibly go up to 200 MHz */
		spi-max-frequency = <100000000>;   /* 100M */ 
		num-cs = <1>;
		cs-gpios = <&port0a 11 GPIO_ACTIVE_HIGH>;
		reg-io-width = <4>;
		status = "okay";
	};

//          dma_test {
//               compatible = "smartlogic,dma_test";
//               status = "okay";
//               iommus = <&smmu>;
//               dma-ranges;
//               memory-region = <&cdsp_fw_mem1>;
//          };

//         smmu_test {
//               compatible = "smartlogic,smmu_test";
//               status = "okay";
//               iommus = <&smmu UCP4008_SID_SMMU_TEST>;
//          };
		timer00: timer@04418000 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004418000 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;					
			clocks = <&clock_reset TIMER00_CLK>;
			clock-names = "timer";
										
//			resets = <&clock_reset TIMER00_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer01: timer@04418014 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004418014 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;			
			
			clocks = <&clock_reset TIMER01_CLK>;
			clock-names = "timer";	

//			resets = <&clock_reset TIMER01_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer02: timer@04418028 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04418028 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER02_CLK>;
			clock-names = "timer";	
//			resets = <&clock_reset TIMER02_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer03: timer@0441803c {
			compatible = "snps,dw-apb-timer";
			reg = <0x0441803c 0x14>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER03_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER03_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer04: timer@04418050 {
			compatible = "snps,dw-apb-timer";
			reg = <0x0441805 0x14>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER04_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER04_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer05: timer@04418064 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04418064 0x14>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER05_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER05_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer06: timer@04418078 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04418078 0x14>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER06_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER06_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer07: timer@0441808c {
			compatible = "snps,dw-apb-timer";
			reg = <0x0441808c 0x14>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER07_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER07_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer10: timer@04D28000 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004D28000 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;					
			clocks = <&clock_reset TIMER10_CLK>;
			clock-names = "timer";
										
//			resets = <&clock_reset TIMER10_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer11: timer@04D28014 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004D28014 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;			
			
			clocks = <&clock_reset TIMER11_CLK>;
			clock-names = "timer";	

//			resets = <&clock_reset TIMER11_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer12: timer@04D28028 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D28028 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER12_CLK>;
			clock-names = "timer";	
//			resets = <&clock_reset TIMER12_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer13: timer@04D2803c {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D2803c 0x14>;
			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER13_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER13_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer14: timer@04D28050 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D2805 0x14>;
			interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER14_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER14_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer15: timer@04D28064 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D28064 0x14>;
			interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER15_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER15_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer16: timer@04D28078 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D28078 0x14>;
			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER16_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER16_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer17: timer@04D2808c {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D2808c 0x14>;
			interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER17_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER17_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};		

		timer20: timer@04D38000 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004D38000 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;					
			clocks = <&clock_reset TIMER20_CLK>;
			clock-names = "timer";
										
//			resets = <&clock_reset TIMER20_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer21: timer@04D38014 {
			compatible = "snps,dw-apb-timer";
			reg = <0x004D38014 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;			
			
			clocks = <&clock_reset TIMER21_CLK>;
			clock-names = "timer";	

//			resets = <&clock_reset TIMER21_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer22: timer@04D38028 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D38028 0x14>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER22_CLK>;
			clock-names = "timer";	
//			resets = <&clock_reset TIMER22_DEV_SWRSTREQ>;
//			reset-names = "timer";					
			status = "okay";
		};
		timer23: timer@04D3803c {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D3803c 0x14>;
			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER23_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER23_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer24: timer@04D38050 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D3805 0x14>;
			interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
					
			clocks = <&clock_reset TIMER24_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER24_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

		timer25: timer@04D38064 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D38064 0x14>;
			interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER25_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER25_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer26: timer@04D38078 {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D38078 0x14>;
			interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER26_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER26_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};
		timer27: timer@04D3808c {
			compatible = "snps,dw-apb-timer";
			reg = <0x04D3808c 0x14>;
			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock_reset TIMER27_CLK>;
			clock-names = "timer";
//			resets = <&clock_reset TIMER27_DEV_SWRSTREQ>;
//			reset-names = "timer";						
			status = "okay";
		};

        test_dma: test {
		    compatible = "smartlogic,dma_test";
		    status = "okay";
	    };

		dmac: dma-controller@04540000 { 
			#dma-cells = <1>;
			compatible = "snps,axi-dma-1.01a";
			reg = <0x04540000 0x400>;
            clocks = <&clock_reset DMAS0_CORE_CLK_DIV>, <&clock_reset DMAS0_CORE_CLK>;
			clock-names = "core-clk", "cfgr-clk";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <8>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,block-size = <512 512 512 512 512 512 512 512>;
			snps,priority = <0 1 2 3 4 5 6 7>;
			snps,axi-max-burst-len = <8>;					
		};
		dmas1: dma-controller@04d38000 { 
			#dma-cells = <1>;
			compatible = "snps,axi-dma-1.01a";
			reg = <0x04d38000 0x400>;
			/*clocks = <&core_clk>, <&cfgr_clk>;
			clock-names = "core-clk", "cfgr-clk"; */
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <8>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,block-size = <512 512 512 512 512 512 512 512>;
			snps,priority = <0 1 2 3 4 5 6 7>;
			snps,axi-max-burst-len = <8>;
//			resets = <&clock_reset DMAS1_DEV_SWRSTREQ>;
//			reset-names = "DMAS1";							
		};	

		wdt: watchdog@04400000 {
			compatible = "snps,dw-wdt";
			reg = <0x04400000  0x100>;
            clock-names = "tclk"; 
			clocks = <&clock_reset MAIN_PCLK_DIV>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;	
			status = "okay";
		};
		
		wdt1: watchdog@04408000 {
			compatible = "snps,dw-wdt";
			reg = <0x04408000  0x100>;
			clock-names = "tclk"; 
			clocks = <&clock_reset MAIN_PCLK_DIV>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			status = "okay";
		};	
			
        rtc: rtc@04410000 {
            compatible = "apm,xgene-rtc";
            reg = <0x04410000 0x8000>;
            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
            #clock-cells = <1>;
			clocks = <&clock_reset RTC_CLK>;
        };		
	};
};

&qspi_0 {
	#address-cells = <1>;
	#size-cells = <0>;

	flash0: n25q00@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;	/* chip select */
		spi-tx-bus-width= <0x1>;
		spi-rx-bus-width= <0x1>;
	//	spi-max-frequency = <100000000>;
		spi-max-frequency = <40000000>;
		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
		status = "okay";

		partition@qspi-boot {
			/* 8MB for raw data. */
			label = "Flash 0 Raw Data";
			reg = <0x0 0x800000>;
		};

		partition@qspi-rootfs {
			/* 120MB for jffs2 data. */
			label = "Flash 0 jffs2 Filesystem";
			reg = <0x800000 0x7800000>;
		};
	};
};

// by daya 3
&spi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	
	spidev0: spidev@0 { 
    		compatible = "rohm,dh2228fv";
    		spi-max-frequency = <8000000>;
      		reg = <0>;  
			bus-width = <4>;
			device-width = <1>;
	};
};

&spi2 {
       #address-cells = <1>;
       #size-cells = <0>;

       phc@0 { /* Clock Matrix */
               compatible = "idt,8a34000";
               spi-max-frequency = <1000000>;
               reg = <0>;
       };	
};

&mdio0 {
		ethphy0: ethernet-phy@0 {
//		compatible = "ethernet-phy-ieee802.3-c22";
		compatible = "marvell,88E1510";
		reg = <1>;
		device_type = "ethernet-phy";
//		marvell,reg-init = <0x12 0x14 0 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <&phy0_reset_gpio>;
		reset-assert-us = <10000>;
		reset-deassert-us = <50000>;
		reset-gpios = <&port1b 5 GPIO_ACTIVE_LOW>;	 /* GPIO1B5 */
	};
};

&mdio1 {
		status = "okay";
		ethphy1: ethernet-phy@1 {
//		compatible = "ethernet-phy-ieee802.3-c22";
		compatible = "marvell,88E1510";
		reg = <1>;
		device_type = "ethernet-phy";
//		marvell,reg-init = <0x12 0x14 0 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <&phy1_reset_gpio>;
		reset-assert-us = <10000>;
		reset-deassert-us = <50000>;
		reset-gpios = <&port1b 4 GPIO_ACTIVE_LOW>;  /* GPIO1B4 */
	};
};

/{
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};

			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};

		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x00 0x00>;
			next-level-cache = <&cluster0_l2>;
			numa-node-id = <0>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x1>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster0_l2>;
			numa-node-id = <0>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x2>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster0_l2>;
			numa-node-id = <0>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x3>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster0_l2>;
			numa-node-id = <0>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x100>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster1_l2>;
			numa-node-id = <1>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x101>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
            cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster1_l2>;
			numa-node-id = <1>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x102>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster1_l2>;
			numa-node-id = <1>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x103>;
			enable-method = "spin-table";
//			cpu-release-addr = <0x00 0x0a200000>;
			cpu-release-addr = <0x00 0x045602c0>;
			next-level-cache = <&cluster1_l2>;
			numa-node-id = <1>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&clock_reset A72CORE_SRCCLK_0>;

		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
		};
	};
};

/   {
cpu0_opp_table: opp_table0 {
        compatible = "operating-points-v2";
        opp-shared;


        opp-1500000000 {
                opp-hz = /bits/ 64 <1500000000>;
                clock-latency-ns = <40000>;
                opp-suspend;
        };

        opp-1600000000 {
                opp-hz = /bits/ 64 <1600000000>;
                clock-latency-ns = <40000>;
                opp-suspend;
        };

        opp-1800000000 {
                opp-hz = /bits/ 64 <1800000000>;
                clock-latency-ns = <40000>;
                opp-suspend;
        };
	};	
};


/ {
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		
		reserved: test@10000000 {
			no-map;
			reg = <0 0x10000000 0x0 0xA8000000>;		
		};
		
		/*reserved2: test2@10000000 {
			no-map;
			reg = <0x1 0x00000000 0x1 0x00000000>;		
		};*/		
		
        cdsp_fw_mem: memory@0xb0000000 {
	    compatible = "shared-dma-pool";
            reg = <0x0 0xF0000000 0 0x0C000000>;  /*CMA (128+64)M*/
            reusable;
            linux,cma-default;
        };		

	
	};
};


/ {

	fixed-rate-clocks {
		xtal0 {
			compatible = "smartlogic,clock-xtal0";
			clock-frequency = <20000000>;  /* 20M */
//		clock-frequency = <1000000000>;  /* 1000M */

		};
		xtal1 {
			compatible = "smartlogic,clock-xtal1";
			clock-frequency = <20000000>;
		};		

		sfp_eth_clk {
			compatible = "smartlogic,sfp_eth_clk";
			clock-frequency = <125000000>;
		};
		pet_eth_ref_clk {
			compatible = "smartlogic,pet_eth_ref_clk";
			clock-frequency = <20000000>;
		};
		es_eth_ref_clk {
			compatible = "smartlogic,es_eth_ref_clk";
			clock-frequency = <20000000>;
		};

		js_jesd_dev_clk {
			compatible = "smartlogic,js_jesd_dev_clk";
			clock-frequency = <20000000>;
		};

		gmac1_ptp_pps {
			compatible = "smartlogic,gmac1_ptp_pps";
			clock-frequency = <20000000>;
		};
		gmac0_ptp_pps {
			compatible = "smartlogic,gmac0_ptp_pps";
			clock-frequency = <20000000>;
		};
		tmac_ptp_pps {
			compatible = "smartlogic,tmac_ptp_pps";
			clock-frequency = <20000000>;
		};
	};		
};
