//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName           : ucp_api_rfic.h
// Author             : boheng.lin@smartlogictech.com
// Date First Issued  : 2023-03-04 17:39:00 PM
// Last Modified      : 
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************

#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_

#include <stdio.h>
#include <stdlib.h>

#ifdef __cplusplus
extern "C" {
#endif

//**********************************************************************************
// system option layer
extern int32_t UCP_API_RFIC_CellInit(void);

/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);

/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);

//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);

/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Init(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);

/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);

/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);

/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);

/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);

/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);

//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);

/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);

/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);

/**
* \brief let the clockGen chip's systemclock one tick.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_OnePluse(uint8_t enable);

#ifdef __cplusplus
}
#endif

#endif /* #ifndef UCP_API_RFIC_H_ */

