yb_arm/rfic/inc/ucp_api_rfic.h

//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName           : ucp_api_rfic.h
// Author             : Boheng Lin bhlin919@126.com
// Date First Issued  : 2023-03-04 17:39:00 PM
// Last Modified      : 
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************

#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_

#include <stdio.h>
#include <stdlib.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 *  \brief define board type
 */
 enum {
    HW_UNKNOW = 0,
    HW_EVMT,     
    HW_EVMF,     
    HW_EVB,      
    HW_EVMY,     
    HW_OTHER  = 254,
    HW_MAX    = 255
};

/**
 *  \brief define some paras for cell init
 */
enum {
    CFG_SAMPLERATE_61_44MHZ  = 61440000,
    CFG_SAMPLERATE_122_88MHZ = 122880000,
    CFG_SAMPLERATE_245_76MHZ = 245760000
};

enum {
    CFG_BW_20MHZ  = 20000000,
    CFG_BW_50MHZ  = 50000000,
    CFG_BW_100MHZ = 100000000,
    CFG_BW_200MHZ = 200000000,
    CFG_BW_240MHZ = 240000000
};

enum {
    CFG_1ANT = 1,
    CFG_2ANT = 2,
    CFG_3ANT = 3,
    CFG_4ANT = 4,
    CFG_5ANT = 5,
    CFG_6ANT = 6,
    CFG_7ANT = 7,
    CFG_8ANT = 8
};

enum {
    CFG_TDD = 0,
    CFG_FDD = 1
};

enum {
    CFG_NORX = 0,
    CFG_TLO_ORX = 1,
    CFG_ALO_ORX = 2,
    CFG_RLO_ORX = 3
};

enum {
    CFG_204B= 0,
    CFG_204C = 1
};

enum {
    CFG_NONE_LOG = 0,
    CFG_LOG = 1
};

/**
 *  \brief define cal para struct
 */

typedef struct ucp_rfic_calPara
{
    int16_t  calOrxGainIndex;
    int16_t  calChAttPara[16];
} ucp_rfic_calPara_t;

//**********************************************************************************
// system option layer
/**
* \brief Sets up the cell's default config
*
* \param sampleRate is Transceiver's sample Rate (Unit hz. 122.88Mhz 245.76Mhz or 61.44Mhz).
* \param bw is bandwidth (Unit hz).
* \param antNumb is the number of antennas (range 1 ~ 8).
* \param enFdd (0: TDD mode, 1: FDD mode).
* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo).
* \param en204C(0: 204B mode, 1: 204C mode).
* \param enUcpLog(0: disable configture Log, 1: enable configture Log).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t sampleRate, 
                                     uint64_t bw,
                                     uint16_t antNumb,
                                     uint16_t enFdd,
                                     uint16_t enOrx,
                                     uint16_t en204C,
                                     uint16_t enUcpLog);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
* \param initGain is Initialize rx Gain index (Unit db, range 183 ~ 255).
* \param auxLo is orx local frequency (Unit hz).
* \param calPara is paras for RX QEC、TX att cal and so on
* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, 
                                      uint16_t initGain, uint64_t auxLo, uint16_t enOrx, 
                                      ucp_rfic_calPara_t calPara);

/**
* \brief delete cell.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);

//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);

/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);

/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);

/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);

/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);

/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);

//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);

/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);

/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);

/**
* \brief gpio of rf controlling
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_GPIO_Tx (void);
extern void UCP_API_GPIO_Rx (void);
extern void UCP_API_GPIO_Off (void);
extern void UCP_API_GPIO_OrxOn (void);
extern void UCP_API_GPIO_OrxOff (void);
extern void UCP_API_GPIO_TrigOn (void);
extern void UCP_API_GPIO_TrigOff (void);

/**
* \brief Get board's indx
*
* \param void
*
* \retval

    HW_UNKNOW = 0
    HW_EVMT   = 1    
    HW_EVMF   = 2    
    HW_EVB    = 3     
    HW_EVMY   = 4     
    HW_OTHER  = 254
    HW_MAX    = 255
    
*/
extern uint8_t UCP_API_RFIC_GetBoardInfo (void);

#ifdef __cplusplus
}
#endif

#endif /* #ifndef UCP_API_RFIC_H_ */