646 lines
61 KiB
C
646 lines
61 KiB
C
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#ifndef __TMAC_H__
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#define __TMAC_H__
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#define TMAC_DWCXL_CORE_BaseAddress 0x09090000
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#define TMAC_DWCXL_MTL_BaseAddress 0x09091000
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#define TMAC_DWCXL_MTL_TCQ0_BaseAddress 0x09091100
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#define TMAC_DWCXL_MTL_TCQ1_BaseAddress 0x09091180
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#define TMAC_DWCXL_MTL_TCQ2_BaseAddress 0x09091200
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#define TMAC_DWCXL_MTL_TCQ3_BaseAddress 0x09091280
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#define TMAC_DWCXL_MTL_TCQ4_BaseAddress 0x09091300
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#define TMAC_DWCXL_MTL_TCQ5_BaseAddress 0x09091380
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#define TMAC_DWCXL_DMA_BaseAddress 0x09093000
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#define TMAC_DWCXL_DMA_CH0_BaseAddress 0x09093100
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#define TMAC_DWCXL_DMA_CH1_BaseAddress 0x09093180
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#define TMAC_DWCXL_DMA_CH2_BaseAddress 0x09093200
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#define TMAC_DWCXL_DMA_CH3_BaseAddress 0x09093280
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#define TMAC_DWCXL_DMA_CH4_BaseAddress 0x09093300
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#define TMAC_DWCXL_DMA_CH5_BaseAddress 0x09093380
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#define TMAC_DWCXL_DMA_DUMMY_BaseAddress 0x09093ff8
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#define TMAC_CTRL_BASE 0x09098000
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#define TMAC_RST_CTRL_REG (TMAC_CTRL_BASE + 0x0 )
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#define TMAC_RST_TIMING_REG (TMAC_CTRL_BASE + 0x4 )
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#define TMAC_STATUS_REG (TMAC_CTRL_BASE + 0x8 )
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#define TMAC_SDB_CTRL_REG (TMAC_CTRL_BASE + 0xc )
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#define TMAC_SPEED_REG (TMAC_CTRL_BASE + 0x10)
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#define TMAC_PCS_LANE_ENABLE_REG (TMAC_CTRL_BASE + 0x14)
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#define TMAC_SNAP_CTRL_REG (TMAC_CTRL_BASE + 0x18)
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#define TMAC_SNAP_TRI_REG (TMAC_CTRL_BASE + 0x1c)
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#define TMAC_TS_REG0 (TMAC_CTRL_BASE + 0x20)
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#define TMAC_TS_REG1 (TMAC_CTRL_BASE + 0x24)
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#define TMAC_INT_FLAG_REG (TMAC_CTRL_BASE + 0x28)
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#define TMAC_INT_EN_REG (TMAC_CTRL_BASE + 0x2c)
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#define TMAC_MAC_Tx_Configuration (TMAC_DWCXL_CORE_BaseAddress + 0x0 )
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#define TMAC_MAC_Rx_Configuration (TMAC_DWCXL_CORE_BaseAddress + 0x4 )
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#define TMAC_MAC_Packet_Filter (TMAC_DWCXL_CORE_BaseAddress + 0x8 )
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#define TMAC_MAC_Watchdog_Timeout (TMAC_DWCXL_CORE_BaseAddress + 0xc )
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#define TMAC_MAC_Hash_Table_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0x10 )
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#define TMAC_MAC_Hash_Table_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0x14 )
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#define TMAC_MAC_Hash_Table_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0x18 )
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#define TMAC_MAC_Hash_Table_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0x1c )
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#define TMAC_MAC_Hash_Table_Reg4 (TMAC_DWCXL_CORE_BaseAddress + 0x20 )
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#define TMAC_MAC_Hash_Table_Reg5 (TMAC_DWCXL_CORE_BaseAddress + 0x24 )
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#define TMAC_MAC_Hash_Table_Reg6 (TMAC_DWCXL_CORE_BaseAddress + 0x28 )
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#define TMAC_MAC_Hash_Table_Reg7 (TMAC_DWCXL_CORE_BaseAddress + 0x2c )
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#define TMAC_MAC_VLAN_Tag_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x50 )
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#define TMAC_MAC_VLAN_Tag_Data (TMAC_DWCXL_CORE_BaseAddress + 0x54 )
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#define TMAC_MAC_VLAN_Tag_Filter0 (TMAC_DWCXL_CORE_BaseAddress + 0x54 )
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#define TMAC_MAC_VLAN_Tag_Filter1 (TMAC_DWCXL_CORE_BaseAddress + 0x54 )
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#define TMAC_MAC_VLAN_Tag_Filter2 (TMAC_DWCXL_CORE_BaseAddress + 0x54 )
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#define TMAC_MAC_VLAN_Tag_Filter3 (TMAC_DWCXL_CORE_BaseAddress + 0x54 )
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#define TMAC_MAC_VLAN_Hash_Table (TMAC_DWCXL_CORE_BaseAddress + 0x58 )
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#define TMAC_MAC_VLAN_Incl (TMAC_DWCXL_CORE_BaseAddress + 0x60 )
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#define TMAC_MAC_Inner_VLAN_Incl (TMAC_DWCXL_CORE_BaseAddress + 0x64 )
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#define TMAC_MAC_Rx_Eth_Type_Match (TMAC_DWCXL_CORE_BaseAddress + 0x6c )
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#define TMAC_MAC_PRI0_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x70 )
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#define TMAC_MAC_PRI1_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x74 )
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#define TMAC_MAC_PRI2_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x78 )
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#define TMAC_MAC_PRI3_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x7c )
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#define TMAC_MAC_PRI4_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x80 )
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#define TMAC_MAC_PRI5_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x84 )
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#define TMAC_MAC_PRI6_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x88 )
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#define TMAC_MAC_PRI7_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x8c )
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#define TMAC_MAC_Rx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x90 )
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#define TMAC_MAC_Interrupt_Status (TMAC_DWCXL_CORE_BaseAddress + 0xb0 )
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#define TMAC_MAC_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0xb4 )
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#define TMAC_MAC_Rx_Tx_Status (TMAC_DWCXL_CORE_BaseAddress + 0xb8 )
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#define TMAC_MAC_PMT_Control_Status (TMAC_DWCXL_CORE_BaseAddress + 0xc0 )
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#define TMAC_MAC_RWK_Packet_Filter (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter0123_Command (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter0123_Offset (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter01_CRC (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter0_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter1_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter23_CRC (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter2_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_RWK_Filter3_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 )
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#define TMAC_MAC_LPI_Control_Status (TMAC_DWCXL_CORE_BaseAddress + 0xd0 )
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#define TMAC_MAC_LPI_Timers_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd4 )
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#define TMAC_MAC_LPI_Auto_Entry_Timer (TMAC_DWCXL_CORE_BaseAddress + 0xd8 )
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#define TMAC_MAC_1US_Tic_Counter (TMAC_DWCXL_CORE_BaseAddress + 0xdc )
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#define TMAC_MAC_Version (TMAC_DWCXL_CORE_BaseAddress + 0x110)
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#define TMAC_MAC_Debug (TMAC_DWCXL_CORE_BaseAddress + 0x114)
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#define TMAC_MAC_HW_Feature0 (TMAC_DWCXL_CORE_BaseAddress + 0x11c)
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#define TMAC_MAC_HW_Feature1 (TMAC_DWCXL_CORE_BaseAddress + 0x120)
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#define TMAC_MAC_HW_Feature2 (TMAC_DWCXL_CORE_BaseAddress + 0x124)
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#define TMAC_MAC_RxQ_Enable_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x140)
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#define TMAC_MAC_RxQ_Mapping_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x150)
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#define TMAC_MAC_RxQ_Mapping_Ctrl1 (TMAC_DWCXL_CORE_BaseAddress + 0x154)
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#define TMAC_MAC_RxQ_Priority_Mapping_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x160)
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#define TMAC_MAC_RxQ_Priority_Mapping_Ctrl1 (TMAC_DWCXL_CORE_BaseAddress + 0x164)
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#define TMAC_MDIO_Single_Command_Address (TMAC_DWCXL_CORE_BaseAddress + 0x200)
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#define TMAC_MDIO_Single_Command_Control_Data (TMAC_DWCXL_CORE_BaseAddress + 0x204)
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#define TMAC_MDIO_Continuous_Write_Address (TMAC_DWCXL_CORE_BaseAddress + 0x208)
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#define TMAC_MDIO_Continuous_Write_Data (TMAC_DWCXL_CORE_BaseAddress + 0x20c)
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#define TMAC_MDIO_Continuous_Scan_Port_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x210)
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#define TMAC_MDIO_Interrupt_Status (TMAC_DWCXL_CORE_BaseAddress + 0x214)
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#define TMAC_MDIO_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x218)
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#define TMAC_MDIO_Port_Connect_Disconnect_Status (TMAC_DWCXL_CORE_BaseAddress + 0x21c)
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#define TMAC_MDIO_Clause_22_Port (TMAC_DWCXL_CORE_BaseAddress + 0x220)
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#define TMAC_MDIO_Port0_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x230)
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#define TMAC_MDIO_Port0_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x234)
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#define TMAC_MDIO_Port0_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x238)
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#define TMAC_MDIO_Port1_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x240)
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#define TMAC_MDIO_Port1_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x244)
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#define TMAC_MDIO_Port1_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x248)
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#define TMAC_MDIO_Port2_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x250)
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#define TMAC_MDIO_Port2_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x254)
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#define TMAC_MDIO_Port2_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x258)
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#define TMAC_MDIO_Port3_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x260)
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#define TMAC_MDIO_Port3_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x264)
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#define TMAC_MDIO_Port3_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x268)
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#define TMAC_MAC_Address0_High (TMAC_DWCXL_CORE_BaseAddress + 0x300)
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#define TMAC_MAC_Address0_Low (TMAC_DWCXL_CORE_BaseAddress + 0x304)
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#define TMAC_MAC_Address1_High (TMAC_DWCXL_CORE_BaseAddress + 0x308)
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#define TMAC_MAC_Address1_Low (TMAC_DWCXL_CORE_BaseAddress + 0x30c)
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#define TMAC_MAC_Address2_High (TMAC_DWCXL_CORE_BaseAddress + 0x310)
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#define TMAC_MAC_Address2_Low (TMAC_DWCXL_CORE_BaseAddress + 0x314)
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#define TMAC_MAC_Address3_High (TMAC_DWCXL_CORE_BaseAddress + 0x318)
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#define TMAC_MAC_Address3_Low (TMAC_DWCXL_CORE_BaseAddress + 0x31c)
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#define TMAC_MAC_Address4_High (TMAC_DWCXL_CORE_BaseAddress + 0x320)
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#define TMAC_MAC_Address4_Low (TMAC_DWCXL_CORE_BaseAddress + 0x324)
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#define TMAC_MAC_Address5_High (TMAC_DWCXL_CORE_BaseAddress + 0x328)
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#define TMAC_MAC_Address5_Low (TMAC_DWCXL_CORE_BaseAddress + 0x32c)
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#define TMAC_MAC_Address6_High (TMAC_DWCXL_CORE_BaseAddress + 0x330)
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#define TMAC_MAC_Address6_Low (TMAC_DWCXL_CORE_BaseAddress + 0x334)
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#define TMAC_MAC_Address7_High (TMAC_DWCXL_CORE_BaseAddress + 0x338)
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#define TMAC_MAC_Address7_Low (TMAC_DWCXL_CORE_BaseAddress + 0x33c)
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#define TMAC_MAC_Address8_High (TMAC_DWCXL_CORE_BaseAddress + 0x340)
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#define TMAC_MAC_Address8_Low (TMAC_DWCXL_CORE_BaseAddress + 0x344)
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#define TMAC_MMC_Control (TMAC_DWCXL_CORE_BaseAddress + 0x800)
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#define TMAC_MMC_Receive_Interrupt (TMAC_DWCXL_CORE_BaseAddress + 0x804)
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#define TMAC_MMC_Transmit_Interrupt (TMAC_DWCXL_CORE_BaseAddress + 0x808)
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#define TMAC_MMC_Receive_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x80c)
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#define TMAC_MMC_Transmit_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x810)
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#define TMAC_Tx_Octet_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x814)
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#define TMAC_Tx_Octet_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x818)
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#define TMAC_Tx_Frame_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x81c)
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#define TMAC_Tx_Frame_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x820)
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#define TMAC_Tx_Broadcast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x824)
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#define TMAC_Tx_Broadcast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x828)
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#define TMAC_Tx_Multicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x82c)
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#define TMAC_Tx_Multicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x830)
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#define TMAC_Tx_64Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x834)
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#define TMAC_Tx_64Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x838)
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#define TMAC_Tx_65To127Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x83c)
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#define TMAC_Tx_65To127Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x840)
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#define TMAC_Tx_128To255Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x844)
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#define TMAC_Tx_128To255Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x848)
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#define TMAC_Tx_256To511Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x84c)
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#define TMAC_Tx_256To511Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x850)
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#define TMAC_Tx_512To1023Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x854)
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#define TMAC_Tx_512To1023Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x858)
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#define TMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x85c)
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#define TMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x860)
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#define TMAC_Tx_Unicast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x864)
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#define TMAC_Tx_Unicast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x868)
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#define TMAC_Tx_Multicast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x86c)
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#define TMAC_Tx_Multicast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x870)
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#define TMAC_Tx_Broadcast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x874)
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#define TMAC_Tx_Broadcast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x878)
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#define TMAC_Tx_Underflow_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x87c)
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#define TMAC_Tx_Underflow_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x880)
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#define TMAC_Tx_Octet_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x884)
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#define TMAC_Tx_Octet_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x888)
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#define TMAC_Tx_Frame_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x88c)
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#define TMAC_Tx_Frame_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x890)
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#define TMAC_Tx_Pause_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x894)
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#define TMAC_Tx_Pause_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x898)
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#define TMAC_Tx_VLAN_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x89c)
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#define TMAC_Tx_VLAN_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x8a0)
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#define TMAC_Rx_Frame_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x900)
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#define TMAC_Rx_Frame_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x904)
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#define TMAC_Rx_Octet_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x908)
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#define TMAC_Rx_Octet_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x90c)
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#define TMAC_Rx_Octet_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x910)
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#define TMAC_Rx_Octet_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x914)
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#define TMAC_Rx_Broadcast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x918)
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#define TMAC_Rx_Broadcast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x91c)
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#define TMAC_Rx_Multicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x920)
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#define TMAC_Rx_Multicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x924)
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#define TMAC_Rx_CRC_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x928)
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#define TMAC_Rx_CRC_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x92c)
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#define TMAC_Rx_Runt_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x930)
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#define TMAC_Rx_Jabber_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x934)
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#define TMAC_Rx_Undersize_Frames_Good (TMAC_DWCXL_CORE_BaseAddress + 0x938)
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#define TMAC_Rx_Oversize_Frames_Good (TMAC_DWCXL_CORE_BaseAddress + 0x93c)
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#define TMAC_Rx_64Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x940)
|
||
|
|
#define TMAC_Rx_64Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x944)
|
||
|
|
#define TMAC_Rx_65To127Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x948)
|
||
|
|
#define TMAC_Rx_65To127Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x94c)
|
||
|
|
#define TMAC_Rx_128To255Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x950)
|
||
|
|
#define TMAC_Rx_128To255Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x954)
|
||
|
|
#define TMAC_Rx_256To511Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x958)
|
||
|
|
#define TMAC_Rx_256To511Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x95c)
|
||
|
|
#define TMAC_Rx_512To1023Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x960)
|
||
|
|
#define TMAC_Rx_512To1023Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x964)
|
||
|
|
#define TMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x968)
|
||
|
|
#define TMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x96c)
|
||
|
|
#define TMAC_Rx_Unicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x970)
|
||
|
|
#define TMAC_Rx_Unicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x974)
|
||
|
|
#define TMAC_Rx_Length_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x978)
|
||
|
|
#define TMAC_Rx_Length_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x97c)
|
||
|
|
#define TMAC_Rx_OutofRange_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x980)
|
||
|
|
#define TMAC_Rx_OutofRange_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x984)
|
||
|
|
#define TMAC_Rx_Pause_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x988)
|
||
|
|
#define TMAC_Rx_Pause_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x98c)
|
||
|
|
#define TMAC_Rx_VLAN_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x998)
|
||
|
|
#define TMAC_Rx_VLAN_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x99c)
|
||
|
|
#define TMAC_Rx_Watchdog_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x9a0)
|
||
|
|
#define TMAC_MAC_L3_L4_Address_Control (TMAC_DWCXL_CORE_BaseAddress + 0xc00)
|
||
|
|
#define TMAC_MAC_L3_L4_Control0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_L3_L4_Control1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_L3_L4_Control2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_L3_L4_Control3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_L3_L4_Data (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr0_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr0_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr0_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr0_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr1_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr1_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr1_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr1_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr2_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr2_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr2_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr2_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr3_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr3_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr3_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer3_Addr3_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer4_Address0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer4_Address1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer4_Address2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_Layer4_Address3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04)
|
||
|
|
#define TMAC_MAC_RSS_Control (TMAC_DWCXL_CORE_BaseAddress + 0xc80)
|
||
|
|
#define TMAC_MAC_RSS_Address (TMAC_DWCXL_CORE_BaseAddress + 0xc88)
|
||
|
|
#define TMAC_MAC_RSS_Data (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key11_8 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key15_12 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key19_16 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key23_20 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key27_24 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key31_28 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key35_32 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key39_36 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key3_0 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Hash_Key7_4 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data0 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data1 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data10 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data11 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data12 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data13 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data14 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data15 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data16 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data17 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data18 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data19 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data2 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data20 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data21 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data22 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data23 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data24 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data25 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data26 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data27 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data28 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data29 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data3 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data30 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data31 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data32 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data33 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data34 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data35 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data36 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data37 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data38 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data39 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data4 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data40 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data41 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data42 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data43 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data44 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data45 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data46 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data47 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data48 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data49 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data5 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data50 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data51 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data52 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data53 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data54 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data55 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data56 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data57 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data58 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data59 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data6 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data60 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data61 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data62 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data63 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data7 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data8 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_RSS_Lookup_Data9 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c)
|
||
|
|
#define TMAC_MAC_Timestamp_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd00)
|
||
|
|
#define TMAC_MAC_Sub_Second_Increment (TMAC_DWCXL_CORE_BaseAddress + 0xd04)
|
||
|
|
#define TMAC_MAC_System_Time_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd08)
|
||
|
|
#define TMAC_MAC_System_Time_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd0c)
|
||
|
|
#define TMAC_MAC_System_Time_Seconds_Update (TMAC_DWCXL_CORE_BaseAddress + 0xd10)
|
||
|
|
#define TMAC_MAC_System_Time_Nanoseconds_Update (TMAC_DWCXL_CORE_BaseAddress + 0xd14)
|
||
|
|
#define TMAC_MAC_Timestamp_Addend (TMAC_DWCXL_CORE_BaseAddress + 0xd18)
|
||
|
|
#define TMAC_MAC_System_Time_Higher_Word_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd1c)
|
||
|
|
#define TMAC_MAC_Timestamp_Status (TMAC_DWCXL_CORE_BaseAddress + 0xd20)
|
||
|
|
#define TMAC_MAC_Tx_Timestamp_Status_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd30)
|
||
|
|
#define TMAC_MAC_Tx_Timestamp_Status_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd34)
|
||
|
|
#define TMAC_MAC_Auxiliary_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd40)
|
||
|
|
#define TMAC_MAC_Auxiliary_Timestamp_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd48)
|
||
|
|
#define TMAC_MAC_Auxiliary_Timestamp_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd4c)
|
||
|
|
#define TMAC_MAC_Timestamp_Ingress_Asym_Corr (TMAC_DWCXL_CORE_BaseAddress + 0xd50)
|
||
|
|
#define TMAC_MAC_Timestamp_Egress_Asym_Corr (TMAC_DWCXL_CORE_BaseAddress + 0xd54)
|
||
|
|
#define TMAC_MAC_Timestamp_Ingress_Corr_Nanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd58)
|
||
|
|
#define TMAC_MAC_Timestamp_Ingress_Corr_Subnanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd5c)
|
||
|
|
#define TMAC_MAC_Timestamp_Egress_Corr_Nanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd60)
|
||
|
|
#define TMAC_MAC_Timestamp_Egress_Corr_Subnanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd64)
|
||
|
|
#define TMAC_MAC_PPS_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd70)
|
||
|
|
#define TMAC_MAC_PPS0_Target_Time_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd80)
|
||
|
|
#define TMAC_MAC_PPS0_Target_Time_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd84)
|
||
|
|
#define TMAC_MAC_PPS0_Interval (TMAC_DWCXL_CORE_BaseAddress + 0xd88)
|
||
|
|
#define TMAC_MAC_PPS0_Width (TMAC_DWCXL_CORE_BaseAddress + 0xd8c)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define TMAC_MTL_Operation_Mode (TMAC_DWCXL_MTL_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_MTL_Debug_Control (TMAC_DWCXL_MTL_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_MTL_Debug_Status (TMAC_DWCXL_MTL_BaseAddress + 0xc )
|
||
|
|
#define TMAC_MTL_FIFO_Debug_Data (TMAC_DWCXL_MTL_BaseAddress + 0x10)
|
||
|
|
#define TMAC_MTL_Interrupt_Status (TMAC_DWCXL_MTL_BaseAddress + 0x20)
|
||
|
|
#define TMAC_MTL_RxQ_DMA_Map0 (TMAC_DWCXL_MTL_BaseAddress + 0x30)
|
||
|
|
#define TMAC_MTL_RxQ_DMA_Map1 (TMAC_DWCXL_MTL_BaseAddress + 0x34)
|
||
|
|
#define TMAC_MTL_TC_Prty_Map0 (TMAC_DWCXL_MTL_BaseAddress + 0x40)
|
||
|
|
#define TMAC_MTL_TC_Prty_Map1 (TMAC_DWCXL_MTL_BaseAddress + 0x44)
|
||
|
|
|
||
|
|
#define TMAC_MTL_TxQ0_Operation_Mode (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_MTL_TxQ0_Underflow (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_MTL_TxQ0_Debug (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_MTL_TC0_ETS_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x10)
|
||
|
|
#define TMAC_MTL_TC0_ETS_Status (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x14)
|
||
|
|
#define TMAC_MTL_TC0_Quantum_Weight (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x18)
|
||
|
|
#define TMAC_MTL_RxQ0_Operation_Mode (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x40)
|
||
|
|
#define TMAC_MTL_RxQ0_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x44)
|
||
|
|
#define TMAC_MTL_RxQ0_Debug (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x48)
|
||
|
|
#define TMAC_MTL_RxQ0_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_MTL_RxQ0_Flow_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x50)
|
||
|
|
#define TMAC_MTL_Q0_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x70)
|
||
|
|
#define TMAC_MTL_Q0_Interrupt_Status (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x74)
|
||
|
|
|
||
|
|
#define TMAC_MTL_TxQ1_Operation_Mode (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_MTL_TxQ1_Underflow (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_MTL_TxQ1_Debug (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_MTL_TC1_ETS_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x10)
|
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|
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#define TMAC_MTL_TC1_ETS_Status (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x14)
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|
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#define TMAC_MTL_TC1_Quantum_Weight (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x18)
|
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|
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#define TMAC_MTL_RxQ1_Operation_Mode (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x40)
|
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|
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#define TMAC_MTL_RxQ1_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x44)
|
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|
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#define TMAC_MTL_RxQ1_Debug (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x48)
|
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|
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#define TMAC_MTL_RxQ1_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x4c)
|
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|
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#define TMAC_MTL_RxQ1_Flow_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x50)
|
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#define TMAC_MTL_Q1_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x70)
|
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|
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#define TMAC_MTL_Q1_Interrupt_Status (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x74)
|
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|
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|
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#define TMAC_MTL_TxQ2_Operation_Mode (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x0 )
|
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#define TMAC_MTL_TxQ2_Underflow (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x4 )
|
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#define TMAC_MTL_TxQ2_Debug (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x8 )
|
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|
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#define TMAC_MTL_TC2_ETS_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x10)
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#define TMAC_MTL_TC2_ETS_Status (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x14)
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#define TMAC_MTL_TC2_Quantum_Weight (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x18)
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#define TMAC_MTL_RxQ2_Operation_Mode (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x40)
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#define TMAC_MTL_RxQ2_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x44)
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#define TMAC_MTL_RxQ2_Debug (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x48)
|
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#define TMAC_MTL_RxQ2_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x4c)
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#define TMAC_MTL_RxQ2_Flow_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x50)
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#define TMAC_MTL_Q2_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x70)
|
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#define TMAC_MTL_Q2_Interrupt_Status (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x74)
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#define TMAC_MTL_TxQ3_Operation_Mode (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x0 )
|
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|
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#define TMAC_MTL_TxQ3_Underflow (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x4 )
|
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|
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#define TMAC_MTL_TxQ3_Debug (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x8 )
|
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|
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#define TMAC_MTL_TC3_ETS_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x10)
|
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#define TMAC_MTL_TC3_ETS_Status (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x14)
|
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|
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#define TMAC_MTL_TC3_Quantum_Weight (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x18)
|
||
|
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#define TMAC_MTL_TC3_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x1c)
|
||
|
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#define TMAC_MTL_RxQ3_Operation_Mode (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x40)
|
||
|
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#define TMAC_MTL_RxQ3_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x44)
|
||
|
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#define TMAC_MTL_RxQ3_Debug (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x48)
|
||
|
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#define TMAC_MTL_RxQ3_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x4c)
|
||
|
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#define TMAC_MTL_RxQ3_Flow_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x50)
|
||
|
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#define TMAC_MTL_Q3_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x70)
|
||
|
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#define TMAC_MTL_Q3_Interrupt_Status (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x74)
|
||
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|
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|
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#define TMAC_MTL_TxQ4_Operation_Mode (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_MTL_TxQ4_Underflow (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_MTL_TxQ4_Debug (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_MTL_TC4_ETS_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x10)
|
||
|
|
#define TMAC_MTL_TC4_ETS_Status (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x14)
|
||
|
|
#define TMAC_MTL_TC4_Quantum_Weight (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x18)
|
||
|
|
#define TMAC_MTL_TC4_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x1c)
|
||
|
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#define TMAC_MTL_TC4_HiCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x20)
|
||
|
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#define TMAC_MTL_TC4_LoCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x24)
|
||
|
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#define TMAC_MTL_RxQ4_Operation_Mode (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x40)
|
||
|
|
#define TMAC_MTL_RxQ4_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x44)
|
||
|
|
#define TMAC_MTL_RxQ4_Debug (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x48)
|
||
|
|
#define TMAC_MTL_RxQ4_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_MTL_RxQ4_Flow_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x50)
|
||
|
|
#define TMAC_MTL_Q4_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x70)
|
||
|
|
#define TMAC_MTL_Q4_Interrupt_Status (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x74)
|
||
|
|
|
||
|
|
#define TMAC_MTL_TxQ5_Operation_Mode (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_MTL_TxQ5_Underflow (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_MTL_TxQ5_Debug (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_MTL_TC5_ETS_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x10)
|
||
|
|
#define TMAC_MTL_TC5_ETS_Status (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x14)
|
||
|
|
#define TMAC_MTL_TC5_Quantum_Weight (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x18)
|
||
|
|
#define TMAC_MTL_TC5_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x1c)
|
||
|
|
#define TMAC_MTL_TC5_HiCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x20)
|
||
|
|
#define TMAC_MTL_TC5_LoCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x24)
|
||
|
|
#define TMAC_MTL_RxQ5_Operation_Mode (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x40)
|
||
|
|
#define TMAC_MTL_RxQ5_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x44)
|
||
|
|
#define TMAC_MTL_RxQ5_Debug (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x48)
|
||
|
|
#define TMAC_MTL_RxQ5_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_MTL_RxQ5_Flow_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x50)
|
||
|
|
#define TMAC_MTL_Q5_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x70)
|
||
|
|
#define TMAC_MTL_Q5_Interrupt_Status (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x74)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define TMAC_DMA_Mode (TMAC_DWCXL_DMA_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_DMA_SysBus_Mode (TMAC_DWCXL_DMA_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_DMA_Interrupt_Status (TMAC_DWCXL_DMA_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_AXI_Tx_AR_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x10)
|
||
|
|
#define TMAC_AXI_Rx_AW_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x18)
|
||
|
|
#define TMAC_AXI_TxRx_AWAR_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x1c)
|
||
|
|
#define TMAC_DMA_Debug_Status0 (TMAC_DWCXL_DMA_BaseAddress + 0x20)
|
||
|
|
#define TMAC_DMA_Debug_Status1 (TMAC_DWCXL_DMA_BaseAddress + 0x24)
|
||
|
|
#define TMAC_DMA_Debug_Status3 (TMAC_DWCXL_DMA_BaseAddress + 0x2c)
|
||
|
|
#define TMAC_DMA_Tx_EDMA_Control (TMAC_DWCXL_DMA_BaseAddress + 0x40)
|
||
|
|
#define TMAC_DMA_Rx_EDMA_Control (TMAC_DWCXL_DMA_BaseAddress + 0x44)
|
||
|
|
#define TMAC_AXI_LPI_Entry_Interval (TMAC_DWCXL_DMA_BaseAddress + 0x50)
|
||
|
|
|
||
|
|
#define TMAC_DMA_CH0_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_DMA_CH0_Tx_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_DMA_CH0_Rx_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_DMA_CH0_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x10)
|
||
|
|
#define TMAC_DMA_CH0_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x14)
|
||
|
|
#define TMAC_DMA_CH0_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x18)
|
||
|
|
#define TMAC_DMA_CH0_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x1c)
|
||
|
|
#define TMAC_DMA_CH0_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x20)
|
||
|
|
#define TMAC_DMA_CH0_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x24)
|
||
|
|
#define TMAC_DMA_CH0_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x28)
|
||
|
|
#define TMAC_DMA_CH0_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x2c)
|
||
|
|
#define TMAC_DMA_CH0_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x30)
|
||
|
|
#define TMAC_DMA_CH0_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x34)
|
||
|
|
#define TMAC_DMA_CH0_Interrupt_Enable (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x38)
|
||
|
|
#define TMAC_DMA_CH0_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x3c)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x44)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x50)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x54)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x58)
|
||
|
|
#define TMAC_DMA_CH0_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x5c)
|
||
|
|
#define TMAC_DMA_CH0_Status (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x60)
|
||
|
|
#define TMAC_DMA_CH0_Debug_Status (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x64)
|
||
|
|
#define TMAC_DMA_CH0_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x68)
|
||
|
|
#define TMAC_DMA_CH0_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x6c)
|
||
|
|
#define TMAC_DMA_CH0_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x70)
|
||
|
|
#define TMAC_DMA_CH0_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x74)
|
||
|
|
#define TMAC_DMA_CH0_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x78)
|
||
|
|
#define TMAC_DMA_CH0_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x7c)
|
||
|
|
|
||
|
|
#define TMAC_DMA_CH1_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_DMA_CH1_Tx_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_DMA_CH1_Rx_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_DMA_CH1_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x10)
|
||
|
|
#define TMAC_DMA_CH1_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x14)
|
||
|
|
#define TMAC_DMA_CH1_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x18)
|
||
|
|
#define TMAC_DMA_CH1_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x1c)
|
||
|
|
#define TMAC_DMA_CH1_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x20)
|
||
|
|
#define TMAC_DMA_CH1_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x24)
|
||
|
|
#define TMAC_DMA_CH1_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x28)
|
||
|
|
#define TMAC_DMA_CH1_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x2c)
|
||
|
|
#define TMAC_DMA_CH1_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x30)
|
||
|
|
#define TMAC_DMA_CH1_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x34)
|
||
|
|
#define TMAC_DMA_CH1_Interrupt_Enable (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x38)
|
||
|
|
#define TMAC_DMA_CH1_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x3c)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x44)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x50)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x54)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x58)
|
||
|
|
#define TMAC_DMA_CH1_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x5c)
|
||
|
|
#define TMAC_DMA_CH1_Status (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x60)
|
||
|
|
#define TMAC_DMA_CH1_Debug_Status (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x64)
|
||
|
|
#define TMAC_DMA_CH1_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x68)
|
||
|
|
#define TMAC_DMA_CH1_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x6c)
|
||
|
|
#define TMAC_DMA_CH1_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x70)
|
||
|
|
#define TMAC_DMA_CH1_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x74)
|
||
|
|
#define TMAC_DMA_CH1_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x78)
|
||
|
|
#define TMAC_DMA_CH1_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x7c)
|
||
|
|
|
||
|
|
#define TMAC_DMA_CH2_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x0 )
|
||
|
|
#define TMAC_DMA_CH2_Tx_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x4 )
|
||
|
|
#define TMAC_DMA_CH2_Rx_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x8 )
|
||
|
|
#define TMAC_DMA_CH2_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x10)
|
||
|
|
#define TMAC_DMA_CH2_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x14)
|
||
|
|
#define TMAC_DMA_CH2_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x18)
|
||
|
|
#define TMAC_DMA_CH2_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x1c)
|
||
|
|
#define TMAC_DMA_CH2_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x20)
|
||
|
|
#define TMAC_DMA_CH2_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x24)
|
||
|
|
#define TMAC_DMA_CH2_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x28)
|
||
|
|
#define TMAC_DMA_CH2_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x2c)
|
||
|
|
#define TMAC_DMA_CH2_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x30)
|
||
|
|
#define TMAC_DMA_CH2_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x34)
|
||
|
|
#define TMAC_DMA_CH2_Interrupt_Enable (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x38)
|
||
|
|
#define TMAC_DMA_CH2_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x3c)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x44)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x4c)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x50)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x54)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x58)
|
||
|
|
#define TMAC_DMA_CH2_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x5c)
|
||
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#define TMAC_DMA_CH2_Status (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x60)
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#define TMAC_DMA_CH2_Debug_Status (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x64)
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#define TMAC_DMA_CH2_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x68)
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#define TMAC_DMA_CH2_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x6c)
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#define TMAC_DMA_CH2_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x70)
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#define TMAC_DMA_CH2_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x74)
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#define TMAC_DMA_CH2_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x78)
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#define TMAC_DMA_CH2_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x7c)
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#define TMAC_DMA_CH3_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x0 )
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#define TMAC_DMA_CH3_Tx_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x4 )
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#define TMAC_DMA_CH3_Rx_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x8 )
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#define TMAC_DMA_CH3_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x10)
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#define TMAC_DMA_CH3_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x14)
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#define TMAC_DMA_CH3_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x18)
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#define TMAC_DMA_CH3_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x1c)
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#define TMAC_DMA_CH3_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x20)
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#define TMAC_DMA_CH3_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x24)
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#define TMAC_DMA_CH3_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x28)
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#define TMAC_DMA_CH3_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x2c)
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#define TMAC_DMA_CH3_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x30)
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#define TMAC_DMA_CH3_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x34)
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#define TMAC_DMA_CH3_Interrupt_Enable (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x38)
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#define TMAC_DMA_CH3_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x3c)
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#define TMAC_DMA_CH3_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x44)
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#define TMAC_DMA_CH3_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x4c)
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#define TMAC_DMA_CH3_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x50)
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#define TMAC_DMA_CH3_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x54)
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#define TMAC_DMA_CH3_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x58)
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#define TMAC_DMA_CH3_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x5c)
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#define TMAC_DMA_CH3_Status (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x60)
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#define TMAC_DMA_CH3_Debug_Status (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x64)
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#define TMAC_DMA_CH3_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x68)
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#define TMAC_DMA_CH3_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x6c)
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#define TMAC_DMA_CH3_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x70)
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#define TMAC_DMA_CH3_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x74)
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#define TMAC_DMA_CH3_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x78)
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#define TMAC_DMA_CH3_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x7c)
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#define TMAC_DMA_CH4_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x0 )
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#define TMAC_DMA_CH4_Tx_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x4 )
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#define TMAC_DMA_CH4_Rx_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x8 )
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#define TMAC_DMA_CH4_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x10)
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#define TMAC_DMA_CH4_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x14)
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#define TMAC_DMA_CH4_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x18)
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#define TMAC_DMA_CH4_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x1c)
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#define TMAC_DMA_CH4_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x20)
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#define TMAC_DMA_CH4_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x24)
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#define TMAC_DMA_CH4_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x28)
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#define TMAC_DMA_CH4_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x2c)
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#define TMAC_DMA_CH4_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x30)
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#define TMAC_DMA_CH4_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x34)
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#define TMAC_DMA_CH4_Interrupt_Enable (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x38)
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#define TMAC_DMA_CH4_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x3c)
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#define TMAC_DMA_CH4_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x44)
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#define TMAC_DMA_CH4_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x4c)
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#define TMAC_DMA_CH4_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x50)
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#define TMAC_DMA_CH4_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x54)
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#define TMAC_DMA_CH4_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x58)
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#define TMAC_DMA_CH4_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x5c)
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#define TMAC_DMA_CH4_Status (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x60)
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#define TMAC_DMA_CH4_Debug_Status (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x64)
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#define TMAC_DMA_CH4_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x68)
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#define TMAC_DMA_CH4_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x6c)
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#define TMAC_DMA_CH4_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x70)
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#define TMAC_DMA_CH4_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x74)
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#define TMAC_DMA_CH4_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x78)
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#define TMAC_DMA_CH4_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x7c)
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#define TMAC_DMA_CH5_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x0 )
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#define TMAC_DMA_CH5_Tx_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x4 )
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#define TMAC_DMA_CH5_Rx_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x8 )
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#define TMAC_DMA_CH5_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x10)
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#define TMAC_DMA_CH5_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x14)
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#define TMAC_DMA_CH5_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x18)
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#define TMAC_DMA_CH5_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x1c)
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#define TMAC_DMA_CH5_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x20)
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#define TMAC_DMA_CH5_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x24)
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#define TMAC_DMA_CH5_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x28)
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#define TMAC_DMA_CH5_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x2c)
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#define TMAC_DMA_CH5_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x30)
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#define TMAC_DMA_CH5_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x34)
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#define TMAC_DMA_CH5_Interrupt_Enable (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x38)
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#define TMAC_DMA_CH5_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x3c)
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#define TMAC_DMA_CH5_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x44)
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#define TMAC_DMA_CH5_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x4c)
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#define TMAC_DMA_CH5_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x50)
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#define TMAC_DMA_CH5_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x54)
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#define TMAC_DMA_CH5_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x58)
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#define TMAC_DMA_CH5_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x5c)
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#define TMAC_DMA_CH5_Status (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x60)
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#define TMAC_DMA_CH5_Debug_Status (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x64)
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#define TMAC_DMA_CH5_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x68)
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#define TMAC_DMA_CH5_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x6c)
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#define TMAC_DMA_CH5_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x70)
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#define TMAC_DMA_CH5_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x74)
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#define TMAC_DMA_CH5_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x78)
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#define TMAC_DMA_CH5_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x7c)
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#define TMAC_DMA_Dummy (TMAC_DWCXL_DMA_DUMMY_BaseAddress + 0x4)
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#endif
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