642 lines
33 KiB
C
642 lines
33 KiB
C
|
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
|
||
|
|
// FileName : ucp_jesd_gpio.c
|
||
|
|
// Author : Boheng Lin bhlin919@126.com
|
||
|
|
// Date First Issued : 2022-09-08 02:37:50 PM
|
||
|
|
// Last Modified :
|
||
|
|
// Description :
|
||
|
|
// ------------------------------------------------------------
|
||
|
|
// Modification History:
|
||
|
|
// Version Date Author Modification Description
|
||
|
|
//
|
||
|
|
//**********************************************************************************
|
||
|
|
|
||
|
|
#include <stdint.h>
|
||
|
|
#include <stdbool.h>
|
||
|
|
#include <unistd.h>
|
||
|
|
#include <string.h>
|
||
|
|
#include "ucp_jesd_gpio.h"
|
||
|
|
#include "ucp_reg_io.h"
|
||
|
|
#include "dw_apb_gpio.h"
|
||
|
|
#include "ucp_rfc.h"
|
||
|
|
#include "ucp_sfr_c.h"
|
||
|
|
#include "ucp_param.h"
|
||
|
|
#include "ucp_api_jesd.h"
|
||
|
|
#include "ucp_jsonTools.h"
|
||
|
|
#include "ucp_hardware.h"
|
||
|
|
|
||
|
|
#define GPIO_INVERSE_ENABLELEVEL(a) (a ? ((UCP_JESD_TRX_GPIO_VALID_LOW == a) ? UCP_JESD_TRX_GPIO_VALID_HIGH : UCP_JESD_TRX_GPIO_VALID_LOW) : a)
|
||
|
|
#define GPIO_RF_ON_PIN_LEVEL(a) ((UCP_JESD_TRX_GPIO_VALID_HIGH == a) ? 1 : 0)
|
||
|
|
#define GPIO_RF_OFF_PIN_LEVEL(a) ((UCP_JESD_TRX_GPIO_VALID_HIGH == a) ? 0 : 1)
|
||
|
|
|
||
|
|
// -------------------------------------------------------
|
||
|
|
// | hardware GPIO pin | software GPIO pin |
|
||
|
|
// | GPIO0A0-GPIO0A31 | 480~511 |
|
||
|
|
// | GPIO0B0-GPIO0B31 | 448~479 |
|
||
|
|
// | GPIO1A0-GPIO1A14 | 433~447 |
|
||
|
|
// | GPIO1B0-GPIO1B31 | 401~432 |
|
||
|
|
// -------------------------------------------------------
|
||
|
|
const tUcpGpioRegTable_t infRegPort0AP_A[] = {
|
||
|
|
/*480 AP_GPIO0A0 */ {PA_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT0},
|
||
|
|
/*481 AP_GPIO0A1 */ {PA_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT1},
|
||
|
|
/*482 AP_GPIO0A2 */ {PA_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT2},
|
||
|
|
/*483 AP_GPIO0A3 */ {PA_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT3},
|
||
|
|
/*484 AP_GPIO0A4 */ {PA_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT4},
|
||
|
|
/*485 AP_GPIO0A5 */ {PA_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT5},
|
||
|
|
/*486 AP_GPIO0A6 */ {PA_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT6},
|
||
|
|
/*487 AP_GPIO0A7 */ {PA_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT7},
|
||
|
|
/*488 AP_GPIO0A8 */ {PA_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT8},
|
||
|
|
/*489 AP_GPIO0A9 */ {PA_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT9},
|
||
|
|
/*490 AP_GPIO0A10 */ {PA_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT10},
|
||
|
|
/*491 AP_GPIO0A11 */ {PA_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT11},
|
||
|
|
/*492 AP_GPIO0A12 */ {PA_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT12},
|
||
|
|
/*493 AP_GPIO0A13 */ {PA_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT13},
|
||
|
|
/*494 AP_GPIO0A14 */ {PA_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT14},
|
||
|
|
/*495 AP_GPIO0A15 */ {PD_PMUX0_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT15},
|
||
|
|
/*496 AP_GPIO0A16 */ {PD_PMUX0_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT16},
|
||
|
|
/*497 AP_GPIO0A17 */ {PD_PMUX0_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT17},
|
||
|
|
/*498 AP_GPIO0A18 */ {PD_PMUX0_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT18},
|
||
|
|
/*499 AP_GPIO0A19 */ {PD_PMUX0_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT19},
|
||
|
|
/*500 AP_GPIO0A20 */ {PD_PMUX0_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT20},
|
||
|
|
/*501 AP_GPIO0A21 */ {PD_PMUX0_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT21},
|
||
|
|
/*502 AP_GPIO0A22 */ {PD_PMUX0_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT22},
|
||
|
|
/*503 AP_GPIO0A23 */ {PD_PMUX0_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT23},
|
||
|
|
/*504 AP_GPIO0A24 */ {PB_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT24},
|
||
|
|
/*505 AP_GPIO0A25 */ {PB_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT25},
|
||
|
|
/*506 AP_GPIO0A26 */ {PB_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT26},
|
||
|
|
/*507 AP_GPIO0A27 */ {PB_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT27},
|
||
|
|
/*508 AP_GPIO0A28 */ {PB_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT28},
|
||
|
|
/*509 AP_GPIO0A29 */ {PB_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT29},
|
||
|
|
/*510 AP_GPIO0A30 */ {PC_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT30},
|
||
|
|
/*511 AP_GPIO0A31 */ {PC_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT31}
|
||
|
|
};
|
||
|
|
|
||
|
|
const tUcpGpioRegTable_t infRegPort0AP_B[] = {
|
||
|
|
/*448 AP_GPIO0B0 */ {PC_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT0},
|
||
|
|
/*449 AP_GPIO0B1 */ {PC_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT1},
|
||
|
|
/*450 AP_GPIO0B2 */ {PA_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT2},
|
||
|
|
/*451 AP_GPIO0B3 */ {PC_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT3},
|
||
|
|
/*452 AP_GPIO0B4 */ {PC_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT4},
|
||
|
|
/*453 AP_GPIO0B5 */ {PC_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT5},
|
||
|
|
/*454 AP_GPIO0B6 */ {PC_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT6},
|
||
|
|
/*455 AP_GPIO0B7 */ {PC_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT7},
|
||
|
|
/*456 AP_GPIO0B8 */ {PC_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT8},
|
||
|
|
/*457 AP_GPIO0B9 */ {PC_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT9},
|
||
|
|
/*458 AP_GPIO0B10 */ {PC_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT10},
|
||
|
|
/*459 AP_GPIO0B11 */ {PC_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT11},
|
||
|
|
/*460 AP_GPIO0B12 */ {PC_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT12},
|
||
|
|
/*461 AP_GPIO0B13 */ {PD_PMUX0_REG, ( BIT0), (BIT0 | BIT1), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT13},
|
||
|
|
/*462 AP_GPIO0B14 */ {PD_PMUX0_REG, ( BIT2), (BIT2 | BIT3), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT14},
|
||
|
|
/*463 AP_GPIO0B15 */ {PD_PMUX0_REG, ( 0x00), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT15},
|
||
|
|
/*464 AP_GPIO0B16 */ {PD_PMUX0_REG, ( 0x00), (BIT6 | BIT7), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT16},
|
||
|
|
/*465 AP_GPIO0B17 */ {PD_PMUX0_REG, ( 0x00), (BIT8 | BIT9), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT17},
|
||
|
|
/*466 AP_GPIO0B18 */ {PD_PMUX0_REG, ( 0x00), (BIT10| BIT11), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT18},
|
||
|
|
/*467 AP_GPIO0B19 */ {PD_PMUX0_REG, ( 0x00), (BIT12| BIT13), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT19},
|
||
|
|
/*468 AP_GPIO0B20 */ {PD_PMUX0_REG, ( 0x00), (BIT14| BIT15), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT20},
|
||
|
|
/*469 AP_GPIO0B21 */ {PD_PMUX0_REG, ( 0x00), (BIT16| BIT17), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT21},
|
||
|
|
/*470 AP_GPIO0B22 */ {PD_PMUX0_REG, ( 0x00), (BIT18| BIT19), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT22},
|
||
|
|
/*471 AP_GPIO0B23 */ {PD_PMUX0_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT23},
|
||
|
|
/*472 AP_GPIO0B24 */ {PD_PMUX0_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT24},
|
||
|
|
/*473 AP_GPIO0B25 */ {PD_PMUX0_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT25},
|
||
|
|
/*474 AP_GPIO0B26 */ {PD_PMUX0_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT26},
|
||
|
|
/*475 AP_GPIO0B27 */ {PD_PMUX0_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT27},
|
||
|
|
/*476 AP_GPIO0B28 */ {PD_PMUX0_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT28},
|
||
|
|
/*477 AP_GPIO0B29 */ {PD_PMUX1_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT29},
|
||
|
|
/*478 AP_GPIO0B30 */ {PD_PMUX1_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT30},
|
||
|
|
/*479 AP_GPIO0B31 */ {PD_PMUX1_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT31}
|
||
|
|
};
|
||
|
|
|
||
|
|
const tUcpGpioRegTable_t infRegPort1CP_A[] = {
|
||
|
|
/*433 CP_GPIO1A0 */ {PD_PMUX1_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT0},
|
||
|
|
/*434 CP_GPIO1A1 */ {PD_PMUX1_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT1},
|
||
|
|
/*435 CP_GPIO1A2 */ {PD_PMUX1_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT2},
|
||
|
|
/*436 CP_GPIO1A3 */ {PE_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT3},
|
||
|
|
/*437 CP_GPIO1A4 */ {PE_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT4},
|
||
|
|
/*438 CP_GPIO1A5 */ {PE_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT5},
|
||
|
|
/*439 CP_GPIO1A6 */ {PE_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT6},
|
||
|
|
/*440 CP_GPIO1A7 */ {PE_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT7},
|
||
|
|
/*441 CP_GPIO1A8 */ {PE_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT8},
|
||
|
|
/*442 CP_GPIO1A9 */ {PE_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT9},
|
||
|
|
/*443 CP_GPIO1A10 */ {PE_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT10},
|
||
|
|
/*444 CP_GPIO1A11 */ {PE_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT11},
|
||
|
|
/*445 CP_GPIO1A12 */ {PE_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT12},
|
||
|
|
/*446 CP_GPIO1A13 */ {PE_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT13},
|
||
|
|
/*447 CP_GPIO1A14 */ {PE_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT14},
|
||
|
|
};
|
||
|
|
|
||
|
|
const tUcpGpioRegTable_t infRegPort1CP_B[] = {
|
||
|
|
/*401 CP_GPIO1B0 */ {LVDS_PMUX0_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT0},
|
||
|
|
/*402 CP_GPIO1B1 */ {LVDS_PMUX0_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT1},
|
||
|
|
/*403 CP_GPIO1B2 */ {LVDS_PMUX0_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT2},
|
||
|
|
/*404 CP_GPIO1B3 */ {LVDS_PMUX0_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT3},
|
||
|
|
/*405 CP_GPIO1B4 */ {LVDS_PMUX0_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT4},
|
||
|
|
/*406 CP_GPIO1B5 */ {LVDS_PMUX0_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT5},
|
||
|
|
/*407 CP_GPIO1B6 */ {LVDS_PMUX0_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT6},
|
||
|
|
/*408 CP_GPIO1B7 */ {LVDS_PMUX0_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT7},
|
||
|
|
/*409 CP_GPIO1B8 */ {LVDS_PMUX0_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT8},
|
||
|
|
/*410 CP_GPIO1B9 */ {LVDS_PMUX0_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT9},
|
||
|
|
/*411 CP_GPIO1B10 */ {LVDS_PMUX0_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT10},
|
||
|
|
/*412 CP_GPIO1B11 */ {LVDS_PMUX0_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT11},
|
||
|
|
/*413 CP_GPIO1B12 */ {LVDS_PMUX0_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT12},
|
||
|
|
/*414 CP_GPIO1B13 */ {LVDS_PMUX0_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT13},
|
||
|
|
/*415 CP_GPIO1B14 */ {LVDS_PMUX0_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT14},
|
||
|
|
/*416 CP_GPIO1B15 */ {LVDS_PMUX0_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT15},
|
||
|
|
/*417 CP_GPIO1B16 */ {LVDS_PMUX1_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT16},
|
||
|
|
/*418 CP_GPIO1B17 */ {LVDS_PMUX1_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT17},
|
||
|
|
/*419 CP_GPIO1B18 */ {LVDS_PMUX1_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT18},
|
||
|
|
/*420 CP_GPIO1B19 */ {LVDS_PMUX1_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT19},
|
||
|
|
/*421 CP_GPIO1B20 */ {LVDS_PMUX1_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT20},
|
||
|
|
/*422 CP_GPIO1B21 */ {LVDS_PMUX1_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT21},
|
||
|
|
/*423 CP_GPIO1B22 */ {LVDS_PMUX1_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT22},
|
||
|
|
/*424 CP_GPIO1B23 */ {LVDS_PMUX1_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT23},
|
||
|
|
/*425 CP_GPIO1B24 */ {LVDS_PMUX1_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT24},
|
||
|
|
/*426 CP_GPIO1B25 */ {LVDS_PMUX1_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT25},
|
||
|
|
/*427 CP_GPIO1B26 */ {LVDS_PMUX1_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT26},
|
||
|
|
/*428 CP_GPIO1B27 */ {LVDS_PMUX1_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT27},
|
||
|
|
/*429 CP_GPIO1B28 */ {LVDS_PMUX1_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT28},
|
||
|
|
/*430 CP_GPIO1B29 */ {LVDS_PMUX1_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT29},
|
||
|
|
/*431 CP_GPIO1B30 */ {LVDS_PMUX1_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT30},
|
||
|
|
/*432 CP_GPIO1B31 */ {LVDS_PMUX1_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT31}
|
||
|
|
};
|
||
|
|
|
||
|
|
const tUcpGpioRegTable_t *pUcpGpioTable[] = {infRegPort0AP_A, infRegPort0AP_B, infRegPort1CP_A, infRegPort1CP_B};
|
||
|
|
tGpioInfRegTable infRegTable[GPIO_INDEX_MAX];
|
||
|
|
enum {
|
||
|
|
TR_IND_TX_TRX, TR_IND_TX_RF, TR_IND_TX_SW,
|
||
|
|
TR_IND_RX_TRX, TR_IND_RX_RF, TR_IND_RX_SW,
|
||
|
|
TR_IND_ORX_TRX, TR_IND_ORX_RF, TR_IND_ORX_SW,
|
||
|
|
TR_IND_TRIG
|
||
|
|
};
|
||
|
|
static uint32_t trAnd[10][4], trXor[10][4];
|
||
|
|
|
||
|
|
static void ucp_jesd_gpioCfgInf2CSU (ucp_jesd_gpio_t *gpio, uint32_t bit2csuAddr)
|
||
|
|
{
|
||
|
|
uint32_t bit, enValue;
|
||
|
|
|
||
|
|
bit = 0;
|
||
|
|
enValue = 0;
|
||
|
|
|
||
|
|
// port 0~3: AP_GPIO0A、AP_GPIO0B、CP_GPIO0A、CP_GPIO0B
|
||
|
|
if (gpio->enableLevel)
|
||
|
|
{
|
||
|
|
bit |= (1 << gpio->pin);
|
||
|
|
if (UCP_JESD_TRX_GPIO_VALID_HIGH == gpio->enableLevel)
|
||
|
|
{
|
||
|
|
enValue |= (1 << gpio->pin);
|
||
|
|
}
|
||
|
|
|
||
|
|
ucp_reg32_or_write(bit2csuAddr + gpio->port*4, bit);
|
||
|
|
ucp_reg32_or_write(bit2csuAddr + gpio->port*4 + 16, enValue);
|
||
|
|
}
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ucp_jesd_tr_on (uint8_t trIndex)
|
||
|
|
{
|
||
|
|
if (trAnd[trIndex][0])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO0_SWPORTA_DR, trAnd[trIndex][0]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][1])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO0_SWPORTB_DR, trAnd[trIndex][1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][2])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO1_SWPORTA_DR, trAnd[trIndex][2]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][3])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO1_SWPORTB_DR, trAnd[trIndex][3]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][0])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO0_SWPORTA_DR, trXor[trIndex][0]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][1])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO0_SWPORTB_DR, trXor[trIndex][1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][2])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO1_SWPORTA_DR, trXor[trIndex][2]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][3])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO1_SWPORTB_DR, trXor[trIndex][3]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ucp_jesd_tr_off (uint8_t trIndex)
|
||
|
|
{
|
||
|
|
if (trAnd[trIndex][0])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO0_SWPORTA_DR, trAnd[trIndex][0]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][1])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO0_SWPORTB_DR, trAnd[trIndex][1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][2])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO1_SWPORTA_DR, trAnd[trIndex][2]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trAnd[trIndex][3])
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(GPIO1_SWPORTB_DR, trAnd[trIndex][3]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][0])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO0_SWPORTA_DR, trXor[trIndex][0]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][1])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO0_SWPORTB_DR, trXor[trIndex][1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][2])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO1_SWPORTA_DR, trXor[trIndex][2]);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trXor[trIndex][3])
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(GPIO1_SWPORTB_DR, trXor[trIndex][3]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
ucp_jesd_TrxGpioCfg_t ucp_jesd_gpioInit (const char *trxGpioConfigFile, uint16_t enLog)
|
||
|
|
{
|
||
|
|
ucp_jesd_TrxGpioCfg_t trxGpioCfg;
|
||
|
|
uint32_t i, config[36];
|
||
|
|
|
||
|
|
ucp_reg32_write(GPIO_VERSION2UCP_ADDR, 0);
|
||
|
|
ucp_reg32_write(GPIO_ULDELAY2UCP_ADDR, 0);
|
||
|
|
ucp_reg32_write(GPIO_DLDELAY2UCP_ADDR, 0);
|
||
|
|
|
||
|
|
for (i = 0;i < 80;i++)
|
||
|
|
{
|
||
|
|
ucp_reg32_write(GPIO_TRIGBIT2UCP_ADDR + 4*i, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
memset(infRegTable, 0, sizeof(infRegTable));
|
||
|
|
memset(trAnd, 0, sizeof(trAnd));
|
||
|
|
memset(trXor, 0, sizeof(trXor));
|
||
|
|
|
||
|
|
trxGpioCfg = ucp_GetGpioConfig(trxGpioConfigFile);
|
||
|
|
if (enLog)
|
||
|
|
{
|
||
|
|
ucp_printGpioConfigStruct(trxGpioCfg);
|
||
|
|
}
|
||
|
|
|
||
|
|
ucp_reg32_write(GPIO_PRE_DB_CLK_CFG_REG, 0x527000);
|
||
|
|
ucp_reg32_write(GPIO_DB_CLK_CFG_REG, 0x527000);
|
||
|
|
ucp_reg32_write(RFC_CLK_CFG_REG, 0x521000);
|
||
|
|
//------------------------- CONFIG RF tx/rx/orx GPIO -------------------------
|
||
|
|
for (i = 0;i < trxGpioCfg.maxCh;i++)
|
||
|
|
{
|
||
|
|
config[0 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.trx.enableLevel);
|
||
|
|
config[1 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.rf.enableLevel);
|
||
|
|
config[2 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.sw.enableLevel);
|
||
|
|
|
||
|
|
config[3 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.trx.enableLevel);
|
||
|
|
config[4 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.rf.enableLevel);
|
||
|
|
config[5 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.sw.enableLevel);
|
||
|
|
|
||
|
|
config[6 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.trx.enableLevel);
|
||
|
|
config[7 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.rf.enableLevel);
|
||
|
|
config[8 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.sw.enableLevel);
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0;i < trxGpioCfg.maxCh;i++)
|
||
|
|
{
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_TRX_TX1 + i, GPIO_DIR_OUT, config[0 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.trx.port, trxGpioCfg.ch[i].tx.trx.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_RF_TX1 + i, GPIO_DIR_OUT, config[1 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.rf.port, trxGpioCfg.ch[i].tx.rf.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_SW_TX1 + i, GPIO_DIR_OUT, config[2 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.sw.port, trxGpioCfg.ch[i].tx.sw.pin));
|
||
|
|
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_TRX_RX1 + i, GPIO_DIR_OUT, config[3 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.trx.port, trxGpioCfg.ch[i].rx.trx.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_RF_RX1 + i, GPIO_DIR_OUT, config[4 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.rf.port, trxGpioCfg.ch[i].rx.rf.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_SW_RX1 + i, GPIO_DIR_OUT, config[5 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.sw.port, trxGpioCfg.ch[i].rx.sw.pin));
|
||
|
|
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_TRX_ORX1 + i, GPIO_DIR_OUT, config[6 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.trx.port, trxGpioCfg.ch[i].orx.trx.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_RF_ORX1 + i, GPIO_DIR_OUT, config[7 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.rf.port, trxGpioCfg.ch[i].orx.rf.pin));
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_SW_ORX1 + i, GPIO_DIR_OUT, config[8 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.sw.port, trxGpioCfg.ch[i].orx.sw.pin));
|
||
|
|
}
|
||
|
|
|
||
|
|
ucp_jesd_gpioConfig(GPIO_INDEX_TRIGER,GPIO_DIR_OUT,trxGpioCfg.triger.enableLevel,UCP_GPIO(trxGpioCfg.triger.port,trxGpioCfg.triger.pin));
|
||
|
|
|
||
|
|
//------------------------- CONFIG share memry -------------------------
|
||
|
|
ucp_reg32_write(GPIO_VERSION2UCP_ADDR, trxGpioCfg.version);
|
||
|
|
ucp_reg32_write(GPIO_ULDELAY2UCP_ADDR, trxGpioCfg.uldelay);
|
||
|
|
ucp_reg32_write(GPIO_DLDELAY2UCP_ADDR, trxGpioCfg.dldelay);
|
||
|
|
|
||
|
|
for (i = 0;i < trxGpioCfg.maxCh;i++)
|
||
|
|
{
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.trx, GPIO_TXTRXBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.rf, GPIO_TXRFBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.sw, GPIO_TXSWBIT2UCP_ADDR);
|
||
|
|
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.trx, GPIO_RXTRXBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.rf, GPIO_RXRFBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.sw, GPIO_RXSWBIT2UCP_ADDR);
|
||
|
|
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.trx, GPIO_ORXTRXBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.rf, GPIO_ORXRFBIT2UCP_ADDR);
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.sw, GPIO_ORXSWBIT2UCP_ADDR);
|
||
|
|
}
|
||
|
|
|
||
|
|
ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.triger, GPIO_TRIGBIT2UCP_ADDR);
|
||
|
|
|
||
|
|
for (i = 0;i < 4;i++)
|
||
|
|
{
|
||
|
|
trAnd[TR_IND_TX_TRX][i] = ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_TX_TRX][i] = ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_TX_RF][i] = ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_TX_RF][i] = ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_TX_SW][i] = ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_TX_SW][i] = ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
|
||
|
|
trAnd[TR_IND_RX_TRX][i] = ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_RX_TRX][i] = ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_RX_RF][i] = ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_RX_RF][i] = ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_RX_SW][i] = ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_RX_SW][i] = ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
|
||
|
|
trAnd[TR_IND_ORX_TRX][i] = ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_ORX_TRX][i] = ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_ORX_RF][i] = ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_ORX_RF][i] = ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trAnd[TR_IND_ORX_SW][i] = ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_ORX_SW][i] = ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
|
||
|
|
trAnd[TR_IND_TRIG][i] = ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
trXor[TR_IND_TRIG][i] = ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 16 + 4*i);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (enLog)
|
||
|
|
{
|
||
|
|
printf("VERSION: %d\n", ucp_reg32_read(GPIO_VERSION2UCP_ADDR));
|
||
|
|
printf("ULDELAY: %d\n", ucp_reg32_read(GPIO_ULDELAY2UCP_ADDR));
|
||
|
|
printf("DLDELAY: %d\n\n", ucp_reg32_read(GPIO_DLDELAY2UCP_ADDR));
|
||
|
|
|
||
|
|
for (i = 0;i < 10;i++)
|
||
|
|
{
|
||
|
|
printf("ADDR: %08X, BIT: %08X %08X %08X %08X\n", GPIO_TRIGBIT2UCP_ADDR + i*32,
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 0*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 1*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 2*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 3*4 + i*32));
|
||
|
|
printf("ADDR: %08X, VAILID: %08X %08X %08X %08X\n\n", GPIO_TRIGBIT2UCP_ADDR + 4*4 + i*32,
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 5*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 6*4 + i*32),
|
||
|
|
ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 7*4 + i*32));
|
||
|
|
}
|
||
|
|
|
||
|
|
printf("Trig: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_TRIG][0], trAnd[TR_IND_TRIG][1], trAnd[TR_IND_TRIG][2], trAnd[TR_IND_TRIG][3],
|
||
|
|
trXor[TR_IND_TRIG][0], trXor[TR_IND_TRIG][1], trXor[TR_IND_TRIG][2], trXor[TR_IND_TRIG][3]);
|
||
|
|
printf("TxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_TX_TRX][0], trAnd[TR_IND_TX_TRX][1], trAnd[TR_IND_TX_TRX][2], trAnd[TR_IND_TX_TRX][3],
|
||
|
|
trXor[TR_IND_TX_TRX][0], trXor[TR_IND_TX_TRX][1], trXor[TR_IND_TX_TRX][2], trXor[TR_IND_TX_TRX][3]);
|
||
|
|
printf("TxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_TX_RF][0], trAnd[TR_IND_TX_RF][1], trAnd[TR_IND_TX_RF][2], trAnd[TR_IND_TX_RF][3],
|
||
|
|
trXor[TR_IND_TX_RF][0], trXor[TR_IND_TX_RF][1], trXor[TR_IND_TX_RF][2], trXor[TR_IND_TX_RF][3]);
|
||
|
|
printf("TxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_TX_SW][0], trAnd[TR_IND_TX_SW][1], trAnd[TR_IND_TX_SW][2], trAnd[TR_IND_TX_SW][3],
|
||
|
|
trXor[TR_IND_TX_SW][0], trXor[TR_IND_TX_SW][1], trXor[TR_IND_TX_SW][2], trXor[TR_IND_TX_SW][3]);
|
||
|
|
|
||
|
|
printf("RxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_RX_TRX][0], trAnd[TR_IND_RX_TRX][1], trAnd[TR_IND_RX_TRX][2], trAnd[TR_IND_RX_TRX][3],
|
||
|
|
trXor[TR_IND_RX_TRX][0], trXor[TR_IND_RX_TRX][1], trXor[TR_IND_RX_TRX][2], trXor[TR_IND_RX_TRX][3]);
|
||
|
|
printf("RxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_RX_RF][0], trAnd[TR_IND_RX_RF][1], trAnd[TR_IND_RX_RF][2], trAnd[TR_IND_RX_RF][3],
|
||
|
|
trXor[TR_IND_RX_RF][0], trXor[TR_IND_RX_RF][1], trXor[TR_IND_RX_RF][2], trXor[TR_IND_RX_RF][3]);
|
||
|
|
printf("RxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_RX_SW][0], trAnd[TR_IND_RX_SW][1], trAnd[TR_IND_RX_SW][2], trAnd[TR_IND_RX_SW][3],
|
||
|
|
trXor[TR_IND_RX_SW][0], trXor[TR_IND_RX_SW][1], trXor[TR_IND_RX_SW][2], trXor[TR_IND_RX_SW][3]);
|
||
|
|
|
||
|
|
printf("OrxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_ORX_TRX][0], trAnd[TR_IND_ORX_TRX][1], trAnd[TR_IND_ORX_TRX][2], trAnd[TR_IND_ORX_TRX][3],
|
||
|
|
trXor[TR_IND_ORX_TRX][0], trXor[TR_IND_ORX_TRX][1], trXor[TR_IND_ORX_TRX][2], trXor[TR_IND_ORX_TRX][3]);
|
||
|
|
printf("OrxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n",
|
||
|
|
trAnd[TR_IND_ORX_RF][0], trAnd[TR_IND_ORX_RF][1], trAnd[TR_IND_ORX_RF][2], trAnd[TR_IND_ORX_RF][3],
|
||
|
|
trXor[TR_IND_ORX_RF][0], trXor[TR_IND_ORX_RF][1], trXor[TR_IND_ORX_RF][2], trXor[TR_IND_ORX_RF][3]);
|
||
|
|
|
||
|
|
printf("OrxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n\n",
|
||
|
|
trAnd[TR_IND_ORX_SW][0], trAnd[TR_IND_ORX_SW][1], trAnd[TR_IND_ORX_SW][2], trAnd[TR_IND_ORX_SW][3],
|
||
|
|
trXor[TR_IND_ORX_SW][0], trXor[TR_IND_ORX_SW][1], trXor[TR_IND_ORX_SW][2], trXor[TR_IND_ORX_SW][3]);
|
||
|
|
}
|
||
|
|
//------------------------- CONFIG RF tx/rx/orx GPIO END -------------------------
|
||
|
|
|
||
|
|
return trxGpioCfg;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ucp_jesd_gpioConfig (const int pinIdex, uint8_t dir, uint8_t enable, tUcpGpioRegTable_t *gpio)
|
||
|
|
{
|
||
|
|
if (pinIdex < GPIO_INDEX_MAX)
|
||
|
|
{
|
||
|
|
infRegTable[pinIdex].index = pinIdex;
|
||
|
|
infRegTable[pinIdex].enable = enable;
|
||
|
|
infRegTable[pinIdex].dir = dir;
|
||
|
|
infRegTable[pinIdex].value = 0;
|
||
|
|
infRegTable[pinIdex].gpio = gpio;
|
||
|
|
|
||
|
|
if (infRegTable[pinIdex].enable)
|
||
|
|
{
|
||
|
|
infRegTable[pinIdex].value = (UCP_JESD_TRX_GPIO_VALID_HIGH == infRegTable[pinIdex].enable) ? 1 : 0;
|
||
|
|
|
||
|
|
ucp_reg32_and_write(infRegTable[pinIdex].gpio->pinMuxReg, infRegTable[pinIdex].gpio->muxMask);
|
||
|
|
ucp_reg32_or_write(infRegTable[pinIdex].gpio->pinMuxReg, infRegTable[pinIdex].gpio->muxValue);
|
||
|
|
|
||
|
|
ucp_jesd_gpioSetDir(infRegTable[pinIdex].index, infRegTable[pinIdex].dir);
|
||
|
|
if (GPIO_DIR_OUT == infRegTable[pinIdex].dir)
|
||
|
|
{
|
||
|
|
ucp_jesd_gpioSet(infRegTable[pinIdex].index, infRegTable[pinIdex].value);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__);
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int ucp_jesd_gpioSetDir(const int pinIdex, eGpioDir dir)
|
||
|
|
{
|
||
|
|
if (pinIdex < GPIO_INDEX_MAX)
|
||
|
|
{
|
||
|
|
if (infRegTable[pinIdex].enable)
|
||
|
|
{
|
||
|
|
if (GPIO_DIR_IN == dir )
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
}
|
||
|
|
else if (GPIO_DIR_OUT == dir )
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__);
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
eGpioDir ucp_jesd_gpioGetDir(const int pinIdex)
|
||
|
|
{
|
||
|
|
uint32_t dir;
|
||
|
|
|
||
|
|
if ((pinIdex < GPIO_INDEX_MAX) && infRegTable[pinIdex].enable)
|
||
|
|
{
|
||
|
|
dir = ucp_reg32_and_read(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
return (dir ? GPIO_DIR_IN : GPIO_DIR_OUT);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int ucp_jesd_gpioSet(const int pinIdex, int value)
|
||
|
|
{
|
||
|
|
if (pinIdex < GPIO_INDEX_MAX)
|
||
|
|
{
|
||
|
|
if (infRegTable[pinIdex].enable)
|
||
|
|
{
|
||
|
|
if (0 == value)
|
||
|
|
{
|
||
|
|
ucp_reg32_and_write(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ucp_reg32_or_write(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__);
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int ucp_jesd_gpioGet(const int pinIdex)
|
||
|
|
{
|
||
|
|
uint32_t dir;
|
||
|
|
|
||
|
|
if ((pinIdex < GPIO_INDEX_MAX) && infRegTable[pinIdex].enable)
|
||
|
|
{
|
||
|
|
dir = ucp_reg32_and_read(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask);
|
||
|
|
return (dir ? 1 : 0);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_tx (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_RF);
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_TRX);
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_SW);
|
||
|
|
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_SW);
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_RF);
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_TRX);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_rx (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_TRX);
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_RF);
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_SW);
|
||
|
|
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_SW);
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_RF);
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_TRX);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_on (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_SW);
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_RF);
|
||
|
|
ucp_jesd_tr_on(TR_IND_RX_TRX);
|
||
|
|
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_TRX);
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_RF);
|
||
|
|
ucp_jesd_tr_on(TR_IND_TX_SW);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_off (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_TRX);
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_RF);
|
||
|
|
ucp_jesd_tr_off(TR_IND_TX_SW);
|
||
|
|
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_SW);
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_RF);
|
||
|
|
ucp_jesd_tr_off(TR_IND_RX_TRX);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_orxOn (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_on(TR_IND_ORX_SW);
|
||
|
|
ucp_jesd_tr_on(TR_IND_ORX_RF);
|
||
|
|
ucp_jesd_tr_on(TR_IND_ORX_TRX);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_orxOff (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_off(TR_IND_ORX_TRX);
|
||
|
|
ucp_jesd_tr_off(TR_IND_ORX_RF);
|
||
|
|
ucp_jesd_tr_off(TR_IND_ORX_SW);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_trigOn (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_on(TR_IND_TRIG);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ucp_jesd_gpio_trigOff (void)
|
||
|
|
{
|
||
|
|
ucp_jesd_tr_off(TR_IND_TRIG);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|