327 lines
11 KiB
C
327 lines
11 KiB
C
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/*==============================================================================
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* Copyright (c) 2011~2012, CPIT. All Rights Reserved.
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*
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* MODULE: STC模块驱动
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*
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* FILENAME: stc.h
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*
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* DESCRIPTION: Source Code of STC Driver
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*
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* Current Version: 1.0
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*
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* HISTORY:
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* Date CR No Person Description
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* ---------- ------------ ------ -------------
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* 2022-05-21 Li Weihua Initial version.
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==============================================================================*/
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#ifndef __STC_DRV_H__
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#define __STC_DRV_H__
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#include "typedef.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if 0
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#pragma align(1) /* set tight packing */
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#pragma pack(1)
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#endif
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/*==============================================================================
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Includes and Public Data Declarations
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==============================================================================*/
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/* 包含系统文件以及定义公用数据文件 */
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/*==============================================================================
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Include Files
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==============================================================================*/
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/* 包含本地文件 */
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/*==============================================================================
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Constant / Define Declarations
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==============================================================================*/
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/* 常量定义，并对所定义的常量进行说明 */
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/*==============================================================================
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Global Constant Data Declarations
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==============================================================================*/
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/*==============================================================================
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Macro Definitions
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==============================================================================*/
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/* 宏定义，并对其进行简要说明 */
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#define STC_REG_BASE_ADDR (0x08568000) //STC模块基地址
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#define STC_REG_LEN (0x08000)
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#define STC_LTBG_REG_OFFSET 0x1005
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#define ECS_SUBCTRL_REG_BASE_ADDR (0x08460000) //ECS_SUBCTRL模块基地址
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#define ECS_SUBCTRL_REG_LEN (0x10000)
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#define ECS_CRG_REG_BASE_ADDR (0x08430000) //ECS_CRG模块基地址
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#define ECS_CRG_REG_LEN (0x10000)
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#define AP_GPIO_PINMUX_REG_BASE_ADDR (0x04450000) //AP_GPIO基地址:0x04450000,AP_GPIO_PINMUX模块基地址0x04458000
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#define AP_GPIO_REG_LEN (0x8000)
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#define AP_GPIO_PINMUX_REG_LEN (0x10000)
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#define GMAC0_REG_BASE_ADDR (0x01a40000) //GMAC0模块基地址
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#define GMAC0_TOD_REG (0xB08)
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#define GMAC0_REG_LEN (0x10000)
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#define TMAC_REG_BASE_ADDR (0x09090000) //TMAC模块基地址
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#define TMAC0_TOD_REG (0xD08)
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#define TMAC_REG_LEN (0x100000)
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#define STC_DEV_NAME "/dev/stc_dev"
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#define STC_MODULE_MAGIC 'g'
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#define STC_INT_CFG _IOWR(STC_MODULE_MAGIC, 0x01, uint32_t)
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#define SECOND2NS 1000000000.000001
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#define DEFAULT_RT_VALUE 0x3B9ACA0000000000UL
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#define DEFAULT_RT_HALF 0x1DCD650000000000UL
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#define KERNEL2USER_DELAY 9320 //9320ns
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#define STC_LOCK_CNT 15
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#define SNIFFER_LOCK_THRESHOLD 20 //0x1400000000UL //20ns
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#define SFN_BASE_ADDR 0x0A4f2220UL //0x0A4D7220UL
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#define SNIFFER_BASE_ADDR 0x0A4f2140UL
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#define SHARE_MEM_BASE_ADDR 0x009D00000UL
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#define SHARE_MEM_LEN 0x000800000UL
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#define BIT0 (0x00000001)
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#define BIT1 (0x00000002)
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#define BIT2 (0x00000004)
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#define BIT3 (0x00000008)
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#define BIT4 (0x00000010)
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#define BIT5 (0x00000020)
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#define BIT6 (0x00000040)
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#define BIT7 (0x00000080)
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#define BIT8 (0x00000100)
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#define BIT9 (0x00000200)
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#define BIT10 (0x00000400)
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#define BIT11 (0x00000800)
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#define BIT12 (0x00001000)
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#define BIT13 (0x00002000)
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#define BIT14 (0x00004000)
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#define BIT15 (0x00008000)
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#define BIT16 (0x00010000)
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#define BIT17 (0x00020000)
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#define BIT18 (0x00040000)
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#define BIT19 (0x00080000)
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#define BIT20 (0x00100000)
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#define BIT21 (0x00200000)
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#define BIT22 (0x00400000)
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#define BIT23 (0x00800000)
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#define BIT24 (0x01000000)
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#define BIT25 (0x02000000)
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#define BIT26 (0x04000000)
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#define BIT27 (0x08000000)
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#define BIT28 (0x10000000)
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#define BIT29 (0x20000000)
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#define BIT30 (0x40000000)
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#define BIT31 (0x80000000)
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typedef volatile uint32_t vuint32_t;
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typedef volatile uint8_t vuint8_t;
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/*==============================================================================
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Type Declarations
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==============================================================================*/
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/* 类型定义，struct、enum等，对每种类型定义作简要说明，如果是重要数据结构，要详细
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说明 */
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/*STC 寄存器*/
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typedef struct
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{
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vuint32_t tod_reg_config; /*0*/
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vuint32_t tod_reg_int_status; /*4*/
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vuint32_t tod_reg_irq_en; /*0x8*/
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vuint32_t tod_clr; /*0xc*/
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vuint8_t reserve0[0x30]; /*0x10-0x40*/
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vuint32_t tod_reg_nf; /*0x40*/
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vuint32_t tod_reg_hscc; /*0x44*/
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vuint32_t tod_reg_nsf_init_lo; /*0x48*/
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vuint32_t tod_reg_nsf_init_hi; /*0x4c*/
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vuint32_t tod_reg_ft_lo; /*0x50*/
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vuint32_t tod_reg_ft_hi; /*0x54*/
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vuint32_t tod_reg_rt_lo; /*0x58*/
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vuint32_t tod_reg_rt_hi; /*0x5c*/
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vuint32_t tod_reg_su_lo; /*0x60*/ //TOD second lo
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vuint32_t tod_reg_su_hi; /*0x64*/ //TOD second hi
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vuint32_t tod_reg_nsf_1pps_lo; /*0x68*/
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vuint32_t tod_reg_nsf_1pps_hi; /*0x6c*/
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vuint32_t tod_reg_tod_lo; /*0x70*/
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vuint32_t tod_reg_tod_mi; /*0x74*/
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vuint32_t tod_reg_tod_hi; /*0x78*/
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vuint32_t reserve1; /*0x7c*/
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vuint32_t ltbg0_reg_r; /*0x80*/
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vuint32_t ltbg0_reg_n; /*0x84*/
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vuint32_t ltbg0_reg_n1; /*0x88*/
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vuint8_t reserve2[116]; /*0x8c-100*/
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vuint32_t ctw_reg_timer0_0; /*0x100*/
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vuint32_t ctw_reg_timer0_1; /*0x104*/
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vuint32_t ctw_reg_timer0_2; /*0x108*/
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vuint32_t ctw_reg_timer0_3; /*0x10c*/
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vuint32_t ctw_reg_timer1_0; /*0x110*/
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vuint32_t ctw_reg_timer1_1; /*0x114*/
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vuint32_t ctw_reg_timer1_2; /*0x118*/
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vuint32_t ctw_reg_timer1_3; /*0x11c*/
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vuint32_t ctw_reg_irq0_0; /*0x120*/
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vuint32_t ctw_reg_irq0_1; /*0x124*/
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vuint32_t ctw_reg_irq0_2; /*0x128*/
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vuint32_t ctw_reg_irq0_3; /*0x12c*/
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vuint32_t ctw_reg_irq1_0; /*0x130*/
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vuint32_t ctw_reg_irq1_1; /*0x134*/
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vuint32_t ctw_reg_irq1_2; /*0x138*/
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vuint32_t ctw_reg_irq1_3; /*0x13c*/
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vuint32_t ctw_reg_status; /*0x140*/
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}arm_stc_regs;
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#if 0
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/*输出到PAD的1PPS信号: jecs_subctrl_reg33:gnss_pps_out*/
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typedef enum
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{
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GMAC0_1PPS_OUT = 0, /* gmac0 */
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GMAC1_1PPS_OUT, /* gmac1 */
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RESERVED0_1PPS_OUT, /* Reserved*/
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CPRI_GMAC_1PPS_OUT = 3, /* cpri gmac */
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TMAC_1PPS_OUT, /* tmac */
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STC_1PPS_OUT, /* stc产生的1pps */
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TOD_1PPS_OUT, /* stc产生的1pps */
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RESERVED_1PPS_OUT /* Reserved*/
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} pp1s_output_e;
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#endif
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typedef enum
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{
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ZERO_FLAG = 0, /*0标志*/
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TRUE_FLAG /*1 标志*/
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}clk_flag_e;
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typedef enum
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{
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CLK_DISABLE = 0, /* clock unuseable status */
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CLK_WARM_UP = 1, /* warm up status */
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CLK_TRACKING, /* tracking status */
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CLK_HOLD_OVER /* hold over status */
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}clk_sync_state_e;
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/*前传接口类型*/
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typedef enum
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{
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UCP4008_JESD = 0, /* JESD */
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UCP4008_CPRI, /* CPRI */
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UCP4008_ECPRI, /* eCPRI */
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RESERVED_FH /* Reserved*/
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} front_hual_e;
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/*恢复时钟类型*/
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typedef enum
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{
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SYNC_ETH_CLK = 25000000, /* 外部同步以太网时钟输入 25M*N*/
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CLK_GE_CDR = 125000000, /* 千兆以太网RX时钟，外部输入125MHz */
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CLK_CPRI_CDR = 122880000, /* 内部CPRI SERDES恢复时钟输出122.88MHZ*/
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CLK_ECPRI_CDR = 156250000, /* 内部eCPRI SERDES恢复时钟输出156.25MHz */
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CLK_TMAC_CDR = 156250000 /* 内部TMAC SERDES(PT SERDES)恢复时钟156.25MHz */
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} recovery_clk_e;
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typedef struct
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{
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double integral; //累计偏差(积分)
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double magic_num; //输出系数 PCLK的周期
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double p_ratio; //比例系数
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double i_ratio; //积分系数
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uint8_t status; //是否同步 0:未同步，1同步
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uint8_t tracking_cnt;
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uint16_t holdover_cnt;
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uint32_t disable_cnt;
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}pi_struct_s;
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/*typedef struct
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{
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pi_struct_s
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}adjust_struct_s;*/
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typedef struct
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{
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pp1s_soure_e pp1s_src; //1pps源
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//front_hual_e fh_interface; //前传接口类型
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hscc_dump_soure_e hscc_dump_src;
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//recovery_clk_e recovery_clk;
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uint32_t synce_flag; //是否有synce时钟 1：有，0：没有
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uint32_t synce_clk; //synce时钟频率Hz
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uint32_t cal_period; //频率校准的频率（每秒校准次数）,单位：Hz
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uint32_t p_clk; //P_CLK_STC的频率值
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uint64_t default_ft; //默认的ft值
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double p_clk_period; //P_CLK_STC的周期值
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pi_struct_s freq; //频率校准
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pi_struct_s phase; //相位校准
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clk_sync_state_e state;
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uint32_t pesudo_flag;
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}stc_state_s;
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typedef struct
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{
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uint32_t common_alarm;
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uint32_t hold_over_time;
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clk_sync_state_e status;
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}clock_module_status_s;
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/*错误返回码*/
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#define STC_OK (0) /* 函数调用返回成功 */
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#define PARAMETER1_ERROR (-1)
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#define PARAMETER2_ERROR (-2)
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#define PARAMETER3_ERROR (-3)
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#define PARAMETER4_ERROR (-4)
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#define PARAMETER5_ERROR (-5)
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#define LOGIC_ERROR1 (-6)
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#define LOGIC_ERROR2 (-7)
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#define LOGIC_ERROR3 (-8)
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#define LOGIC_ERROR4 (-9)
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#define LOGIC_ERROR5 (-10)
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#define LOGIC_ERROR6 (-11)
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#define LOGIC_ERROR7 (-12)
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#define LOGIC_ERROR8 (-13)
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#define LOGIC_ERROR9 (-14)
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#define LOGIC_ERROR10 (-15)
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#define LOGIC_ERROR11 (-16)
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#define LOGIC_ERROR12 (-17)
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#define LOGIC_ERROR13 (-18)
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/*==============================================================================
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Function Prototypes
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==============================================================================*/
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int32_t set_clk_mode(clk_flag_e pseudo_flag);
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int32_t get_clock_module_status(volatile clock_module_status_s* clk_module_status_ptr);
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stc_state_s* get_stc_state();
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arm_stc_regs * get_stc_reg_base();
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void set_su_reg(uint64_t value);
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void * get_ap_gpio_reg_base();
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#if 0
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#pragma align() /* restore default packing */
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#pragma pack()
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STC_DRV_H__ */
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