279 lines
23 KiB
C
279 lines
23 KiB
C
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#ifndef __TPCS_H__
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#define __TPCS_H__
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#define TPCS_PMA_MMD_BaseAddress 0x090a0000
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#define TPCS_PCS_MMD_BaseAddress 0x090d0000
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#define TPCS_AN_MMD_BaseAddress 0x09100000
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#define TPCS_VS_MMD1_BaseAddress 0x09130000
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//#define TPCS_PMA_MMD_BaseAddress 0x10000
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//#define TPCS_PCS_MMD_BaseAddress 0x30000
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//#define TPCS_AN_MMD_BaseAddress 0x70000
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//#define TPCS_VS_MMD1_BaseAddress 0x1e0000
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#define TPCS_SR_PMA_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x0 )
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#define TPCS_SR_PMA_STATUS1 (TPCS_PMA_MMD_BaseAddress + 4*0x1 )
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#define TPCS_SR_PMA_DEV_ID_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2 )
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#define TPCS_SR_PMA_DEV_ID_2 (TPCS_PMA_MMD_BaseAddress + 4*0x3 )
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#define TPCS_SR_PMA_SPD_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x4 )
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#define TPCS_SR_PMA_DEV_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0x5 )
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#define TPCS_SR_PMA_DEV_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0x6 )
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#define TPCS_SR_PMA_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x7 )
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#define TPCS_SR_PMA_STATUS2 (TPCS_PMA_MMD_BaseAddress + 4*0x8 )
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#define TPCS_SR_PMA_TX_DIS (TPCS_PMA_MMD_BaseAddress + 4*0x9 )
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#define TPCS_SR_PMA_RX_SIG_DET (TPCS_PMA_MMD_BaseAddress + 4*0xa )
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#define TPCS_SR_PMA_EXT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xb )
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#define TPCS_SR_PMA_EXT_ABL1 (TPCS_PMA_MMD_BaseAddress + 4*0xd )
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#define TPCS_SR_PMA_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0xe )
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#define TPCS_SR_PMA_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0xf )
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#define TPCS_SR_EEE_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x10 )
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#define TPCS_SR_PMA_EXT_ABL2 (TPCS_PMA_MMD_BaseAddress + 4*0x13 )
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#define TPCS_SR_PMA_KR_PMD_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x96 )
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#define TPCS_SR_PMA_KR_PMD_STS (TPCS_PMA_MMD_BaseAddress + 4*0x97 )
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#define TPCS_SR_PMA_KR_LP_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x98 )
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#define TPCS_SR_PMA_KR_LP_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x99 )
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#define TPCS_SR_PMA_KR_LD_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x9a )
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#define TPCS_SR_PMA_KR_LD_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x9b )
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#define TPCS_SR_PMA_KX_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xa0 )
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#define TPCS_SR_PMA_KX_STS (TPCS_PMA_MMD_BaseAddress + 4*0xa1 )
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#define TPCS_SR_PMA_KR_FEC_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xaa )
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#define TPCS_SR_PMA_KR_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xab )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xac )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xad )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xae )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xaf )
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#define TPCS_SR_PMA_RS_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xc8 )
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#define TPCS_SR_PMA_RS_FEC_STATUS (TPCS_PMA_MMD_BaseAddress + 4*0xc9 )
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#define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xca )
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#define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcb )
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#define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xcc )
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#define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcd )
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#define TPCS_SR_PMA_RS_FEC_LANE_MAP (TPCS_PMA_MMD_BaseAddress + 4*0xce )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd2 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd3 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd4 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd5 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd6 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd7 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd8 )
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#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd9 )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12c )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12d )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12e )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12f )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x130 )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x131 )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x132 )
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#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x133 )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bc )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bd )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2be )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2bf )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c0 )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c1 )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c2 )
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#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c3 )
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#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x44c )
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#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x44d )
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#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x44e )
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#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x44f )
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#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x4b0 )
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#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x4b1 )
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#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x4b2 )
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#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x4b3 )
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#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x514 )
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#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x515 )
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#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x516 )
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#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x517 )
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#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x578 )
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#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x579 )
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#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x57a )
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#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x57b )
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#define TPCS_SR_PMA_LNK_TRN_PAT (TPCS_PMA_MMD_BaseAddress + 4*0x5aa )
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#define TPCS_SR_PMA_LNK_TRN_PAT_LN1 (TPCS_PMA_MMD_BaseAddress + 4*0x5ab )
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#define TPCS_SR_PMA_LNK_TRN_PAT_LN2 (TPCS_PMA_MMD_BaseAddress + 4*0x5ac )
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#define TPCS_SR_PMA_LNK_TRN_PAT_LN3 (TPCS_PMA_MMD_BaseAddress + 4*0x5ad )
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#define TPCS_SR_PMA_KR_TST_PAT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x5dc )
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#define TPCS_SR_PMA_KR_TST_PAT_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5dd )
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#define TPCS_SR_PMA_KR_SQUARE_WAVE_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5e6 )
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#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x640 )
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#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x641 )
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#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x642 )
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#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x643 )
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#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x6a4 )
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#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x6a5 )
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#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x6a6 )
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#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x6a7 )
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#define TPCS_VR_PMA_DIG_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8000)
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#define TPCS_VR_PMA_KRTR_PRBS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8003)
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#define TPCS_VR_PMA_KRTR_PRBS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8004)
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#define TPCS_VR_PMA_KRTR_PRBS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x8005)
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#define TPCS_VR_PMA_KRTR_TIMER_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8006)
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#define TPCS_VR_PMA_KRTR_TIMER_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8007)
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#define TPCS_VR_PMA_DIG_STS (TPCS_PMA_MMD_BaseAddress + 4*0x8010)
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#define TPCS_VR_PMA_RX_LSTS (TPCS_PMA_MMD_BaseAddress + 4*0x8020)
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#define TPCS_VR_PMA_CWM00 (TPCS_PMA_MMD_BaseAddress + 4*0x80a3)
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#define TPCS_VR_PMA_CWM01 (TPCS_PMA_MMD_BaseAddress + 4*0x80a4)
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#define TPCS_VR_PMA_CWM02 (TPCS_PMA_MMD_BaseAddress + 4*0x80a5)
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#define TPCS_VR_PMA_CWM03 (TPCS_PMA_MMD_BaseAddress + 4*0x80a6)
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#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b0)
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#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b1)
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#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b2)
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#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b3)
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#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b4)
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#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b5)
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#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b6)
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#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b7)
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#define TPCS_VR_PMA_PHY_TX_EQ_STS0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b8)
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#define TPCS_VR_PMA_PHY_TX_EQ_STS1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b9)
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#define TPCS_VR_PMA_PHY_TX_EQ_STS2 (TPCS_PMA_MMD_BaseAddress + 4*0x80ba)
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#define TPCS_VR_PMA_PHY_TX_EQ_STS3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bb)
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#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80bc)
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#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80bd)
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#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80be)
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#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bf)
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#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c0)
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#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c1)
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#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c2)
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#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c3)
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#define TPCS_VR_PMA_PHY_RX_EQ_CEU0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c4)
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#define TPCS_VR_PMA_PHY_RX_EQ_CEU1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c5)
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#define TPCS_VR_PMA_PHY_RX_EQ_CEU2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c6)
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#define TPCS_VR_PMA_PHY_RX_EQ_CEU3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c7)
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#define TPCS_SR_PCS_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x0 )
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#define TPCS_SR_PCS_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x1 )
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#define TPCS_SR_PCS_DEV_ID1 (TPCS_PCS_MMD_BaseAddress + 4*0x2 )
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#define TPCS_SR_PCS_DEV_ID2 (TPCS_PCS_MMD_BaseAddress + 4*0x3 )
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#define TPCS_SR_PCS_SPD_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x4 )
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#define TPCS_SR_PCS_DEV_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0x5 )
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#define TPCS_SR_PCS_DEV_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0x6 )
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#define TPCS_SR_PCS_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x7 )
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#define TPCS_SR_PCS_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x8 )
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#define TPCS_SR_PCS_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0xe )
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#define TPCS_SR_PCS_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0xf )
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#define TPCS_SR_PCS_EEE_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x14 )
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#define TPCS_SR_PCS_EEE_WKERR (TPCS_PCS_MMD_BaseAddress + 4*0x16 )
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#define TPCS_SR_PCS_LSTS (TPCS_PCS_MMD_BaseAddress + 4*0x18 )
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#define TPCS_SR_PCS_BASER_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x20 )
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#define TPCS_SR_PCS_BASER_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x21 )
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#define TPCS_SR_PCS_TP_A0 (TPCS_PCS_MMD_BaseAddress + 4*0x22 )
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#define TPCS_SR_PCS_TP_A1 (TPCS_PCS_MMD_BaseAddress + 4*0x23 )
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#define TPCS_SR_PCS_TP_A2 (TPCS_PCS_MMD_BaseAddress + 4*0x24 )
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#define TPCS_SR_PCS_TP_A3 (TPCS_PCS_MMD_BaseAddress + 4*0x25 )
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#define TPCS_SR_PCS_TP_B0 (TPCS_PCS_MMD_BaseAddress + 4*0x26 )
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#define TPCS_SR_PCS_TP_B1 (TPCS_PCS_MMD_BaseAddress + 4*0x27 )
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#define TPCS_SR_PCS_TP_B2 (TPCS_PCS_MMD_BaseAddress + 4*0x28 )
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#define TPCS_SR_PCS_TP_B3 (TPCS_PCS_MMD_BaseAddress + 4*0x29 )
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#define TPCS_SR_PCS_TP_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x2a )
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#define TPCS_SR_PCS_TP_ERRCTR (TPCS_PCS_MMD_BaseAddress + 4*0x2b )
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#define TPCS_SR_PCS_BER_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2c )
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#define TPCS_SR_PCS_ERR_BLK_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2d )
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#define TPCS_SR_PCS_MLN_ALIGN_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x32 )
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#define TPCS_SR_PCS_MLN_ALIGN_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x33 )
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#define TPCS_SR_PCS_MLN_ALIGN_STS3 (TPCS_PCS_MMD_BaseAddress + 4*0x34 )
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#define TPCS_SR_PCS_MLN_ALIGN_STS4 (TPCS_PCS_MMD_BaseAddress + 4*0x35 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE0 (TPCS_PCS_MMD_BaseAddress + 4*0xc8 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE1 (TPCS_PCS_MMD_BaseAddress + 4*0xc9 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE2 (TPCS_PCS_MMD_BaseAddress + 4*0xca )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE3 (TPCS_PCS_MMD_BaseAddress + 4*0xcb )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE4 (TPCS_PCS_MMD_BaseAddress + 4*0xcc )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE5 (TPCS_PCS_MMD_BaseAddress + 4*0xcd )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE6 (TPCS_PCS_MMD_BaseAddress + 4*0xce )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE7 (TPCS_PCS_MMD_BaseAddress + 4*0xcf )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE8 (TPCS_PCS_MMD_BaseAddress + 4*0xd0 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE9 (TPCS_PCS_MMD_BaseAddress + 4*0xd1 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE10 (TPCS_PCS_MMD_BaseAddress + 4*0xd2 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE11 (TPCS_PCS_MMD_BaseAddress + 4*0xd3 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE12 (TPCS_PCS_MMD_BaseAddress + 4*0xd4 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE13 (TPCS_PCS_MMD_BaseAddress + 4*0xd5 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE14 (TPCS_PCS_MMD_BaseAddress + 4*0xd6 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE15 (TPCS_PCS_MMD_BaseAddress + 4*0xd7 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE16 (TPCS_PCS_MMD_BaseAddress + 4*0xd8 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE17 (TPCS_PCS_MMD_BaseAddress + 4*0xd9 )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE18 (TPCS_PCS_MMD_BaseAddress + 4*0xda )
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#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE19 (TPCS_PCS_MMD_BaseAddress + 4*0xdb )
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#define TPCS_SR_PCS_LANE0_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x190 )
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#define TPCS_SR_PCS_LANE1_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x191 )
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#define TPCS_SR_PCS_LANE2_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x192 )
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#define TPCS_SR_PCS_LANE3_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x193 )
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#define TPCS_SR_PCS_LANE4_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x194 )
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#define TPCS_SR_PCS_LANE5_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x195 )
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#define TPCS_SR_PCS_LANE6_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x196 )
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#define TPCS_SR_PCS_LANE7_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x197 )
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#define TPCS_SR_PCS_LANE8_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x198 )
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#define TPCS_SR_PCS_LANE9_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x199 )
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#define TPCS_SR_PCS_LANE10_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19a )
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#define TPCS_SR_PCS_LANE11_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19b )
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#define TPCS_SR_PCS_LANE12_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19c )
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#define TPCS_SR_PCS_LANE13_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19d )
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#define TPCS_SR_PCS_LANE14_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19e )
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#define TPCS_SR_PCS_LANE15_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19f )
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#define TPCS_SR_PCS_LANE16_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a0 )
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#define TPCS_SR_PCS_LANE17_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a1 )
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#define TPCS_SR_PCS_LANE18_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a2 )
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#define TPCS_SR_PCS_LANE19_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a3 )
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#define TPCS_VR_PCS_DIG_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x8000)
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#define TPCS_VR_PCS_DIG_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x8001)
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#define TPCS_VR_PCS_DIG_CTRL3 (TPCS_PCS_MMD_BaseAddress + 4*0x8003)
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#define TPCS_VR_PCS_DEBUG_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8005)
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#define TPCS_VR_PCS_EEE_MCTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8006)
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#define TPCS_VR_PCS_KR_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8007)
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#define TPCS_VR_PCS_EEE_TXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8008)
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#define TPCS_VR_PCS_EEE_RXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8009)
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#define TPCS_VR_PCS_EEE_MISC_TIMER (TPCS_PCS_MMD_BaseAddress + 4*0x800a)
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#define TPCS_VR_PCS_DIG_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8010)
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#define TPCS_VR_PCS_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x8018)
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#define TPCS_VR_PCS_SKW_OUT_OF_RANGE (TPCS_PCS_MMD_BaseAddress + 4*0x8019)
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#define TPCS_VR_PCS_ALT_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x801a)
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#define TPCS_VR_PCS_MISC_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8020)
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#define TPCS_SR_AN_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x0 )
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#define TPCS_SR_AN_STS (TPCS_AN_MMD_BaseAddress + 4*0x1 )
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#define TPCS_SR_AN_DEV_ID1 (TPCS_AN_MMD_BaseAddress + 4*0x2 )
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#define TPCS_SR_AN_DEV_ID2 (TPCS_AN_MMD_BaseAddress + 4*0x3 )
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#define TPCS_SR_AN_DEV_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0x5 )
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#define TPCS_SR_AN_DEV_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0x6 )
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#define TPCS_SR_AN_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0xe )
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#define TPCS_SR_AN_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0xf )
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#define TPCS_SR_AN_ADV1 (TPCS_AN_MMD_BaseAddress + 4*0x10 )
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#define TPCS_SR_AN_ADV2 (TPCS_AN_MMD_BaseAddress + 4*0x11 )
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#define TPCS_SR_AN_ADV3 (TPCS_AN_MMD_BaseAddress + 4*0x12 )
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#define TPCS_SR_AN_LP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x13 )
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#define TPCS_SR_AN_LP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x14 )
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#define TPCS_SR_AN_LP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x15 )
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#define TPCS_SR_AN_XNP_TX1 (TPCS_AN_MMD_BaseAddress + 4*0x16 )
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#define TPCS_SR_AN_XNP_TX2 (TPCS_AN_MMD_BaseAddress + 4*0x17 )
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#define TPCS_SR_AN_XNP_TX3 (TPCS_AN_MMD_BaseAddress + 4*0x18 )
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#define TPCS_SR_AN_LP_XNP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x19 )
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#define TPCS_SR_AN_LP_XNP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x1a )
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#define TPCS_SR_AN_LP_XNP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x1b )
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#define TPCS_SR_AN_COMP_STS (TPCS_AN_MMD_BaseAddress + 4*0x30 )
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#define TPCS_SR_AN_EEE_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3c )
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#define TPCS_SR_AN_EEE_LP_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3d )
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#define TPCS_VR_AN_VR_DIG_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8000 )
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#define TPCS_VR_AN_INTR_MSK (TPCS_AN_MMD_BaseAddress + 4*0x8001 )
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#define TPCS_VR_AN_INTR (TPCS_AN_MMD_BaseAddress + 4*0x8002 )
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#define TPCS_VR_AN_MODE_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8003 )
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#define TPCS_VR_AN_TIMER_CTRL0 (TPCS_AN_MMD_BaseAddress + 4*0x8004 )
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#define TPCS_VR_AN_TIMER_CTRL1 (TPCS_AN_MMD_BaseAddress + 4*0x8005 )
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#define TPCS_SR_VSMMD_PMA_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x0 )
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#define TPCS_SR_VSMMD_PMA_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x1 )
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#define TPCS_SR_VSMMD_DEV_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x2 )
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#define TPCS_SR_VSMMD_DEV_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x3 )
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#define TPCS_SR_VSMMD_PCS_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x4 )
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#define TPCS_SR_VSMMD_PCS_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x5 )
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#define TPCS_SR_VSMMD_AN_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x6 )
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#define TPCS_SR_VSMMD_AN_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x7 )
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#define TPCS_SR_VSMMD_STS (TPCS_VS_MMD1_BaseAddress + 4*0x8 )
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#define TPCS_SR_VSMMD_CTRL (TPCS_VS_MMD1_BaseAddress + 4*0x9 )
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#define TPCS_SR_VSMMD_PKGID1 (TPCS_VS_MMD1_BaseAddress + 4*0xe )
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#define TPCS_SR_VSMMD_PKGID2 (TPCS_VS_MMD1_BaseAddress + 4*0xf )
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#endif
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