修改 build.sh 中关于 rfic/adrv9026/out 的取库路径；增加 UCP_AOI_RFIC_CellInit 的带宽设置
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boheng.lin
parent
a20ae806a1
commit
098a159cd3
@ -31,8 +31,8 @@ extern int32_t osp_set_taskcpu(uint8_t cpu, uint8_t pri);
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extern uint8_t osp_sw_queue_init();
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#ifdef ENABLE_JESD_TEST
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extern int32_t UCP_API_RFIC_CellInit(void);
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extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
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extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
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extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
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#endif
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@ -51,8 +51,9 @@ int32_t main(int32_t argc, char* argvp[])
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sched_setaffinity(0,sizeof(cpu_set_t),&mask);
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#ifdef ENABLE_JESD_TEST
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UCP_API_RFIC_CellInit();
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UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 100000000u, 0);
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UCP_API_RFIC_CellInit(100000000u);
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// UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 0);
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UCP_API_RFIC_CellSetup(2566890000u, 2566890000u, 0);
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#endif
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osp_init();
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osp_set_taskcpu(7, 95);
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2
build.sh
2
build.sh
@ -39,7 +39,7 @@ done
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export DIR_ROOT=$(cd `dirname "$0"`;pwd)
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#echo "# script_dir:${DIR_ROOT}"
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export RFIC_DIR=${DIR_ROOT}/driver/rfic
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export RFIC_DIR=${DIR_ROOT}/driver/rfic/adrv9026
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export BUILD_DIR=${DIR_ROOT}/build
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if [ -d ${BUILD_DIR} ]; then
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@ -6,7 +6,7 @@ git submodule update --remote --merge --recursive driver/rfic
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pushd driver/rfic
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git clean -dxf
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git fetch
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git checkout DEV
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git checkout DEV_feature#1028#
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git pull
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#git checkout commitid
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#git submodule init
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43
download.exp
Normal file
43
download.exp
Normal file
@ -0,0 +1,43 @@
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#!/usr/bin/expect
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set port [lindex $argv 0]
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#set ip 172.29.118
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set ip 192.168.20
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set timeout -1
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spawn ssh root@$ip.$port rm -rf /root/rfic
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expect {
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"password" {send "root\r"}
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}
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expect eof
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set timeout -1
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spawn ssh root@$ip.$port rm -rf /root/*.txt;
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expect {
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"password" {send "root\r"}
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}
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expect eof
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set timeout -1
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spawn scp -r ./build/msgtransfer.out ./driver/rfic/adrv9026/csubin/256QAM/ ./driver/rfic/adrv9026/csubin/256QAM/start.sh root@$ip.$port:/root/
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expect {
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"password" {send "root\r"}
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}
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expect eof
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set timeout -1
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spawn scp -r ./driver/rfic/adrv9026/resources/ucp_trx_gpioCfg_evmy.json ./driver/rfic/adrv9026/resources/ucp_trx_gpioCfg_evb.json root@$ip.$port:/lib/firmware/resources/
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expect {
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"password" {send "root\r"}
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}
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expect eof
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set timeout -1
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spawn ssh root@$ip.$port sync;
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expect {
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"password" {send "root\r"}
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}
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expect eof
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@ -1 +1 @@
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Subproject commit 089a57ea572f30331b34103b1ed5429682856c75
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Subproject commit 0391452992501a90564728d5e5844c3f724eee5f
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@ -1,6 +1,6 @@
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//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
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// FileName : ucp_api_jesd.h
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// Author : boheng.lin@smartlogictech.com
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// Author : Boheng Lin bhlin919@126.com
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// Date First Issued : 2023-03-04 14:37:50 PM
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// Last Modified :
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// Description :
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@ -14,12 +14,18 @@
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#define UCP_API_JESD_H_
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \brief the max channels of trx
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*/
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#define MAX_UCP_JESD_TRX_CH (4)
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/**
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* \brief Data structure to hold UCP API State
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*/
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@ -45,20 +51,42 @@ typedef enum ucp_jesd_ApeWorkStep
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UCP_JESD_APE_CELLRUN = 0x02,
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} ucp_jesd_ApeWorkStep_e;
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/**
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* \brief Data structure to the level status of trx's control pins.
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*/
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typedef enum ucp_jesd_gpioEnableLevel
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{
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UCP_JESD_TRX_GPIO_DISABLE = 0x00,
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UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
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UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
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} ucp_jesd_gpioEnableLevel_e;
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/**
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* \brief Data structure to contrl pins of rf's trx
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*/
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typedef struct ucp_jesd_gpio {
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uint8_t port;
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uint8_t pin;
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uint8_t enableLevel;
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} ucp_jesd_gpio_t;
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typedef struct ucp_jesd_TrxGpio {
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uint8_t ch0_tx_gpio_index;
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uint8_t ch0_rx_gpio_index;
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uint8_t ch1_tx_gpio_index;
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uint8_t ch1_rx_gpio_index;
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uint8_t ch2_tx_gpio_index;
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uint8_t ch2_rx_gpio_index;
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uint8_t ch3_tx_gpio_index;
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uint8_t ch3_rx_gpio_index;
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ucp_jesd_gpio_t tx;
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ucp_jesd_gpio_t rx;
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ucp_jesd_gpio_t orx;
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} ucp_jesd_TrxGpio_t;
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/**
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* \brief Data structure to configure of trx's contrl pins
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*/
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typedef struct ucp_jesd_TrxGpioCfg {
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uint8_t maxCh;
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int32_t uldelay;
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int32_t dldelay;
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ucp_jesd_gpio_t triger;
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ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
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} ucp_jesd_TrxGpioCfg_t;
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/**
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* \brief Data structure to hold digital clock settings
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*/
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@ -141,7 +169,7 @@ extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
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*
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* \retval none.
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*/
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extern void UCP_API_JESD_TrxGpioSetup (ucp_jesd_TrxGpio_t *gpio);
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extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
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/**
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* \brief Sets up the ucp4008 jesd's para setting
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@ -1,6 +1,6 @@
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//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
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// FileName : ucp_api_rfic.h
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// Author : boheng.lin@smartlogictech.com
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// Author : Boheng Lin bhlin919@126.com
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// Date First Issued : 2023-03-04 17:39:00 PM
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// Last Modified :
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// Description :
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@ -22,19 +22,25 @@ extern "C" {
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//**********************************************************************************
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// system option layer
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extern int32_t UCP_API_RFIC_CellInit(void);
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/**
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* \brief Sets up the cell's default config
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*
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* \param bw is bandwidth (Unit hz).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
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/**
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* \brief Sets up the cell's default config
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*
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* \param txLo is Transmit local frequency (Unit hz).
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* \param rxLo is Receive local frequency (Unit hz).
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* \param bw is bandwidth (Unit hz).
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* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
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extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
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/**
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* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
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@ -61,19 +67,6 @@ extern int32_t UCP_API_RFIC_CellDelete(void);
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*/
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extern int32_t UCP_API_TRANSCEIVER_Reset(void);
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/**
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* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
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* then process Initialize transceiver
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*
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* \param txLo is Transmit local frequency (Unit hz).
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* \param rxLo is Receive local frequency (Unit hz).
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* \param bw is bandwidth (Unit hz).
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* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_TRANSCEIVER_Init(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
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/**
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* \brief Sets up the transceiver's MGC Mod.
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*
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@ -146,15 +139,6 @@ extern int32_t UCP_API_CLOCKGEN_Init(void);
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*/
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extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
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/**
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* \brief let the clockGen chip's systemclock one tick.
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*
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* \param void.
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*
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* \retval void.
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*/
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extern void UCP_API_CLOCKGEN_OnePluse(uint8_t enable);
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#ifdef __cplusplus
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}
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#endif
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18
root.exp
Normal file
18
root.exp
Normal file
@ -0,0 +1,18 @@
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#!/usr/bin/expect
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set port [lindex $argv 0]
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#set ip 172.29.118
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set ip 192.168.20
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spawn rm /public/linboheng/.ssh/known_hosts
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set timeout -1
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spawn ssh root@$ip.$port
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expect {
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"yes/no" {send "yes\r"}
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}
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set timeout 3
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expect {
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"password" {send "root\r"}
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}
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expect eof
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