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修改 build.sh 中关于 rfic/adrv9026/out 的取库路径；增加 UCP_AOI_RFIC_CellInit 的带宽设置

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This commit is contained in:
boheng.lin 2023-09-22 12:14:28 +08:00
parent a20ae806a1
commit 098a159cd3
8 changed files with 117 additions and 43 deletions
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9
app/src/main.c
View File

@ -31,8 +31,8 @@ extern int32_t osp_set_taskcpu(uint8_t cpu, uint8_t pri);
extern uint8_t osp_sw_queue_init();
#ifdef ENABLE_JESD_TEST
extern int32_t UCP_API_RFIC_CellInit(void);
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
#endif
@ -51,8 +51,9 @@ int32_t main(int32_t argc, char* argvp[])
sched_setaffinity(0,sizeof(cpu_set_t),&mask);
#ifdef ENABLE_JESD_TEST
UCP_API_RFIC_CellInit();
UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 100000000u, 0);
UCP_API_RFIC_CellInit(100000000u);
// UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 0);
UCP_API_RFIC_CellSetup(2566890000u, 2566890000u, 0);
#endif
osp_init();
osp_set_taskcpu(7, 95);

2
build.sh
View File

@ -39,7 +39,7 @@ done
export DIR_ROOT=$(cd `dirname "$0"`;pwd)
#echo "# script_dir:${DIR_ROOT}"
export RFIC_DIR=${DIR_ROOT}/driver/rfic
export RFIC_DIR=${DIR_ROOT}/driver/rfic/adrv9026
export BUILD_DIR=${DIR_ROOT}/build
if [ -d ${BUILD_DIR} ]; then

2
build_jesd.sh
View File

@ -6,7 +6,7 @@ git submodule update --remote --merge --recursive driver/rfic
pushd driver/rfic
git clean -dxf
git fetch
git checkout DEV
git checkout DEV_feature#1028#
git pull
#git checkout commitid
#git submodule init

43
download.exp Normal file
View File

@ -0,0 +1,43 @@
#!/usr/bin/expect
set port [lindex $argv 0]
#set ip 172.29.118
set ip 192.168.20
set timeout -1
spawn ssh root@$ip.$port rm -rf /root/rfic
expect {
"password" {send "root\r"}
}
expect eof
set timeout -1
spawn ssh root@$ip.$port rm -rf /root/*.txt;
expect {
"password" {send "root\r"}
}
expect eof
set timeout -1
spawn scp -r ./build/msgtransfer.out ./driver/rfic/adrv9026/csubin/256QAM/ ./driver/rfic/adrv9026/csubin/256QAM/start.sh root@$ip.$port:/root/
expect {
"password" {send "root\r"}
}
expect eof
set timeout -1
spawn scp -r ./driver/rfic/adrv9026/resources/ucp_trx_gpioCfg_evmy.json ./driver/rfic/adrv9026/resources/ucp_trx_gpioCfg_evb.json root@$ip.$port:/lib/firmware/resources/
expect {
"password" {send "root\r"}
}
expect eof
set timeout -1
spawn ssh root@$ip.$port sync;
expect {
"password" {send "root\r"}
}
expect eof

2
driver/rfic

@ -1 +1 @@
Subproject commit 089a57ea572f30331b34103b1ed5429682856c75
Subproject commit 0391452992501a90564728d5e5844c3f724eee5f

48
interface/ucp_api_jesd.h
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@ -1,6 +1,6 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_jesd.h
// Author : boheng.lin@smartlogictech.com
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 14:37:50 PM
// Last Modified :
// Description :
@ -14,12 +14,18 @@
#define UCP_API_JESD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief the max channels of trx
*/
#define MAX_UCP_JESD_TRX_CH (4)
/**
* \brief Data structure to hold UCP API State
*/
@ -45,20 +51,42 @@ typedef enum ucp_jesd_ApeWorkStep
UCP_JESD_APE_CELLRUN = 0x02,
} ucp_jesd_ApeWorkStep_e;
/**
* \brief Data structure to the level status of trx's control pins.
*/
typedef enum ucp_jesd_gpioEnableLevel
{
UCP_JESD_TRX_GPIO_DISABLE = 0x00,
UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
} ucp_jesd_gpioEnableLevel_e;
/**
* \brief Data structure to contrl pins of rf's trx
*/
typedef struct ucp_jesd_gpio {
uint8_t port;
uint8_t pin;
uint8_t enableLevel;
} ucp_jesd_gpio_t;
typedef struct ucp_jesd_TrxGpio {
uint8_t ch0_tx_gpio_index;
uint8_t ch0_rx_gpio_index;
uint8_t ch1_tx_gpio_index;
uint8_t ch1_rx_gpio_index;
uint8_t ch2_tx_gpio_index;
uint8_t ch2_rx_gpio_index;
uint8_t ch3_tx_gpio_index;
uint8_t ch3_rx_gpio_index;
ucp_jesd_gpio_t tx;
ucp_jesd_gpio_t rx;
ucp_jesd_gpio_t orx;
} ucp_jesd_TrxGpio_t;
/**
* \brief Data structure to configure of trx's contrl pins
*/
typedef struct ucp_jesd_TrxGpioCfg {
uint8_t maxCh;
int32_t uldelay;
int32_t dldelay;
ucp_jesd_gpio_t triger;
ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
} ucp_jesd_TrxGpioCfg_t;
/**
* \brief Data structure to hold digital clock settings
*/
@ -141,7 +169,7 @@ extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
*
* \retval none.
*/
extern void UCP_API_JESD_TrxGpioSetup (ucp_jesd_TrxGpio_t *gpio);
extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
/**
* \brief Sets up the ucp4008 jesd's para setting

36
interface/ucp_api_rfic.h
View File

@ -1,6 +1,6 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_rfic.h
// Author : boheng.lin@smartlogictech.com
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 17:39:00 PM
// Last Modified :
// Description :
@ -22,19 +22,25 @@ extern "C" {
//**********************************************************************************
// system option layer
extern int32_t UCP_API_RFIC_CellInit(void);
/**
* \brief Sets up the cell's default config
*
* \param bw is bandwidth (Unit hz).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
@ -61,19 +67,6 @@ extern int32_t UCP_API_RFIC_CellDelete(void);
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Init(uint64_t txLo, uint64_t rxLo, uint64_t bw, uint16_t initAtt);
/**
* \brief Sets up the transceiver's MGC Mod.
*
@ -146,15 +139,6 @@ extern int32_t UCP_API_CLOCKGEN_Init(void);
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
/**
* \brief let the clockGen chip's systemclock one tick.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_OnePluse(uint8_t enable);
#ifdef __cplusplus
}
#endif

18
root.exp Normal file
View File

@ -0,0 +1,18 @@
#!/usr/bin/expect
set port [lindex $argv 0]
#set ip 172.29.118
set ip 192.168.20
spawn rm /public/linboheng/.ssh/known_hosts
set timeout -1
spawn ssh root@$ip.$port
expect {
"yes/no" {send "yes\r"}
}
set timeout 3
expect {
"password" {send "root\r"}
}
expect eof