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Merge branch 'dev_ck_v2.1_feature#1028#' into 'dev_ck_v2.1'

Browse Source 
链接 ucp4008_rfic DEV 版本; 添加 case43

See merge request ucp/driver/ucp4008_platform_arm!25
This commit is contained in:
Xianfeng Du 2023-09-25 07:52:09 +00:00
commit 0cc6b8347d
19 changed files with 1446 additions and 376 deletions
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2
build_jesd.sh Executable file → Normal file
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@ -6,7 +6,7 @@ git submodule update --remote --merge --recursive driver/rfic
pushd driver/rfic
git clean -dxf
git fetch
git checkout DEV_feature#1028#
git checkout DEV
git pull
#git checkout commitid
#git submodule init

33
test/case40/inc/ucp_api_clockGen.h
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@ -1,33 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_clockGen.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_CLOCKGEN_H_
#define UCP_API_CLOCKGEN_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_CLOCKGEN_Reset(void);
extern void UCP_API_CLOCKGEN_Init(void);
extern void UCP_API_CLOCKGEN_LockStatus(void);
extern void UCP_API_CLOCKGEN_OnePluse(void);
extern uint8_t UCP_API_CLOCKGEN_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_CLOCKGEN_H_ */

201
test/case40/inc/ucp_api_jesd.h
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@ -1,7 +1,7 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_jesd.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 14:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
@ -14,34 +14,193 @@
#define UCP_API_JESD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_JESD_PlatformSetup (void);
extern void UCP_API_JESD_Reset(void);
extern void UCP_API_JESD_CRG_Cfg(void);
extern void UCP_API_JESD_PMA_Cfg(void);
extern void UCP_API_JESD_JsSubCtrl_Cfg(void);
extern void UCP_API_JESD_SUB_Init(void);
extern void UCP_API_JESD_Gpio_Cfg(void);
extern void UCP_API_RF_PA_Pow(void);
extern void UCP_API_RF_PA_Set(void);
extern void UCP_API_RF_PA_Get(void);
extern void UCP_API_RF_LNA_Pow(void);
extern void UCP_API_RF_LNA_Set(void);
extern void UCP_API_RF_LNA_Get(void);
extern void UCP_API_RF_RFFE_Tx(void);
extern void UCP_API_RF_RFFE_Rx(void);
extern void UCP_API_RF_RFFE_Att_Set(void);
extern void UCP_API_RF_RFFE_Att_Get(void);
extern void UCP_API_RF_RFFE_Gain_Set(void);
extern void UCP_API_RF_RFFE_Gain_Get(void);
/**
* \brief the max channels of trx
*/
#define MAX_UCP_JESD_TRX_CH (4)
/**
* \brief Data structure to hold UCP API State
*/
typedef enum ucp_jesd_States
{
UCP_JESD_STATE_POWERONRESET = 0x00,
UCP_JESD_STATE_JSCTRLOK = 0x01,
UCP_JESD_STATE_CRGOK = 0x02,
UCP_JESD_STATE_SUBCTRLOK = 0x04,
UCP_JESD_STATE_204COREOK = 0x08,
UCP_JESD_STATE_PMAOK = 0x10,
UCP_JESD_STATE_TIMEROK = 0x20,
UCP_JESD_STATE_RUN = 0x40
} ucp_jesd_States_e;
/**
* \brief Data structure to ape working step
*/
typedef enum ucp_jesd_ApeWorkStep
{
UCP_JESD_APE_POWERONRESET = 0x00,
UCP_JESD_APE_CLOCKGENRUN = 0x01,
UCP_JESD_APE_CELLRUN = 0x02,
} ucp_jesd_ApeWorkStep_e;
/**
* \brief Data structure to the level status of trx's control pins.
*/
typedef enum ucp_jesd_gpioEnableLevel
{
UCP_JESD_TRX_GPIO_DISABLE = 0x00,
UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
} ucp_jesd_gpioEnableLevel_e;
/**
* \brief Data structure to contrl pins of rf's trx
*/
typedef struct ucp_jesd_gpio {
uint8_t port;
uint8_t pin;
uint8_t enableLevel;
} ucp_jesd_gpio_t;
typedef struct ucp_jesd_TrxGpio {
ucp_jesd_gpio_t tx;
ucp_jesd_gpio_t rx;
ucp_jesd_gpio_t orx;
} ucp_jesd_TrxGpio_t;
/**
* \brief Data structure to configure of trx's contrl pins
*/
typedef struct ucp_jesd_TrxGpioCfg {
uint8_t maxCh;
int32_t uldelay;
int32_t dldelay;
ucp_jesd_gpio_t triger;
ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
} ucp_jesd_TrxGpioCfg_t;
/**
* \brief Data structure to hold digital clock settings
*/
typedef struct ucp_jesd_CommonSettings
{
uint32_t devClock_kHz; /*!< Device clock frequency in kHz */
uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */
uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */
uint8_t jesdSubClass;
} ucp_jesd_CommonSettings_t;
/**
* \brief Data structure to hold UCP JESD204b Framer configuration settings
*/
typedef struct ucp_jesd_FrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */
} ucp_jesd_FrmCfg_t;
/**
* \brief Data structure to hold the settings for the deframer configuration
*/
typedef struct ucp_jesd_DfrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */
} ucp_jesd_DfrmCfg_t;
/**
* \brief Data structure to hold ucp JESD Framer and Deframer configuration information
*/
typedef struct ucp_jesd_Init
{
ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */
ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */
ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */
} ucp_jesd_Init_t;
/**
* \brief get jesd module's version
*
* \param void
*
* \retval version.
*/
extern uint32_t UCP_API_JESD_Version(void);
/**
* \brief Sets up the ape work step
*
* \param step
* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value
* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value
* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value
*
* \retval none.
*/
extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
/**
* \brief Sets up the gpios of tx and rx
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_CellDelete (void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_JESD_H_ */

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test/case40/inc/ucp_api_rfic.h Normal file
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@ -0,0 +1,147 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_rfic.h
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 17:39:00 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
//**********************************************************************************
// system option layer
/**
* \brief Sets up the cell's default config
*
* \param bw is bandwidth (Unit hz).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);
//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);
/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);
/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);
/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);
/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);
/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);
//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);
/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);
/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_RFIC_H_ */

50
test/case40/inc/ucp_api_transceiver.h
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@ -1,50 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_transceiver.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_TRANSCEIVER_H_
#define UCP_API_TRANSCEIVER_H_
#include <stdint.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_TRANSCEIVER_Reset(void);
extern void UCP_API_TRANSCEIVER_Init(void);
extern void UCP_API_TRANSCEIVER_MGC_Cfg(void);
extern void UCP_API_TRANSCEIVER_Gain_Set(void);
extern void UCP_API_TRANSCEIVER_Gain_Get(void);
extern void UCP_API_TRANSCEIVER_Att_Set(void);
extern void UCP_API_TRANSCEIVER_Att_Get(void);
extern void UCP_API_TRANSCEIVER_TRX_Cfg(void);
extern void UCP_API_TRANSCEIVER_Tx(void);
extern void UCP_API_TRANSCEIVER_Rx(void);
extern void UCP_API_TRANSCEIVER_LO_Set(void);
extern void UCP_API_TRANSCEIVER_LO_Get(void);
extern void UCP_API_TRANSCEIVER_IQ_Cal(void);
extern void UCP_API_TRANSCEIVER_MCS(void);
extern void UCP_API_TRANSCEIVER_SampleRate_Get(void);
extern void UCP_API_TRANSCEIVER_Bandwidth_Get(void);
extern void UCP_API_TRANSCEIVER_LinkStatus(void);
extern void UCP_API_TRANSCEIVER_Tone(bool set);
extern int16_t UCP_API_TRANSCEIVER_getTemperature(void);
extern uint32_t UCP_API_TRANSCEIVER_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_TRANSCEIVER_H_ */

102
test/case40/src/testcase.c
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@ -1,49 +1,53 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : test.c
// Author : xianfeng.du
// Created On : 2022-11-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include <stddef.h>
#include <string.h>
#include <sys/time.h>
#include <unistd.h>
#include "typedef.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "ecs_sm_mgt.h"
#include "ucp_handshake.h"
#include "ospShell.h"
#include "stc_drv.h"
#include "ospLog.h"
#include "osp_cfg_to_bin.h"
#include "ucp_api_jesd.h"
#include "ucp_api_transceiver.h"
int32_t test_case(uint32_t argc, int32_t* argvp)
{
UCP_PRINT_DEBUG("start running testcase 40.");
UCP_PRINT_DEBUG("start monitor temperature and lock status.");
while (1)
{
UCP_API_TRANSCEIVER_getTemperature();
UCP_API_TRANSCEIVER_getLockStatus();
sleep(2);
}
return 0;
}
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : test.c
// Author : xianfeng.du
// Created On : 2022-11-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include <stddef.h>
#include <string.h>
#include <sys/time.h>
#include <unistd.h>
#include "typedef.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "pet_sm_mgt.h"
#include "ucp_handshake.h"
#include "ospShell.h"
#include "ospLog.h"
#include "ospCfgToBin.h"
#include "drv_init.h"
#include "ucp_api_jesd.h"
#include "ucp_api_rfic.h"
extern uint8_t ucp_api_ad9528_LockStatus(void);
extern uint32_t adrv9026_getLockStatus (void);
extern int16_t adrv9026_getTemperature (void);
int32_t test_case(uint32_t argc, int32_t* argvp)
{
UCP_PRINT_DEBUG("start running testcase 40.");
UCP_PRINT_DEBUG("start monitor temperature and lock status.");
while (1)
{
ucp_api_ad9528_LockStatus();
adrv9026_getLockStatus();
adrv9026_getTemperature();
sleep(2);
}
return 0;
}

33
test/case41/inc/ucp_api_clockGen.h
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@ -1,33 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_clockGen.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_CLOCKGEN_H_
#define UCP_API_CLOCKGEN_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_CLOCKGEN_Reset(void);
extern void UCP_API_CLOCKGEN_Init(void);
extern void UCP_API_CLOCKGEN_LockStatus(void);
extern void UCP_API_CLOCKGEN_OnePluse(void);
extern uint8_t UCP_API_CLOCKGEN_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_CLOCKGEN_H_ */

201
test/case41/inc/ucp_api_jesd.h
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@ -1,7 +1,7 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_jesd.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 14:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
@ -14,34 +14,193 @@
#define UCP_API_JESD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_JESD_PlatformSetup (void);
extern void UCP_API_JESD_Reset(void);
extern void UCP_API_JESD_CRG_Cfg(void);
extern void UCP_API_JESD_PMA_Cfg(void);
extern void UCP_API_JESD_JsSubCtrl_Cfg(void);
extern void UCP_API_JESD_SUB_Init(void);
extern void UCP_API_JESD_Gpio_Cfg(void);
extern void UCP_API_RF_PA_Pow(void);
extern void UCP_API_RF_PA_Set(void);
extern void UCP_API_RF_PA_Get(void);
extern void UCP_API_RF_LNA_Pow(void);
extern void UCP_API_RF_LNA_Set(void);
extern void UCP_API_RF_LNA_Get(void);
extern void UCP_API_RF_RFFE_Tx(void);
extern void UCP_API_RF_RFFE_Rx(void);
extern void UCP_API_RF_RFFE_Att_Set(void);
extern void UCP_API_RF_RFFE_Att_Get(void);
extern void UCP_API_RF_RFFE_Gain_Set(void);
extern void UCP_API_RF_RFFE_Gain_Get(void);
/**
* \brief the max channels of trx
*/
#define MAX_UCP_JESD_TRX_CH (4)
/**
* \brief Data structure to hold UCP API State
*/
typedef enum ucp_jesd_States
{
UCP_JESD_STATE_POWERONRESET = 0x00,
UCP_JESD_STATE_JSCTRLOK = 0x01,
UCP_JESD_STATE_CRGOK = 0x02,
UCP_JESD_STATE_SUBCTRLOK = 0x04,
UCP_JESD_STATE_204COREOK = 0x08,
UCP_JESD_STATE_PMAOK = 0x10,
UCP_JESD_STATE_TIMEROK = 0x20,
UCP_JESD_STATE_RUN = 0x40
} ucp_jesd_States_e;
/**
* \brief Data structure to ape working step
*/
typedef enum ucp_jesd_ApeWorkStep
{
UCP_JESD_APE_POWERONRESET = 0x00,
UCP_JESD_APE_CLOCKGENRUN = 0x01,
UCP_JESD_APE_CELLRUN = 0x02,
} ucp_jesd_ApeWorkStep_e;
/**
* \brief Data structure to the level status of trx's control pins.
*/
typedef enum ucp_jesd_gpioEnableLevel
{
UCP_JESD_TRX_GPIO_DISABLE = 0x00,
UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
} ucp_jesd_gpioEnableLevel_e;
/**
* \brief Data structure to contrl pins of rf's trx
*/
typedef struct ucp_jesd_gpio {
uint8_t port;
uint8_t pin;
uint8_t enableLevel;
} ucp_jesd_gpio_t;
typedef struct ucp_jesd_TrxGpio {
ucp_jesd_gpio_t tx;
ucp_jesd_gpio_t rx;
ucp_jesd_gpio_t orx;
} ucp_jesd_TrxGpio_t;
/**
* \brief Data structure to configure of trx's contrl pins
*/
typedef struct ucp_jesd_TrxGpioCfg {
uint8_t maxCh;
int32_t uldelay;
int32_t dldelay;
ucp_jesd_gpio_t triger;
ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
} ucp_jesd_TrxGpioCfg_t;
/**
* \brief Data structure to hold digital clock settings
*/
typedef struct ucp_jesd_CommonSettings
{
uint32_t devClock_kHz; /*!< Device clock frequency in kHz */
uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */
uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */
uint8_t jesdSubClass;
} ucp_jesd_CommonSettings_t;
/**
* \brief Data structure to hold UCP JESD204b Framer configuration settings
*/
typedef struct ucp_jesd_FrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */
} ucp_jesd_FrmCfg_t;
/**
* \brief Data structure to hold the settings for the deframer configuration
*/
typedef struct ucp_jesd_DfrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */
} ucp_jesd_DfrmCfg_t;
/**
* \brief Data structure to hold ucp JESD Framer and Deframer configuration information
*/
typedef struct ucp_jesd_Init
{
ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */
ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */
ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */
} ucp_jesd_Init_t;
/**
* \brief get jesd module's version
*
* \param void
*
* \retval version.
*/
extern uint32_t UCP_API_JESD_Version(void);
/**
* \brief Sets up the ape work step
*
* \param step
* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value
* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value
* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value
*
* \retval none.
*/
extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
/**
* \brief Sets up the gpios of tx and rx
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_CellDelete (void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_JESD_H_ */

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//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_rfic.h
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 17:39:00 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
//**********************************************************************************
// system option layer
/**
* \brief Sets up the cell's default config
*
* \param bw is bandwidth (Unit hz).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);
//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);
/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);
/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);
/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);
/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);
/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);
//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);
/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);
/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_RFIC_H_ */

50
test/case41/inc/ucp_api_transceiver.h
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@ -1,50 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_transceiver.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_TRANSCEIVER_H_
#define UCP_API_TRANSCEIVER_H_
#include <stdint.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_TRANSCEIVER_Reset(void);
extern void UCP_API_TRANSCEIVER_Init(void);
extern void UCP_API_TRANSCEIVER_MGC_Cfg(void);
extern void UCP_API_TRANSCEIVER_Gain_Set(void);
extern void UCP_API_TRANSCEIVER_Gain_Get(void);
extern void UCP_API_TRANSCEIVER_Att_Set(void);
extern void UCP_API_TRANSCEIVER_Att_Get(void);
extern void UCP_API_TRANSCEIVER_TRX_Cfg(void);
extern void UCP_API_TRANSCEIVER_Tx(void);
extern void UCP_API_TRANSCEIVER_Rx(void);
extern void UCP_API_TRANSCEIVER_LO_Set(void);
extern void UCP_API_TRANSCEIVER_LO_Get(void);
extern void UCP_API_TRANSCEIVER_IQ_Cal(void);
extern void UCP_API_TRANSCEIVER_MCS(void);
extern void UCP_API_TRANSCEIVER_SampleRate_Get(void);
extern void UCP_API_TRANSCEIVER_Bandwidth_Get(void);
extern void UCP_API_TRANSCEIVER_LinkStatus(void);
extern void UCP_API_TRANSCEIVER_Tone(bool set);
extern int16_t UCP_API_TRANSCEIVER_getTemperature(void);
extern uint32_t UCP_API_TRANSCEIVER_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_TRANSCEIVER_H_ */

17
test/case41/src/testcase.c
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@ -20,25 +20,26 @@
#include "typedef.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "ecs_sm_mgt.h"
#include "pet_sm_mgt.h"
#include "ucp_handshake.h"
#include "ospShell.h"
#include "stc_drv.h"
#include "ospLog.h"
#include "osp_cfg_to_bin.h"
#include "ospCfgToBin.h"
#include "drv_init.h"
#include "ucp_api_jesd.h"
#include "ucp_api_transceiver.h"
#include "ucp_api_rfic.h"
extern int32_t adrv9025_tone (bool set);
int32_t test_case(uint32_t argc, int32_t* argvp)
{
UCP_PRINT_DEBUG("start running testcase 41.");
UCP_PRINT_DEBUG("start transceiver tone.");
UCP_API_JESD_PlatformSetup();
UCP_API_TRANSCEIVER_Init();
UCP_API_TRANSCEIVER_Tone(true);
UCP_API_RFIC_CellInit(100000000u);
UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 0);
adrv9025_tone(true);
return 0;
}

33
test/case42/inc/ucp_api_clockGen.h
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@ -1,33 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_clockGen.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_CLOCKGEN_H_
#define UCP_API_CLOCKGEN_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_CLOCKGEN_Reset(void);
extern void UCP_API_CLOCKGEN_Init(void);
extern void UCP_API_CLOCKGEN_LockStatus(void);
extern void UCP_API_CLOCKGEN_OnePluse(void);
extern uint8_t UCP_API_CLOCKGEN_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_CLOCKGEN_H_ */

201
test/case42/inc/ucp_api_jesd.h
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@ -1,7 +1,7 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_jesd.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 14:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
@ -14,34 +14,193 @@
#define UCP_API_JESD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_JESD_PlatformSetup (void);
extern void UCP_API_JESD_Reset(void);
extern void UCP_API_JESD_CRG_Cfg(void);
extern void UCP_API_JESD_PMA_Cfg(void);
extern void UCP_API_JESD_JsSubCtrl_Cfg(void);
extern void UCP_API_JESD_SUB_Init(void);
extern void UCP_API_JESD_Gpio_Cfg(void);
extern void UCP_API_RF_PA_Pow(void);
extern void UCP_API_RF_PA_Set(void);
extern void UCP_API_RF_PA_Get(void);
extern void UCP_API_RF_LNA_Pow(void);
extern void UCP_API_RF_LNA_Set(void);
extern void UCP_API_RF_LNA_Get(void);
extern void UCP_API_RF_RFFE_Tx(void);
extern void UCP_API_RF_RFFE_Rx(void);
extern void UCP_API_RF_RFFE_Att_Set(void);
extern void UCP_API_RF_RFFE_Att_Get(void);
extern void UCP_API_RF_RFFE_Gain_Set(void);
extern void UCP_API_RF_RFFE_Gain_Get(void);
/**
* \brief the max channels of trx
*/
#define MAX_UCP_JESD_TRX_CH (4)
/**
* \brief Data structure to hold UCP API State
*/
typedef enum ucp_jesd_States
{
UCP_JESD_STATE_POWERONRESET = 0x00,
UCP_JESD_STATE_JSCTRLOK = 0x01,
UCP_JESD_STATE_CRGOK = 0x02,
UCP_JESD_STATE_SUBCTRLOK = 0x04,
UCP_JESD_STATE_204COREOK = 0x08,
UCP_JESD_STATE_PMAOK = 0x10,
UCP_JESD_STATE_TIMEROK = 0x20,
UCP_JESD_STATE_RUN = 0x40
} ucp_jesd_States_e;
/**
* \brief Data structure to ape working step
*/
typedef enum ucp_jesd_ApeWorkStep
{
UCP_JESD_APE_POWERONRESET = 0x00,
UCP_JESD_APE_CLOCKGENRUN = 0x01,
UCP_JESD_APE_CELLRUN = 0x02,
} ucp_jesd_ApeWorkStep_e;
/**
* \brief Data structure to the level status of trx's control pins.
*/
typedef enum ucp_jesd_gpioEnableLevel
{
UCP_JESD_TRX_GPIO_DISABLE = 0x00,
UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
} ucp_jesd_gpioEnableLevel_e;
/**
* \brief Data structure to contrl pins of rf's trx
*/
typedef struct ucp_jesd_gpio {
uint8_t port;
uint8_t pin;
uint8_t enableLevel;
} ucp_jesd_gpio_t;
typedef struct ucp_jesd_TrxGpio {
ucp_jesd_gpio_t tx;
ucp_jesd_gpio_t rx;
ucp_jesd_gpio_t orx;
} ucp_jesd_TrxGpio_t;
/**
* \brief Data structure to configure of trx's contrl pins
*/
typedef struct ucp_jesd_TrxGpioCfg {
uint8_t maxCh;
int32_t uldelay;
int32_t dldelay;
ucp_jesd_gpio_t triger;
ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
} ucp_jesd_TrxGpioCfg_t;
/**
* \brief Data structure to hold digital clock settings
*/
typedef struct ucp_jesd_CommonSettings
{
uint32_t devClock_kHz; /*!< Device clock frequency in kHz */
uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */
uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */
uint8_t jesdSubClass;
} ucp_jesd_CommonSettings_t;
/**
* \brief Data structure to hold UCP JESD204b Framer configuration settings
*/
typedef struct ucp_jesd_FrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */
} ucp_jesd_FrmCfg_t;
/**
* \brief Data structure to hold the settings for the deframer configuration
*/
typedef struct ucp_jesd_DfrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */
} ucp_jesd_DfrmCfg_t;
/**
* \brief Data structure to hold ucp JESD Framer and Deframer configuration information
*/
typedef struct ucp_jesd_Init
{
ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */
ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */
ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */
} ucp_jesd_Init_t;
/**
* \brief get jesd module's version
*
* \param void
*
* \retval version.
*/
extern uint32_t UCP_API_JESD_Version(void);
/**
* \brief Sets up the ape work step
*
* \param step
* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value
* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value
* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value
*
* \retval none.
*/
extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
/**
* \brief Sets up the gpios of tx and rx
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_CellDelete (void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_JESD_H_ */

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//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_rfic.h
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 17:39:00 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
//**********************************************************************************
// system option layer
/**
* \brief Sets up the cell's default config
*
* \param bw is bandwidth (Unit hz).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);
//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);
/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);
/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);
/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);
/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);
/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);
//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);
/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);
/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_RFIC_H_ */

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@ -1,50 +0,0 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_transceiver.h
// Author : boheng.lin@smartlogictech.com
// Date First Issued : 2023-03-04 02:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_TRANSCEIVER_H_
#define UCP_API_TRANSCEIVER_H_
#include <stdint.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void UCP_API_TRANSCEIVER_Reset(void);
extern void UCP_API_TRANSCEIVER_Init(void);
extern void UCP_API_TRANSCEIVER_MGC_Cfg(void);
extern void UCP_API_TRANSCEIVER_Gain_Set(void);
extern void UCP_API_TRANSCEIVER_Gain_Get(void);
extern void UCP_API_TRANSCEIVER_Att_Set(void);
extern void UCP_API_TRANSCEIVER_Att_Get(void);
extern void UCP_API_TRANSCEIVER_TRX_Cfg(void);
extern void UCP_API_TRANSCEIVER_Tx(void);
extern void UCP_API_TRANSCEIVER_Rx(void);
extern void UCP_API_TRANSCEIVER_LO_Set(void);
extern void UCP_API_TRANSCEIVER_LO_Get(void);
extern void UCP_API_TRANSCEIVER_IQ_Cal(void);
extern void UCP_API_TRANSCEIVER_MCS(void);
extern void UCP_API_TRANSCEIVER_SampleRate_Get(void);
extern void UCP_API_TRANSCEIVER_Bandwidth_Get(void);
extern void UCP_API_TRANSCEIVER_LinkStatus(void);
extern void UCP_API_TRANSCEIVER_Tone(bool set);
extern int16_t UCP_API_TRANSCEIVER_getTemperature(void);
extern uint32_t UCP_API_TRANSCEIVER_getLockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_TRANSCEIVER_H_ */

12
test/case42/src/testcase.c
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@ -20,15 +20,15 @@
#include "typedef.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "ecs_sm_mgt.h"
#include "pet_sm_mgt.h"
#include "ucp_handshake.h"
#include "ospShell.h"
#include "stc_drv.h"
#include "ospLog.h"
#include "osp_cfg_to_bin.h"
#include "ospCfgToBin.h"
#include "drv_init.h"
#include "ucp_api_jesd.h"
#include "ucp_api_transceiver.h"
#include "ucp_api_rfic.h"
extern void ad9025_rssi(void);
@ -37,8 +37,8 @@ int32_t test_case(uint32_t argc, int32_t* argvp)
UCP_PRINT_DEBUG("start running testcase 42s.");
UCP_PRINT_DEBUG("print rssi.");
UCP_API_JESD_PlatformSetup();
UCP_API_TRANSCEIVER_Init();
UCP_API_RFIC_CellInit(100000000u);
UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 0);
ad9025_rssi();
return 0;

206
test/case43/inc/ucp_api_jesd.h Normal file
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@ -0,0 +1,206 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_jesd.h
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 14:37:50 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_JESD_H_
#define UCP_API_JESD_H_
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief the max channels of trx
*/
#define MAX_UCP_JESD_TRX_CH (4)
/**
* \brief Data structure to hold UCP API State
*/
typedef enum ucp_jesd_States
{
UCP_JESD_STATE_POWERONRESET = 0x00,
UCP_JESD_STATE_JSCTRLOK = 0x01,
UCP_JESD_STATE_CRGOK = 0x02,
UCP_JESD_STATE_SUBCTRLOK = 0x04,
UCP_JESD_STATE_204COREOK = 0x08,
UCP_JESD_STATE_PMAOK = 0x10,
UCP_JESD_STATE_TIMEROK = 0x20,
UCP_JESD_STATE_RUN = 0x40
} ucp_jesd_States_e;
/**
* \brief Data structure to ape working step
*/
typedef enum ucp_jesd_ApeWorkStep
{
UCP_JESD_APE_POWERONRESET = 0x00,
UCP_JESD_APE_CLOCKGENRUN = 0x01,
UCP_JESD_APE_CELLRUN = 0x02,
} ucp_jesd_ApeWorkStep_e;
/**
* \brief Data structure to the level status of trx's control pins.
*/
typedef enum ucp_jesd_gpioEnableLevel
{
UCP_JESD_TRX_GPIO_DISABLE = 0x00,
UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
} ucp_jesd_gpioEnableLevel_e;
/**
* \brief Data structure to contrl pins of rf's trx
*/
typedef struct ucp_jesd_gpio {
uint8_t port;
uint8_t pin;
uint8_t enableLevel;
} ucp_jesd_gpio_t;
typedef struct ucp_jesd_TrxGpio {
ucp_jesd_gpio_t tx;
ucp_jesd_gpio_t rx;
ucp_jesd_gpio_t orx;
} ucp_jesd_TrxGpio_t;
/**
* \brief Data structure to configure of trx's contrl pins
*/
typedef struct ucp_jesd_TrxGpioCfg {
uint8_t maxCh;
int32_t uldelay;
int32_t dldelay;
ucp_jesd_gpio_t triger;
ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
} ucp_jesd_TrxGpioCfg_t;
/**
* \brief Data structure to hold digital clock settings
*/
typedef struct ucp_jesd_CommonSettings
{
uint32_t devClock_kHz; /*!< Device clock frequency in kHz */
uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */
uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */
uint8_t jesdSubClass;
} ucp_jesd_CommonSettings_t;
/**
* \brief Data structure to hold UCP JESD204b Framer configuration settings
*/
typedef struct ucp_jesd_FrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */
} ucp_jesd_FrmCfg_t;
/**
* \brief Data structure to hold the settings for the deframer configuration
*/
typedef struct ucp_jesd_DfrmCfg
{
uint8_t enable;
uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */
uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */
uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */
uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */
uint8_t jesd204E; /*!< JESD204C E parameter */
uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */
uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */
} ucp_jesd_DfrmCfg_t;
/**
* \brief Data structure to hold ucp JESD Framer and Deframer configuration information
*/
typedef struct ucp_jesd_Init
{
ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */
ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */
ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */
} ucp_jesd_Init_t;
/**
* \brief get jesd module's version
*
* \param void
*
* \retval version.
*/
extern uint32_t UCP_API_JESD_Version(void);
/**
* \brief Sets up the ape work step
*
* \param step
* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value
* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value
* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value
*
* \retval none.
*/
extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
/**
* \brief Sets up the gpios of tx and rx
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting);
/**
* \brief Sets up the ucp4008 jesd's para setting
*
* \param setting
*
* \retval none.
*/
extern void UCP_API_JESD_CellDelete (void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_JESD_H_ */

147
test/case43/inc/ucp_api_rfic.h Normal file
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@ -0,0 +1,147 @@
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
// FileName : ucp_api_rfic.h
// Author : Boheng Lin bhlin919@126.com
// Date First Issued : 2023-03-04 17:39:00 PM
// Last Modified :
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef UCP_API_RFIC_H_
#define UCP_API_RFIC_H_
#include <stdio.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
//**********************************************************************************
// system option layer
/**
* \brief Sets up the cell's default config
*
* \param bw is bandwidth (Unit hz).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellInit(uint64_t bw);
/**
* \brief Sets up the cell's default config
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt);
/**
* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
* then process Initialize transceiver
*
* \param txLo is Transmit local frequency (Unit hz).
* \param rxLo is Receive local frequency (Unit hz).
* \param bw is bandwidth (Unit hz).
* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
*
* \retval 0.
*/
extern int32_t UCP_API_RFIC_CellDelete(void);
//**********************************************************************************
// chip option layer
// TRANSCEIVER
/**
* \brief transceiver chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_TRANSCEIVER_Reset(void);
/**
* \brief Sets up the transceiver's MGC Mod.
*
* \param en, if set 1, MGC Mode; set 0, AGC Mode.
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);
/**
* \brief Sets up the transceiver's rx gain at MGC mode.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);
/**
* \brief Get the transceiver's rx gain.
*
* \param gain_db (Unit db, range 0~36, step 0.5db).
*
* \retval gain_db (Unit db, range 0~36, step 0.5db).
*/
extern double UCP_API_TRANSCEIVER_Gain_Get(void);
/**
* \brief Set up the transceiver's tx attenuation.
*
* \param att_db (Unit db, range 0~20).
*
* \retval 0.
*/
extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);
/**
* \brief Get the transceiver's tx attenuation.
*
* \retval att_db (Unit db, range 0~20).
*/
extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);
//**********************************************************************************
// CLOCKGEN
/**
* \brief clockGen chip hardware reset.
*
* \param void.
*
* \retval void.
*/
extern void UCP_API_CLOCKGEN_Reset(void);
/**
* \brief clockGen chip init function.
*
* \param void.
*
* \retval void.
*/
extern int32_t UCP_API_CLOCKGEN_Init(void);
/**
* \brief Get the status of clockGen chip's pll.
*
* \param void.
*
* \retval lock code.
*/
extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef UCP_API_RFIC_H_ */

43
test/case43/src/testcase.c Normal file
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@ -0,0 +1,43 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : test.c
// Author : xianfeng.du
// Created On : 2022-11-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include <stddef.h>
#include <string.h>
#include <sys/time.h>
#include <unistd.h>
#include "typedef.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "pet_sm_mgt.h"
#include "ucp_handshake.h"
#include "ospShell.h"
#include "ospLog.h"
#include "ospCfgToBin.h"
#include "drv_init.h"
#include "ucp_api_jesd.h"
#include "ucp_api_rfic.h"
int32_t test_case(uint32_t argc, int32_t* argvp)
{
UCP_PRINT_DEBUG("start running testcase 42s.");
UCP_PRINT_DEBUG("print rssi.");
UCP_API_RFIC_CellInit(200000000u);
UCP_API_RFIC_CellSetup(2575770000u, 2575770000u, 0);
return 0;
}