6 Commits

Author SHA1 Message Date
lishuang.xie
fe2787d53f update New Feature#1737 from dev_ck_v2.1_featuer#1737# to dev_ck_v2.1
1. modified the function: int32_t osp_read_spe_cfg_file(char* path, uint8_t cellid), add the cellid
2. modified the function: int32_t osp_get_cfg_file(char* name, uint8_t cellid, uint64_t *paddr, uint32_t *psize);, add the cellid
3. modified the interface file
4. modified the testcase which used the functions
5. Test:
   5.1 spu_case0_arm_case0_cpri:  Pass
   5.2 spu_case14_arm_caes20_cpri:Pass
   5.3 spu_case20_arm_case20_cpri:Pass
   5.4 spu_case24_arm_case24_cpri:Pass
   5.5 spu_case34_arm_case5:      Pass
   5.6 spu_case44_arm_case5:      Pass
2024-03-30 16:23:55 +08:00
lishuang.xie
5831721775 update feature#1694# merge dev_ck_v2.1_xls_feature#1694# to dev_ck_v2.1
1. Four-channel support
2. OAM ul change 32 blocks to 16 blocks, so modified the cases
3. Test:
   3.1 spu_case0_arm_case0_cpri:  Pass
   3.2 spu_case14_arm_case20_cpri:Pass
   3.3 spu_case20_arm_case20_cpri:Pass
   3.4 spu_case24_arm_case24_cpri:Pass
   3.5 spu_case34_arm_case5:      Pass
   3.6 spu_case44_arm_case5:      Pass
2024-03-18 15:23:35 +08:00
lishuang.xie
2d80c897ed use the enhancement#1546 delete the cell_setup_simulation's sleep into dev_ck_v2.1
1. delete the sleep which in the function of cell_setup_simulation
2. the function of cell_setup_simulation define in many cases
3. Test:
   3.1 spu(case0)+arm(case0):  Pass
   3.2 spu(case14)+arm(case20):Pass
   3.3 spu(case20)+arm(case20):Pass
   3.4 spu(case21)+arm(case21):Pass
   3.5 spu(case34)+arm(case5): Pass
   3.6 spu(case42)+arm(case46):Pass
   3.7 spu(case44)+arm(case5): Pass
2024-01-02 15:05:50 +08:00
liweihua
6719f4cde9 libstc.a与libmsgtransfer.a解耦 2023-12-29 16:48:28 +08:00
lishuang.xie
ec4c51c8d6 update New Feature#1120#
1. update the test/case20/src/testcase20.c
2. update the function cell_setup_simulation
3. test:
   3.1 SPU(case14)+ARM(case3) :PASS
   3.2 SPU(case20)+ARM(case20):PASS
   3.3 SPU(case21)+ARM(case21):PASS
   3.4 SPU(case34)+ARM(case5) :PASS
   3.5 SPU(case44)+ARM(case5) :PASS
2023-10-12 10:47:28 +08:00
lishuang.xie
d734e714d5 1. New Feature#1006
2. add case0 : LTE 2 ape testcase
3. add case20: NR  4 ape testcase
4. add case21: NR  8 ape testcase
5. add case22: LTE 8 ape testcase
6. add case50: PCIE EP: arm read cfg for phy
2023-08-23 16:02:18 +08:00