//******************** (C) COPYRIGHT 2022 SmartLogic******************************* // FileName : ucp_api_jesd.h // Author : Boheng Lin bhlin919@126.com // Date First Issued : 2023-03-04 14:37:50 PM // Last Modified : // Description : // ------------------------------------------------------------ // Modification History: // Version Date Author Modification Description // //********************************************************************************** #ifndef UCP_API_JESD_H_ #define UCP_API_JESD_H_ #include #include #include #ifdef __cplusplus extern "C" { #endif /** * \brief the max channels of trx */ #define MAX_UCP_JESD_TRX_CH (4) /** * \brief Data structure to hold UCP API State */ typedef enum ucp_jesd_States { UCP_JESD_STATE_POWERONRESET = 0x00, UCP_JESD_STATE_JSCTRLOK = 0x01, UCP_JESD_STATE_CRGOK = 0x02, UCP_JESD_STATE_SUBCTRLOK = 0x04, UCP_JESD_STATE_204COREOK = 0x08, UCP_JESD_STATE_PMAOK = 0x10, UCP_JESD_STATE_TIMEROK = 0x20, UCP_JESD_STATE_RUN = 0x40 } ucp_jesd_States_e; /** * \brief Data structure to ape working step */ typedef enum ucp_jesd_ApeWorkStep { UCP_JESD_APE_POWERONRESET = 0x00, UCP_JESD_APE_CLOCKGENRUN = 0x01, UCP_JESD_APE_CELLRUN = 0x02, } ucp_jesd_ApeWorkStep_e; /** * \brief Data structure to the level status of trx's control pins. */ typedef enum ucp_jesd_gpioEnableLevel { UCP_JESD_TRX_GPIO_DISABLE = 0x00, UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01, UCP_JESD_TRX_GPIO_VALID_LOW = 0x02, } ucp_jesd_gpioEnableLevel_e; /** * \brief Data structure to contrl pins of rf's trx */ typedef struct ucp_jesd_gpio { uint8_t port; uint8_t pin; uint8_t enableLevel; } ucp_jesd_gpio_t; typedef struct ucp_jesd_TrxGpio { ucp_jesd_gpio_t tx; ucp_jesd_gpio_t rx; ucp_jesd_gpio_t orx; } ucp_jesd_TrxGpio_t; /** * \brief Data structure to configure of trx's contrl pins */ typedef struct ucp_jesd_TrxGpioCfg { uint8_t maxCh; int32_t uldelay; int32_t dldelay; ucp_jesd_gpio_t triger; ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH]; } ucp_jesd_TrxGpioCfg_t; /** * \brief Data structure to hold digital clock settings */ typedef struct ucp_jesd_CommonSettings { uint32_t devClock_kHz; /*!< Device clock frequency in kHz */ uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ uint8_t jesdSubClass; } ucp_jesd_CommonSettings_t; /** * \brief Data structure to hold UCP JESD204b Framer configuration settings */ typedef struct ucp_jesd_FrmCfg { uint8_t enable; uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */ uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */ uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */ uint8_t jesd204E; /*!< JESD204C E parameter */ uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */ } ucp_jesd_FrmCfg_t; /** * \brief Data structure to hold the settings for the deframer configuration */ typedef struct ucp_jesd_DfrmCfg { uint8_t enable; uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */ uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */ uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */ uint8_t jesd204E; /*!< JESD204C E parameter */ uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */ } ucp_jesd_DfrmCfg_t; /** * \brief Data structure to hold ucp JESD Framer and Deframer configuration information */ typedef struct ucp_jesd_Init { ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */ ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */ ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */ } ucp_jesd_Init_t; /** * \brief get jesd module's version * * \param void * * \retval version. */ extern uint32_t UCP_API_JESD_Version(void); /** * \brief Sets up the ape work step * * \param step * UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value * UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value * UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value * * \retval none. */ extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step); /** * \brief Sets up the gpios of tx and rx * * \param setting * * \retval none. */ extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile); /** * \brief Sets up the ucp4008 jesd's para setting * * \param setting * * \retval none. */ extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting); /** * \brief Sets up the ucp4008 jesd's para setting * * \param setting * * \retval none. */ extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting); /** * \brief Sets up the ucp4008 jesd's para setting * * \param setting * * \retval none. */ extern void UCP_API_JESD_CellDelete (void); #ifdef __cplusplus } #endif #endif /* #ifndef UCP_API_JESD_H_ */