#ifndef __TPCS_H__ #define __TPCS_H__ #define TPCS_PMA_MMD_BaseAddress 0x090a0000 #define TPCS_PCS_MMD_BaseAddress 0x090d0000 #define TPCS_AN_MMD_BaseAddress 0x09100000 #define TPCS_VS_MMD1_BaseAddress 0x09130000 //#define TPCS_PMA_MMD_BaseAddress 0x10000 //#define TPCS_PCS_MMD_BaseAddress 0x30000 //#define TPCS_AN_MMD_BaseAddress 0x70000 //#define TPCS_VS_MMD1_BaseAddress 0x1e0000 #define TPCS_SR_PMA_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x0 ) #define TPCS_SR_PMA_STATUS1 (TPCS_PMA_MMD_BaseAddress + 4*0x1 ) #define TPCS_SR_PMA_DEV_ID_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2 ) #define TPCS_SR_PMA_DEV_ID_2 (TPCS_PMA_MMD_BaseAddress + 4*0x3 ) #define TPCS_SR_PMA_SPD_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x4 ) #define TPCS_SR_PMA_DEV_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0x5 ) #define TPCS_SR_PMA_DEV_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0x6 ) #define TPCS_SR_PMA_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x7 ) #define TPCS_SR_PMA_STATUS2 (TPCS_PMA_MMD_BaseAddress + 4*0x8 ) #define TPCS_SR_PMA_TX_DIS (TPCS_PMA_MMD_BaseAddress + 4*0x9 ) #define TPCS_SR_PMA_RX_SIG_DET (TPCS_PMA_MMD_BaseAddress + 4*0xa ) #define TPCS_SR_PMA_EXT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xb ) #define TPCS_SR_PMA_EXT_ABL1 (TPCS_PMA_MMD_BaseAddress + 4*0xd ) #define TPCS_SR_PMA_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0xe ) #define TPCS_SR_PMA_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0xf ) #define TPCS_SR_EEE_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x10 ) #define TPCS_SR_PMA_EXT_ABL2 (TPCS_PMA_MMD_BaseAddress + 4*0x13 ) #define TPCS_SR_PMA_KR_PMD_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x96 ) #define TPCS_SR_PMA_KR_PMD_STS (TPCS_PMA_MMD_BaseAddress + 4*0x97 ) #define TPCS_SR_PMA_KR_LP_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x98 ) #define TPCS_SR_PMA_KR_LP_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x99 ) #define TPCS_SR_PMA_KR_LD_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x9a ) #define TPCS_SR_PMA_KR_LD_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x9b ) #define TPCS_SR_PMA_KX_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xa0 ) #define TPCS_SR_PMA_KX_STS (TPCS_PMA_MMD_BaseAddress + 4*0xa1 ) #define TPCS_SR_PMA_KR_FEC_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xaa ) #define TPCS_SR_PMA_KR_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xab ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xac ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xad ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xae ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xaf ) #define TPCS_SR_PMA_RS_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xc8 ) #define TPCS_SR_PMA_RS_FEC_STATUS (TPCS_PMA_MMD_BaseAddress + 4*0xc9 ) #define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xca ) #define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcb ) #define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xcc ) #define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcd ) #define TPCS_SR_PMA_RS_FEC_LANE_MAP (TPCS_PMA_MMD_BaseAddress + 4*0xce ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd2 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd3 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd4 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd5 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd6 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd7 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd8 ) #define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd9 ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12c ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12d ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12e ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12f ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x130 ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x131 ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x132 ) #define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x133 ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bc ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bd ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2be ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2bf ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c0 ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c1 ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c2 ) #define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c3 ) #define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x44c ) #define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x44d ) #define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x44e ) #define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x44f ) #define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x4b0 ) #define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x4b1 ) #define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x4b2 ) #define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x4b3 ) #define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x514 ) #define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x515 ) #define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x516 ) #define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x517 ) #define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x578 ) #define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x579 ) #define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x57a ) #define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x57b ) #define TPCS_SR_PMA_LNK_TRN_PAT (TPCS_PMA_MMD_BaseAddress + 4*0x5aa ) #define TPCS_SR_PMA_LNK_TRN_PAT_LN1 (TPCS_PMA_MMD_BaseAddress + 4*0x5ab ) #define TPCS_SR_PMA_LNK_TRN_PAT_LN2 (TPCS_PMA_MMD_BaseAddress + 4*0x5ac ) #define TPCS_SR_PMA_LNK_TRN_PAT_LN3 (TPCS_PMA_MMD_BaseAddress + 4*0x5ad ) #define TPCS_SR_PMA_KR_TST_PAT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x5dc ) #define TPCS_SR_PMA_KR_TST_PAT_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5dd ) #define TPCS_SR_PMA_KR_SQUARE_WAVE_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5e6 ) #define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x640 ) #define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x641 ) #define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x642 ) #define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x643 ) #define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x6a4 ) #define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x6a5 ) #define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x6a6 ) #define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x6a7 ) #define TPCS_VR_PMA_DIG_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8000) #define TPCS_VR_PMA_KRTR_PRBS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8003) #define TPCS_VR_PMA_KRTR_PRBS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8004) #define TPCS_VR_PMA_KRTR_PRBS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x8005) #define TPCS_VR_PMA_KRTR_TIMER_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8006) #define TPCS_VR_PMA_KRTR_TIMER_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8007) #define TPCS_VR_PMA_DIG_STS (TPCS_PMA_MMD_BaseAddress + 4*0x8010) #define TPCS_VR_PMA_RX_LSTS (TPCS_PMA_MMD_BaseAddress + 4*0x8020) #define TPCS_VR_PMA_CWM00 (TPCS_PMA_MMD_BaseAddress + 4*0x80a3) #define TPCS_VR_PMA_CWM01 (TPCS_PMA_MMD_BaseAddress + 4*0x80a4) #define TPCS_VR_PMA_CWM02 (TPCS_PMA_MMD_BaseAddress + 4*0x80a5) #define TPCS_VR_PMA_CWM03 (TPCS_PMA_MMD_BaseAddress + 4*0x80a6) #define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b0) #define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b1) #define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b2) #define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b3) #define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b4) #define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b5) #define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b6) #define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b7) #define TPCS_VR_PMA_PHY_TX_EQ_STS0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b8) #define TPCS_VR_PMA_PHY_TX_EQ_STS1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b9) #define TPCS_VR_PMA_PHY_TX_EQ_STS2 (TPCS_PMA_MMD_BaseAddress + 4*0x80ba) #define TPCS_VR_PMA_PHY_TX_EQ_STS3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bb) #define TPCS_VR_PMA_KRTR_RX_EQ_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80bc) #define TPCS_VR_PMA_KRTR_RX_EQ_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80bd) #define TPCS_VR_PMA_KRTR_RX_EQ_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80be) #define TPCS_VR_PMA_KRTR_RX_EQ_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bf) #define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c0) #define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c1) #define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c2) #define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c3) #define TPCS_VR_PMA_PHY_RX_EQ_CEU0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c4) #define TPCS_VR_PMA_PHY_RX_EQ_CEU1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c5) #define TPCS_VR_PMA_PHY_RX_EQ_CEU2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c6) #define TPCS_VR_PMA_PHY_RX_EQ_CEU3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c7) #define TPCS_SR_PCS_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x0 ) #define TPCS_SR_PCS_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x1 ) #define TPCS_SR_PCS_DEV_ID1 (TPCS_PCS_MMD_BaseAddress + 4*0x2 ) #define TPCS_SR_PCS_DEV_ID2 (TPCS_PCS_MMD_BaseAddress + 4*0x3 ) #define TPCS_SR_PCS_SPD_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x4 ) #define TPCS_SR_PCS_DEV_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0x5 ) #define TPCS_SR_PCS_DEV_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0x6 ) #define TPCS_SR_PCS_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x7 ) #define TPCS_SR_PCS_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x8 ) #define TPCS_SR_PCS_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0xe ) #define TPCS_SR_PCS_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0xf ) #define TPCS_SR_PCS_EEE_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x14 ) #define TPCS_SR_PCS_EEE_WKERR (TPCS_PCS_MMD_BaseAddress + 4*0x16 ) #define TPCS_SR_PCS_LSTS (TPCS_PCS_MMD_BaseAddress + 4*0x18 ) #define TPCS_SR_PCS_BASER_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x20 ) #define TPCS_SR_PCS_BASER_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x21 ) #define TPCS_SR_PCS_TP_A0 (TPCS_PCS_MMD_BaseAddress + 4*0x22 ) #define TPCS_SR_PCS_TP_A1 (TPCS_PCS_MMD_BaseAddress + 4*0x23 ) #define TPCS_SR_PCS_TP_A2 (TPCS_PCS_MMD_BaseAddress + 4*0x24 ) #define TPCS_SR_PCS_TP_A3 (TPCS_PCS_MMD_BaseAddress + 4*0x25 ) #define TPCS_SR_PCS_TP_B0 (TPCS_PCS_MMD_BaseAddress + 4*0x26 ) #define TPCS_SR_PCS_TP_B1 (TPCS_PCS_MMD_BaseAddress + 4*0x27 ) #define TPCS_SR_PCS_TP_B2 (TPCS_PCS_MMD_BaseAddress + 4*0x28 ) #define TPCS_SR_PCS_TP_B3 (TPCS_PCS_MMD_BaseAddress + 4*0x29 ) #define TPCS_SR_PCS_TP_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x2a ) #define TPCS_SR_PCS_TP_ERRCTR (TPCS_PCS_MMD_BaseAddress + 4*0x2b ) #define TPCS_SR_PCS_BER_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2c ) #define TPCS_SR_PCS_ERR_BLK_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2d ) #define TPCS_SR_PCS_MLN_ALIGN_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x32 ) #define TPCS_SR_PCS_MLN_ALIGN_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x33 ) #define TPCS_SR_PCS_MLN_ALIGN_STS3 (TPCS_PCS_MMD_BaseAddress + 4*0x34 ) #define TPCS_SR_PCS_MLN_ALIGN_STS4 (TPCS_PCS_MMD_BaseAddress + 4*0x35 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE0 (TPCS_PCS_MMD_BaseAddress + 4*0xc8 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE1 (TPCS_PCS_MMD_BaseAddress + 4*0xc9 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE2 (TPCS_PCS_MMD_BaseAddress + 4*0xca ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE3 (TPCS_PCS_MMD_BaseAddress + 4*0xcb ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE4 (TPCS_PCS_MMD_BaseAddress + 4*0xcc ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE5 (TPCS_PCS_MMD_BaseAddress + 4*0xcd ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE6 (TPCS_PCS_MMD_BaseAddress + 4*0xce ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE7 (TPCS_PCS_MMD_BaseAddress + 4*0xcf ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE8 (TPCS_PCS_MMD_BaseAddress + 4*0xd0 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE9 (TPCS_PCS_MMD_BaseAddress + 4*0xd1 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE10 (TPCS_PCS_MMD_BaseAddress + 4*0xd2 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE11 (TPCS_PCS_MMD_BaseAddress + 4*0xd3 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE12 (TPCS_PCS_MMD_BaseAddress + 4*0xd4 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE13 (TPCS_PCS_MMD_BaseAddress + 4*0xd5 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE14 (TPCS_PCS_MMD_BaseAddress + 4*0xd6 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE15 (TPCS_PCS_MMD_BaseAddress + 4*0xd7 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE16 (TPCS_PCS_MMD_BaseAddress + 4*0xd8 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE17 (TPCS_PCS_MMD_BaseAddress + 4*0xd9 ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE18 (TPCS_PCS_MMD_BaseAddress + 4*0xda ) #define TPCS_SR_PCS_BIP_ERR_CNTR_LANE19 (TPCS_PCS_MMD_BaseAddress + 4*0xdb ) #define TPCS_SR_PCS_LANE0_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x190 ) #define TPCS_SR_PCS_LANE1_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x191 ) #define TPCS_SR_PCS_LANE2_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x192 ) #define TPCS_SR_PCS_LANE3_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x193 ) #define TPCS_SR_PCS_LANE4_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x194 ) #define TPCS_SR_PCS_LANE5_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x195 ) #define TPCS_SR_PCS_LANE6_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x196 ) #define TPCS_SR_PCS_LANE7_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x197 ) #define TPCS_SR_PCS_LANE8_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x198 ) #define TPCS_SR_PCS_LANE9_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x199 ) #define TPCS_SR_PCS_LANE10_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19a ) #define TPCS_SR_PCS_LANE11_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19b ) #define TPCS_SR_PCS_LANE12_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19c ) #define TPCS_SR_PCS_LANE13_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19d ) #define TPCS_SR_PCS_LANE14_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19e ) #define TPCS_SR_PCS_LANE15_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19f ) #define TPCS_SR_PCS_LANE16_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a0 ) #define TPCS_SR_PCS_LANE17_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a1 ) #define TPCS_SR_PCS_LANE18_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a2 ) #define TPCS_SR_PCS_LANE19_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a3 ) #define TPCS_VR_PCS_DIG_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x8000) #define TPCS_VR_PCS_DIG_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x8001) #define TPCS_VR_PCS_DIG_CTRL3 (TPCS_PCS_MMD_BaseAddress + 4*0x8003) #define TPCS_VR_PCS_DEBUG_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8005) #define TPCS_VR_PCS_EEE_MCTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8006) #define TPCS_VR_PCS_KR_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8007) #define TPCS_VR_PCS_EEE_TXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8008) #define TPCS_VR_PCS_EEE_RXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8009) #define TPCS_VR_PCS_EEE_MISC_TIMER (TPCS_PCS_MMD_BaseAddress + 4*0x800a) #define TPCS_VR_PCS_DIG_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8010) #define TPCS_VR_PCS_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x8018) #define TPCS_VR_PCS_SKW_OUT_OF_RANGE (TPCS_PCS_MMD_BaseAddress + 4*0x8019) #define TPCS_VR_PCS_ALT_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x801a) #define TPCS_VR_PCS_MISC_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8020) #define TPCS_SR_AN_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x0 ) #define TPCS_SR_AN_STS (TPCS_AN_MMD_BaseAddress + 4*0x1 ) #define TPCS_SR_AN_DEV_ID1 (TPCS_AN_MMD_BaseAddress + 4*0x2 ) #define TPCS_SR_AN_DEV_ID2 (TPCS_AN_MMD_BaseAddress + 4*0x3 ) #define TPCS_SR_AN_DEV_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0x5 ) #define TPCS_SR_AN_DEV_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0x6 ) #define TPCS_SR_AN_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0xe ) #define TPCS_SR_AN_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0xf ) #define TPCS_SR_AN_ADV1 (TPCS_AN_MMD_BaseAddress + 4*0x10 ) #define TPCS_SR_AN_ADV2 (TPCS_AN_MMD_BaseAddress + 4*0x11 ) #define TPCS_SR_AN_ADV3 (TPCS_AN_MMD_BaseAddress + 4*0x12 ) #define TPCS_SR_AN_LP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x13 ) #define TPCS_SR_AN_LP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x14 ) #define TPCS_SR_AN_LP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x15 ) #define TPCS_SR_AN_XNP_TX1 (TPCS_AN_MMD_BaseAddress + 4*0x16 ) #define TPCS_SR_AN_XNP_TX2 (TPCS_AN_MMD_BaseAddress + 4*0x17 ) #define TPCS_SR_AN_XNP_TX3 (TPCS_AN_MMD_BaseAddress + 4*0x18 ) #define TPCS_SR_AN_LP_XNP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x19 ) #define TPCS_SR_AN_LP_XNP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x1a ) #define TPCS_SR_AN_LP_XNP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x1b ) #define TPCS_SR_AN_COMP_STS (TPCS_AN_MMD_BaseAddress + 4*0x30 ) #define TPCS_SR_AN_EEE_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3c ) #define TPCS_SR_AN_EEE_LP_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3d ) #define TPCS_VR_AN_VR_DIG_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8000 ) #define TPCS_VR_AN_INTR_MSK (TPCS_AN_MMD_BaseAddress + 4*0x8001 ) #define TPCS_VR_AN_INTR (TPCS_AN_MMD_BaseAddress + 4*0x8002 ) #define TPCS_VR_AN_MODE_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8003 ) #define TPCS_VR_AN_TIMER_CTRL0 (TPCS_AN_MMD_BaseAddress + 4*0x8004 ) #define TPCS_VR_AN_TIMER_CTRL1 (TPCS_AN_MMD_BaseAddress + 4*0x8005 ) #define TPCS_SR_VSMMD_PMA_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x0 ) #define TPCS_SR_VSMMD_PMA_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x1 ) #define TPCS_SR_VSMMD_DEV_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x2 ) #define TPCS_SR_VSMMD_DEV_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x3 ) #define TPCS_SR_VSMMD_PCS_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x4 ) #define TPCS_SR_VSMMD_PCS_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x5 ) #define TPCS_SR_VSMMD_AN_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x6 ) #define TPCS_SR_VSMMD_AN_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x7 ) #define TPCS_SR_VSMMD_STS (TPCS_VS_MMD1_BaseAddress + 4*0x8 ) #define TPCS_SR_VSMMD_CTRL (TPCS_VS_MMD1_BaseAddress + 4*0x9 ) #define TPCS_SR_VSMMD_PKGID1 (TPCS_VS_MMD1_BaseAddress + 4*0xe ) #define TPCS_SR_VSMMD_PKGID2 (TPCS_VS_MMD1_BaseAddress + 4*0xf ) #endif