#ifndef __UCP_RFC_H__ #define __UCP_RFC_H__ #define RF_BASE_ADDR 0x04da0000 /*----------------------------------------------------- RF0_REG -------------------------------------------------------*/ #define RF_MODE_REG ( RF_BASE_ADDR + 0x00*4 ) #define IO_CTRL_REG ( RF_BASE_ADDR + 0x01*4 ) #define CG_CTRL_REG ( RF_BASE_ADDR + 0x02*4 ) #define ADC_STATUS_REG ( RF_BASE_ADDR + 0x04*4 ) #define ADC_CTRL_REG ( RF_BASE_ADDR + 0x05*4 ) #define ADC_DFMT_REG ( RF_BASE_ADDR + 0x06*4 ) #define ADC_EOF_REG ( RF_BASE_ADDR + 0x07*4 ) #define DP_PN_CG_REG ( RF_BASE_ADDR + 0x08*4 ) #define DAC_CTRL_REG ( RF_BASE_ADDR + 0x09*4 ) #define DAC_DIV_REG ( RF_BASE_ADDR + 0x0A*4 ) #define DAC_PAT1_REG ( RF_BASE_ADDR + 0x0B*4 ) #define DAC_PAT2_REG ( RF_BASE_ADDR + 0x0C*4 ) #define DAC_EOF_REG ( RF_BASE_ADDR + 0x0D*4 ) #define DP_BIAS_REG ( RF_BASE_ADDR + 0x10*4 ) #define DP_RTERM0_REG ( RF_BASE_ADDR + 0x11*4 ) #define DP_RTERM1_REG ( RF_BASE_ADDR + 0x12*4 ) #define CK_RTERM_REG ( RF_BASE_ADDR + 0x13*4 ) #define LVDS_EN_REG ( RF_BASE_ADDR + 0x14*4 ) #define LVDS_CM_REG ( RF_BASE_ADDR + 0x15*4 ) #define LVDS_TXDRV_REG ( RF_BASE_ADDR + 0x16*4 ) #define CMOS_IE_REG ( RF_BASE_ADDR + 0x17*4 ) #define CMOS_OE_REG ( RF_BASE_ADDR + 0x18*4 ) #define CMOS_PULL_REG ( RF_BASE_ADDR + 0x19*4 ) #define CMOS_SMT_REG ( RF_BASE_ADDR + 0x1A*4 ) #define CK_TUNING_REG ( RF_BASE_ADDR + 0x1B*4 ) #define FRM_TUNING_REG ( RF_BASE_ADDR + 0x1C*4 ) #define CMOS_TUNING0_REG ( RF_BASE_ADDR + 0x1D*4 ) #define CMOS_TUNING1_REG ( RF_BASE_ADDR + 0x1E*4 ) #define CMOS_TUNING2_REG ( RF_BASE_ADDR + 0x1F*4 ) #define CMOS_TUNING3_REG ( RF_BASE_ADDR + 0x20*4 ) #define CMOS_TUNING4_REG ( RF_BASE_ADDR + 0x21*4 ) #define CMOS_TUNING5_REG ( RF_BASE_ADDR + 0x22*4 ) #define LVDS_TUNING0_REG ( RF_BASE_ADDR + 0x23*4 ) #define LVDS_TUNING1_REG ( RF_BASE_ADDR + 0x24*4 ) #define LVDS_PMUX0_REG ( RF_BASE_ADDR + 0x25*4 ) #define LVDS_PMUX1_REG ( RF_BASE_ADDR + 0x26*4 ) /*----------------------------------------------------- RF common reg -------------------------------------------------------*/ #define PIN_CTRL_REG ( RF_BASE_ADDR + 0x5B*4 ) #define TMR_CTRL_REG ( RF_BASE_ADDR + 0x60*4 ) #define RF_INTC_REG ( RF_BASE_ADDR + 0x61*4 ) #define TMR_SCR_REQ_REG ( RF_BASE_ADDR + 0x62*4 ) /*----------------------------------------------------- timer0 reg -------------------------------------------------------*/ #define TMR_TEVENT_REG ( RF_BASE_ADDR + 0x80*4 ) #define TMR_TSCR_TRG_REG ( RF_BASE_ADDR + 0x81*4 ) #define TMR_TWREQ_REG ( RF_BASE_ADDR + 0x82*4 ) #define TMR_TINTE0_REG ( RF_BASE_ADDR + 0x83*4 ) #define TMR_TINTF0_REG ( RF_BASE_ADDR + 0x84*4 ) #define TMR_TINTE1_REG ( RF_BASE_ADDR + 0x85*4 ) #define TMR_TINTF1_REG ( RF_BASE_ADDR + 0x86*4 ) #define TMR_TINTE2_REG ( RF_BASE_ADDR + 0x87*4 ) #define TMR_TINTF2_REG ( RF_BASE_ADDR + 0x88*4 ) #define TMR_CEVENT_REG ( RF_BASE_ADDR + 0x89*4 ) #define TMR_CMSK_REG ( RF_BASE_ADDR + 0x8A*4 ) #define TMR_CINTE0_REG ( RF_BASE_ADDR + 0x8B*4 ) #define TMR_CINTF0_REG ( RF_BASE_ADDR + 0x8C*4 ) #define TMR_CINTE1_REG ( RF_BASE_ADDR + 0x8D*4 ) #define TMR_CINTF1_REG ( RF_BASE_ADDR + 0x8E*4 ) #define TMR_CINTE2_REG ( RF_BASE_ADDR + 0x8F*4 ) #define TMR_CINTF2_REG ( RF_BASE_ADDR + 0x90*4 ) #define TMR_OVFL_REG ( RF_BASE_ADDR + 0x91*4 ) #define TMR_OVFH_REG ( RF_BASE_ADDR + 0x92*4 ) #define TMR_RXDP_EN0L_REG ( RF_BASE_ADDR + 0x93*4 ) #define TMR_RXDP_EN0H_REG ( RF_BASE_ADDR + 0x94*4 ) #define TMR_RXDP_EN1L_REG ( RF_BASE_ADDR + 0x95*4 ) #define TMR_RXDP_EN1H_REG ( RF_BASE_ADDR + 0x96*4 ) #define TMR_TXDP_EN0L_REG ( RF_BASE_ADDR + 0x97*4 ) #define TMR_TXDP_EN0H_REG ( RF_BASE_ADDR + 0x98*4 ) #define TMR_TXDP_EN1L_REG ( RF_BASE_ADDR + 0x99*4 ) #define TMR_TXDP_EN1H_REG ( RF_BASE_ADDR + 0x9A*4 ) #define TMR_RXEOFL_REG ( RF_BASE_ADDR + 0x9B*4 ) #define TMR_RXEOFH_REG ( RF_BASE_ADDR + 0x9C*4 ) #define TMR_TXEOFL_REG ( RF_BASE_ADDR + 0x9D*4 ) #define TMR_TXEOFH_REG ( RF_BASE_ADDR + 0x9E*4 ) #define TMR_EN_CTRL0L_REG ( RF_BASE_ADDR + 0x9F*4 ) #define TMR_EN_CTRL0H_REG ( RF_BASE_ADDR + 0xA0*4 ) #define TMR_EN_CTRL1L_REG ( RF_BASE_ADDR + 0xA1*4 ) #define TMR_EN_CTRL1H_REG ( RF_BASE_ADDR + 0xA2*4 ) #define TMR_EN_CTRL2L_REG ( RF_BASE_ADDR + 0xA3*4 ) #define TMR_EN_CTRL2H_REG ( RF_BASE_ADDR + 0xA4*4 ) #define TMR_EN_CTRL3L_REG ( RF_BASE_ADDR + 0xA5*4 ) #define TMR_EN_CTRL3H_REG ( RF_BASE_ADDR + 0xA6*4 ) #define TMR_TXRX_CTRL0L_REG ( RF_BASE_ADDR + 0xA7*4 ) #define TMR_TXRX_CTRL0H_REG ( RF_BASE_ADDR + 0xA8*4 ) #define TMR_TXRX_CTRL1L_REG ( RF_BASE_ADDR + 0xA9*4 ) #define TMR_TXRX_CTRL1H_REG ( RF_BASE_ADDR + 0xAA*4 ) #define TMR_SCRATH0L_REG ( RF_BASE_ADDR + 0xAB*4 ) #define TMR_SCRATH0H_REG ( RF_BASE_ADDR + 0xAC*4 ) #define TMR_SCRATH1L_REG ( RF_BASE_ADDR + 0xAD*4 ) #define TMR_SCRATH1H_REG ( RF_BASE_ADDR + 0xAE*4 ) #define TMR_1PPSL_REG ( RF_BASE_ADDR + 0xAF*4 ) #define TMR_1PPSH_REG ( RF_BASE_ADDR + 0xB0*4 ) /*----------------------------------------------------- timer array -------------------------------------------------------*/ #define TMR0_ARRAY_BASE RF_BASE_ADDR+0x400 #define TMR_TNL_REG0 ( TMR0_ARRAY_BASE + 0x00*4 ) #define TMR_TNH_REG0 ( TMR0_ARRAY_BASE + 0x01*4 ) #define TMR_TNL_REG1 ( TMR0_ARRAY_BASE + 0x02*4 ) #define TMR_TNH_REG1 ( TMR0_ARRAY_BASE + 0x03*4 ) #define TMR_TNL_REG2 ( TMR0_ARRAY_BASE + 0x04*4 ) #define TMR_TNH_REG2 ( TMR0_ARRAY_BASE + 0x05*4 ) #define TMR_TNL_REG3 ( TMR0_ARRAY_BASE + 0x06*4 ) #define TMR_TNH_REG3 ( TMR0_ARRAY_BASE + 0x07*4 ) #define TMR_TNL_REG4 ( TMR0_ARRAY_BASE + 0x08*4 ) #define TMR_TNH_REG4 ( TMR0_ARRAY_BASE + 0x09*4 ) #define TMR_TNL_REG5 ( TMR0_ARRAY_BASE + 0x0A*4 ) #define TMR_TNH_REG5 ( TMR0_ARRAY_BASE + 0x0B*4 ) #define TMR_TNL_REG6 ( TMR0_ARRAY_BASE + 0x0C*4 ) #define TMR_TNH_REG6 ( TMR0_ARRAY_BASE + 0x0D*4 ) #define TMR_TNL_REG7 ( TMR0_ARRAY_BASE + 0x0E*4 ) #define TMR_TNH_REG7 ( TMR0_ARRAY_BASE + 0x0F*4 ) #define TMR_TNL_REG8 ( TMR0_ARRAY_BASE + 0x10*4 ) #define TMR_TNH_REG8 ( TMR0_ARRAY_BASE + 0x11*4 ) #define TMR_TNL_REG9 ( TMR0_ARRAY_BASE + 0x12*4 ) #define TMR_TNH_REG9 ( TMR0_ARRAY_BASE + 0x13*4 ) #define TMR_TNL_REG10 ( TMR0_ARRAY_BASE + 0x14*4 ) #define TMR_TNH_REG10 ( TMR0_ARRAY_BASE + 0x15*4 ) #define TMR_TNL_REG11 ( TMR0_ARRAY_BASE + 0x16*4 ) #define TMR_TNH_REG11 ( TMR0_ARRAY_BASE + 0x17*4 ) #define TMR_TNL_REG12 ( TMR0_ARRAY_BASE + 0x18*4 ) #define TMR_TNH_REG12 ( TMR0_ARRAY_BASE + 0x19*4 ) #define TMR_TNL_REG13 ( TMR0_ARRAY_BASE + 0x1A*4 ) #define TMR_TNH_REG13 ( TMR0_ARRAY_BASE + 0x1B*4 ) #define TMR_TNL_REG14 ( TMR0_ARRAY_BASE + 0x1C*4 ) #define TMR_TNH_REG14 ( TMR0_ARRAY_BASE + 0x1D*4 ) #define TMR_TNL_REG15 ( TMR0_ARRAY_BASE + 0x1E*4 ) #define TMR_TNH_REG15 ( TMR0_ARRAY_BASE + 0x1F*4 ) #define TMR_TNL_REG16 ( TMR0_ARRAY_BASE + 0x20*4 ) #define TMR_TNH_REG16 ( TMR0_ARRAY_BASE + 0x21*4 ) #define TMR_TNL_REG17 ( TMR0_ARRAY_BASE + 0x22*4 ) #define TMR_TNH_REG17 ( TMR0_ARRAY_BASE + 0x23*4 ) #define TMR_TNL_REG18 ( TMR0_ARRAY_BASE + 0x24*4 ) #define TMR_TNH_REG18 ( TMR0_ARRAY_BASE + 0x25*4 ) #define TMR_TNL_REG19 ( TMR0_ARRAY_BASE + 0x26*4 ) #define TMR_TNH_REG19 ( TMR0_ARRAY_BASE + 0x27*4 ) #define TMR_TNL_REG20 ( TMR0_ARRAY_BASE + 0x28*4 ) #define TMR_TNH_REG20 ( TMR0_ARRAY_BASE + 0x29*4 ) #define TMR_TNL_REG21 ( TMR0_ARRAY_BASE + 0x2A*4 ) #define TMR_TNH_REG21 ( TMR0_ARRAY_BASE + 0x2B*4 ) #define TMR_TNL_REG22 ( TMR0_ARRAY_BASE + 0x2C*4 ) #define TMR_TNH_REG22 ( TMR0_ARRAY_BASE + 0x2D*4 ) #define TMR_TNL_REG23 ( TMR0_ARRAY_BASE + 0x2E*4 ) #define TMR_TNH_REG23 ( TMR0_ARRAY_BASE + 0x2F*4 ) #define TMR_TNL_REG24 ( TMR0_ARRAY_BASE + 0x30*4 ) #define TMR_TNH_REG24 ( TMR0_ARRAY_BASE + 0x31*4 ) #define TMR_TNL_REG25 ( TMR0_ARRAY_BASE + 0x32*4 ) #define TMR_TNH_REG25 ( TMR0_ARRAY_BASE + 0x33*4 ) #define TMR_TNL_REG26 ( TMR0_ARRAY_BASE + 0x34*4 ) #define TMR_TNH_REG26 ( TMR0_ARRAY_BASE + 0x35*4 ) #define TMR_TNL_REG27 ( TMR0_ARRAY_BASE + 0x36*4 ) #define TMR_TNH_REG27 ( TMR0_ARRAY_BASE + 0x37*4 ) #define TMR_TNL_REG28 ( TMR0_ARRAY_BASE + 0x38*4 ) #define TMR_TNH_REG28 ( TMR0_ARRAY_BASE + 0x39*4 ) #define TMR_TNL_REG29 ( TMR0_ARRAY_BASE + 0x3A*4 ) #define TMR_TNH_REG29 ( TMR0_ARRAY_BASE + 0x3B*4 ) #define TMR_TNL_REG30 ( TMR0_ARRAY_BASE + 0x3C*4 ) #define TMR_TNH_REG30 ( TMR0_ARRAY_BASE + 0x3D*4 ) #define TMR_TNL_REG31 ( TMR0_ARRAY_BASE + 0x3E*4 ) #define TMR_TNH_REG31 ( TMR0_ARRAY_BASE + 0x3F*4 ) #define GPIO_PIN_BASE RF_BASE_ADDR+0x800 #define GPIO_PMUX0_REG ( GPIO_PIN_BASE + 0x00*4 ) #define GPIO_CTRL0_REG ( GPIO_PIN_BASE + 0x01*4 ) /*----------------------------------------------------- RF_REG MASK -------------------------------------------------------*/ /////RF_REG_mask///// #define RF_MODE_REG_MASK 0x800003FF #define IO_CTRL_REG_MASK 0x00000003 #define ADC_STATUS_REG_MASK 0x00000F0F #define ADC_CTRL_REG_MASK 0x3300010F #define ADC_DFMT_REG_MASK 0x00000FFF #define DAC_STATUS_REG_MASK 0xFF000000 #define ADC_EOF_REG_MASK 0xC0000000 #define DAC_CTRL_REG_MASK 0x0000030B #define DAC_DIV_REG_MASK 0x0000FFFF #define DAC_PAT1_REG_MASK 0xFFFFFFFF #define DAC_PAT2_REG_MASK 0xFFFFFFFF #define DAC_EOF_REG_MASK 0xC0000000 #define DP_BIAS_REG_MASK 0xFFFFFFFF #define DP_RTERM0_REG_MASK 0x3F777777 #define DP_RTERM1_REG_MASK 0x3F777777 #define CK_RTERM_REG_MASK 0x0000FFFF #define LVDS_EN_REG_MASK 0x00FF00FF //#define DEBUG_LVDS_REG_MASK 0x003F003F #define LVDS_CM_REG_MASK 0xFFFFFFFF #define LVDS_TXDRV_REG_MASK 0xFFFFFFFF #define CMOS_IE_REG_MASK 0xCFFF0FFF #define CMOS_OE_REG_MASK 0xCFFF0FFF #define CMOS_PULL_REG_MASK 0xF03F003F #define CMOS_SMT_REG_MASK 0xF03F003F #define CK_TUNING_REG_MASK 0x00000F0F #define FRM_TUNING_REG_MASK 0x000000FF #define CMOS_TUNING0_REG_MASK 0xFFFFFFFF #define CMOS_TUNING1_REG_MASK 0xFFFFFFFF #define CMOS_TUNING2_REG_MASK 0xFFFFFFFF #define CMOS_TUNING3_REG_MASK 0xFFFFFFFF #define CMOS_TUNING4_REG_MASK 0xFFFFFFFF #define CMOS_TUNING5_REG_MASK 0xFFFFFFFF #define LVDS_TUNING0_REG_MASK 0x00FFFFFF #define LVDS_TUNING1_REG_MASK 0x00FFFFFF #define LVDS_PMUX0_REG_MASK 0xFFFFFFFF #define LVDS_PMUX1_REG_MASK 0xFFFFFFFF #define PIN_CTRL_REG_MASK 0xC0007F7F //!!!0xC0003F3F #define SYNC_GEN_REG_MASK 0x00000001 #define SYNC_CTRL_REG_MASK 0x0000000F #define TMR_CTRL_REG_MASK 0x8000C303 #define RF_INTC_REG_MASK 0x00030000 #define TMR_SCR_REQ_REG_MASK 0x00000000 /////timer_reg_mask #define TMR_MASK 0x00000000 #define TMR_UNMASK 0xFFFFFFFF #define TMR_TSCR_TRG_MASK 0xFF000000 #define TMR_CEVENT_MASK 0x0000007F #define TMR_CMSK_MASK 0x00003333 #define TMR_CINTE_MASK 0x0000007F #define TMR_OVFH_MASK 0x3FFFFFFF #endif