/********************************************************************* * * Filename: ucp_pma.h * * Created: 2021-11-06 03:30:30 PM * Last Modified: 2022-01-22 02:50:47 PM * Author: LiPin , lip2014@ia.ac.cn * Organization: Beijing Smart Logic Technology Co., Ltd. * * Description: * * ********************************************************************/ #ifndef __PMA__ #define __PMA__ //The PMA Config Base Addr #define JS_PMA0_CFG 0x05f74000 #define JECS_PMA1_CFG 0x08484000 #define PET_PMA3_CFG 0x09204000 //------------------------JS0 SUBSYSTEM -------------------------// //The PMA Lane Config Base Addr #define JS_PMA0_LANE0_BASE JS_PMA0_CFG + 0x10000*4 #define JS_PMA0_LANE1_BASE JS_PMA0_CFG + 0x10800*4 #define JS_PMA0_LANE2_BASE JS_PMA0_CFG + 0x11000*4 #define JS_PMA0_LANE3_BASE JS_PMA0_CFG + 0x11800*4 #define JS_PMA0_BROADCAST_BASE JS_PMA0_CFG + 0x12000*4 //The PMA COMMON Base Addr #define JS_PMA0_COMMON_BASE JS_PMA0_CFG + 0x14000*4 //The PMA PCS Addr #define JS_PMA0_PCS_BASE JS_PMA0_CFG + 0x18000*4 //The PMA Lane Config Register #define JS_PMA0_LANE0_PMA_LOOPBACK_CTRL (JS_PMA0_LANE0_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ (JS_PMA0_LANE0_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x02) //Attributes : RO #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE0_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE0_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE0_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE0_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE0_BASE + 4*0x07) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE0_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE0_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE0_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_ADAPT_REQ (JS_PMA0_LANE0_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x11) //Attributes : RO #define JS_PMA0_LANE0_RECEIVER_ADAPT_DIR (JS_PMA0_LANE0_BASE + 4*0x12) //Attributes : RO #define JS_PMA0_LANE0_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE0_BASE + 4*0x13) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x14) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_DATAPATH_EN (JS_PMA0_LANE0_BASE + 4*0x20) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE0_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE0_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE0_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE0_BASE + 4*0x24) //Attributes : RO #define JS_PMA0_LANE0_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE0_BASE + 4*0x25) //Attributes : RO #define JS_PMA0_LANE0_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x26) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_RESET (JS_PMA0_LANE0_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_CONTROL (JS_PMA0_LANE0_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x32) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_RECAL_CTRL (JS_PMA0_LANE0_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_LANE0_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_REQ (JS_PMA0_LANE0_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_LANE0_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE0_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE0_BASE + 4*0x53) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x55) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE0_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE0_BASE + 4*0x61) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE0_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x63) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_CONTROL1 (JS_PMA0_LANE0_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_CONTROL2 (JS_PMA0_LANE0_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_EQ1 (JS_PMA0_LANE0_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_EQ2 (JS_PMA0_LANE0_BASE + 4*0x81) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_EQ3 (JS_PMA0_LANE0_BASE + 4*0x82) //Attributes : RW #define JS_PMA0_LANE0_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x83) //Attributes : RW #define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE0_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE0_BASE + 4*0x91) //Attributes : RW #define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE0_BASE + 4*0x92) //Attributes : RW #define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE0_BASE + 4*0x93) //Attributes : RW #define JS_PMA0_LANE0_CONTEXT_RESTORE_MUX (JS_PMA0_LANE0_BASE + 4*0x94) //Attributes : RW #define JS_PMA0_LANE0_LANE_REFCLK_SEL (JS_PMA0_LANE0_BASE + 4*0xA0) //Attributes : RW #define JS_PMA0_LANE0_ETH_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xB0) //Attributes : RW #define JS_PMA0_LANE0_ETH_CLK_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xB1) //Attributes : RW #define JS_PMA0_LANE0_RX_ADAPT_CTRL (JS_PMA0_LANE0_BASE + 4*0xC0) //Attributes : RW #define JS_PMA0_LANE0_RX_DCC_CTRL (JS_PMA0_LANE0_BASE + 4*0xC1) //Attributes : RW #define JS_PMA0_LANE0_RX_EQ_CTRL1 (JS_PMA0_LANE0_BASE + 4*0xC2) //Attributes : RW #define JS_PMA0_LANE0_RX_EQ_CTRL2 (JS_PMA0_LANE0_BASE + 4*0xC3) //Attributes : RW #define JS_PMA0_LANE0_RX_MARGIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xC4) //Attributes : RW #define JS_PMA0_LANE0_RX_MARGIN_ERROR (JS_PMA0_LANE0_BASE + 4*0xC5) //Attributes : RO #define JS_PMA0_LANE0_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xC6) //Attributes : RW #define JS_PMA0_LANE0_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE0_BASE + 4*0xC8) //Attributes : RW #define JS_PMA0_LANE0_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xC9) //Attributes : RW #define JS_PMA0_LANE0_RX_DIV_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xCA) //Attributes : RW #define JS_PMA0_LANE0_TX_DIV_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xCB) //Attributes : RW #define JS_PMA0_LANE0_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xCC) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_CTRL1 (JS_PMA0_LANE0_BASE + 4*0xD0) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_CTRL2 (JS_PMA0_LANE0_BASE + 4*0xD1) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_CTRL3 (JS_PMA0_LANE0_BASE + 4*0xD2) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_CTRL4 (JS_PMA0_LANE0_BASE + 4*0xD3) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_CTRL5 (JS_PMA0_LANE0_BASE + 4*0xD4) //Attributes : RW #define JS_PMA0_LANE0_TRANS_REQ_MUX (JS_PMA0_LANE0_BASE + 4*0xD5) //Attributes : RW #define JS_PMA0_LANE0_TRANS_INTERFACE_CTRL (JS_PMA0_LANE0_BASE + 4*0xD6) //Attributes : RW #define JS_PMA0_LANE0_TRANS_INTERFACE_MUX (JS_PMA0_LANE0_BASE + 4*0xD7) //Attributes : RW #define JS_PMA0_LANE0_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE0_BASE + 4*0xD8) //Attributes : RW #define JS_PMA0_LANE0_TRANS_PLL_STATE (JS_PMA0_LANE0_BASE + 4*0xD9) //Attributes : RO #define JS_PMA0_LANE0_PLL_STATE_MUX (JS_PMA0_LANE0_BASE + 4*0xDA) //Attributes : RW #define JS_PMA0_LANE0_RX_VALID_PHY (JS_PMA0_LANE0_BASE + 4*0xDF) //Attributes : RO #define JS_PMA0_LANE0_RX_VALID_MUX (JS_PMA0_LANE0_BASE + 4*0xE0) //Attributes : RW #define JS_PMA0_LANE0_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE0_BASE + 4*0xE1) //Attributes : RW #define JS_PMA0_LANE0_SRIO_DEGRADED (JS_PMA0_LANE0_BASE + 4*0xE2) //Attributes : RW #define JS_PMA0_LANE0_SRIO_RETRAIN (JS_PMA0_LANE0_BASE + 4*0xE3) //Attributes : RW #define JS_PMA0_LANE0_SRIO_SHORT_RUN (JS_PMA0_LANE0_BASE + 4*0xE4) //Attributes : RW #define JS_PMA0_LANE0_EQ_INIT_C0 (JS_PMA0_LANE0_BASE + 4*0xE5) //Attributes : RW #define JS_PMA0_LANE0_EQ_INIT_CN1 (JS_PMA0_LANE0_BASE + 4*0xE6) //Attributes : RW #define JS_PMA0_LANE0_EQ_INIT_CP1 (JS_PMA0_LANE0_BASE + 4*0xE7) //Attributes : RW #define JS_PMA0_LANE0_EQ_RULE_CTRL_1 (JS_PMA0_LANE0_BASE + 4*0xE8) //Attributes : RW #define JS_PMA0_LANE0_EQ_RULE_CTRL_2 (JS_PMA0_LANE0_BASE + 4*0xE9) //Attributes : RW #define JS_PMA0_LANE0_EQ_RULE_CTRL_3 (JS_PMA0_LANE0_BASE + 4*0xEA) //Attributes : RW #define JS_PMA0_LANE0_EQ_RULE_CTRL_4 (JS_PMA0_LANE0_BASE + 4*0xEB) //Attributes : RW #define JS_PMA0_LANE0_EQ_ALGORITHM_CTRL (JS_PMA0_LANE0_BASE + 4*0xEC) //Attributes : RW #define JS_PMA0_LANE0_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xED) //Attributes : RW #define JS_PMA0_LANE0_EQ_ADJ_INTERVAL (JS_PMA0_LANE0_BASE + 4*0xEE) //Attributes : RW #define JS_PMA0_LANE0_EQ_RX_REQ_CTRL (JS_PMA0_LANE0_BASE + 4*0xEF) //Attributes : RW #define JS_PMA0_LANE0_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_LANE0_EQ_RX_RESET_CYCLE (JS_PMA0_LANE0_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_LANE0_RPCS_KTR_STATUS (JS_PMA0_LANE0_BASE + 4*0xF2) //Attributes : RO #define JS_PMA0_LANE0_EQ_FSM (JS_PMA0_LANE0_BASE + 4*0xF3) //Attributes : RO #define JS_PMA0_LANE0_ETH_RX_LOS (JS_PMA0_LANE0_BASE + 4*0xF4) //Attributes : RW #define JS_PMA0_LANE0_EQ_PRESET_C0 (JS_PMA0_LANE0_BASE + 4*0xF5) //Attributes : RW #define JS_PMA0_LANE0_EQ_PRESET_CN1 (JS_PMA0_LANE0_BASE + 4*0xF6) //Attributes : RW #define JS_PMA0_LANE0_EQ_PRESET_CP1 (JS_PMA0_LANE0_BASE + 4*0xF7) //Attributes : RW #define JS_PMA0_LANE0_EQ_SUCC_MASK (JS_PMA0_LANE0_BASE + 4*0xF8) //Attributes : RW #define JS_PMA0_LANE0_PMA_COM_SCRATCH (JS_PMA0_LANE0_BASE + 4*0xff) //Attributes : RW #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x101) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x102) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x103) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x104) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x105) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x106) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x108) //Attributes : RW #define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT #define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x10D) //Attributes : RW #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x111) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x112) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x113) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x114) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x115) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x116) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x118) //Attributes : RW #define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x11D) //Attributes : RW #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x121) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x122) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x123) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x124) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x125) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x126) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x128) //Attributes : RW #define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x12D) //Attributes : RW #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x131) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x132) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x133) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x134) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x135) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x136) //Attributes : RO_EXT #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x138) //Attributes : RW #define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L #define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT #define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x13D) //Attributes : RW #define JS_PMA0_LANE1_PMA_LOOPBACK_CTRL (JS_PMA0_LANE1_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ (JS_PMA0_LANE1_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x02) //Attributes : RO #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE1_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE1_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE1_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE1_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE1_BASE + 4*0x07) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE1_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE1_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE1_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_ADAPT_REQ (JS_PMA0_LANE1_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x11) //Attributes : RO #define JS_PMA0_LANE1_RECEIVER_ADAPT_DIR (JS_PMA0_LANE1_BASE + 4*0x12) //Attributes : RO #define JS_PMA0_LANE1_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE1_BASE + 4*0x13) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x14) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_DATAPATH_EN (JS_PMA0_LANE1_BASE + 4*0x20) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE1_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE1_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE1_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE1_BASE + 4*0x24) //Attributes : RO #define JS_PMA0_LANE1_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE1_BASE + 4*0x25) //Attributes : RO #define JS_PMA0_LANE1_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x26) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_RESET (JS_PMA0_LANE1_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_CONTROL (JS_PMA0_LANE1_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x32) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_RECAL_CTRL (JS_PMA0_LANE1_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_LANE1_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_REQ (JS_PMA0_LANE1_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_LANE1_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE1_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE1_BASE + 4*0x53) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x55) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE1_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE1_BASE + 4*0x61) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE1_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x63) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_CONTROL1 (JS_PMA0_LANE1_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_CONTROL2 (JS_PMA0_LANE1_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_EQ1 (JS_PMA0_LANE1_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_EQ2 (JS_PMA0_LANE1_BASE + 4*0x81) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_EQ3 (JS_PMA0_LANE1_BASE + 4*0x82) //Attributes : RW #define JS_PMA0_LANE1_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x83) //Attributes : RW #define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE1_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE1_BASE + 4*0x91) //Attributes : RW #define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE1_BASE + 4*0x92) //Attributes : RW #define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE1_BASE + 4*0x93) //Attributes : RW #define JS_PMA0_LANE1_CONTEXT_RESTORE_MUX (JS_PMA0_LANE1_BASE + 4*0x94) //Attributes : RW #define JS_PMA0_LANE1_LANE_REFCLK_SEL (JS_PMA0_LANE1_BASE + 4*0xA0) //Attributes : RW #define JS_PMA0_LANE1_ETH_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xB0) //Attributes : RW #define JS_PMA0_LANE1_ETH_CLK_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xB1) //Attributes : RW #define JS_PMA0_LANE1_RX_ADAPT_CTRL (JS_PMA0_LANE1_BASE + 4*0xC0) //Attributes : RW #define JS_PMA0_LANE1_RX_DCC_CTRL (JS_PMA0_LANE1_BASE + 4*0xC1) //Attributes : RW #define JS_PMA0_LANE1_RX_EQ_CTRL1 (JS_PMA0_LANE1_BASE + 4*0xC2) //Attributes : RW #define JS_PMA0_LANE1_RX_EQ_CTRL2 (JS_PMA0_LANE1_BASE + 4*0xC3) //Attributes : RW #define JS_PMA0_LANE1_RX_MARGIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xC4) //Attributes : RW #define JS_PMA0_LANE1_RX_MARGIN_ERROR (JS_PMA0_LANE1_BASE + 4*0xC5) //Attributes : RO #define JS_PMA0_LANE1_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xC6) //Attributes : RW #define JS_PMA0_LANE1_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE1_BASE + 4*0xC8) //Attributes : RW #define JS_PMA0_LANE1_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xC9) //Attributes : RW #define JS_PMA0_LANE1_RX_DIV_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xCA) //Attributes : RW #define JS_PMA0_LANE1_TX_DIV_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xCB) //Attributes : RW #define JS_PMA0_LANE1_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xCC) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_CTRL1 (JS_PMA0_LANE1_BASE + 4*0xD0) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_CTRL2 (JS_PMA0_LANE1_BASE + 4*0xD1) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_CTRL3 (JS_PMA0_LANE1_BASE + 4*0xD2) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_CTRL4 (JS_PMA0_LANE1_BASE + 4*0xD3) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_CTRL5 (JS_PMA0_LANE1_BASE + 4*0xD4) //Attributes : RW #define JS_PMA0_LANE1_TRANS_REQ_MUX (JS_PMA0_LANE1_BASE + 4*0xD5) //Attributes : RW #define JS_PMA0_LANE1_TRANS_INTERFACE_CTRL (JS_PMA0_LANE1_BASE + 4*0xD6) //Attributes : RW #define JS_PMA0_LANE1_TRANS_INTERFACE_MUX (JS_PMA0_LANE1_BASE + 4*0xD7) //Attributes : RW #define JS_PMA0_LANE1_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE1_BASE + 4*0xD8) //Attributes : RW #define JS_PMA0_LANE1_TRANS_PLL_STATE (JS_PMA0_LANE1_BASE + 4*0xD9) //Attributes : RO #define JS_PMA0_LANE1_PLL_STATE_MUX (JS_PMA0_LANE1_BASE + 4*0xDA) //Attributes : RW #define JS_PMA0_LANE1_RX_VALID_PHY (JS_PMA0_LANE1_BASE + 4*0xDF) //Attributes : RO #define JS_PMA0_LANE1_RX_VALID_MUX (JS_PMA0_LANE1_BASE + 4*0xE0) //Attributes : RW #define JS_PMA0_LANE1_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE1_BASE + 4*0xE1) //Attributes : RW #define JS_PMA0_LANE1_SRIO_DEGRADED (JS_PMA0_LANE1_BASE + 4*0xE2) //Attributes : RW #define JS_PMA0_LANE1_SRIO_RETRAIN (JS_PMA0_LANE1_BASE + 4*0xE3) //Attributes : RW #define JS_PMA0_LANE1_SRIO_SHORT_RUN (JS_PMA0_LANE1_BASE + 4*0xE4) //Attributes : RW #define JS_PMA0_LANE1_EQ_INIT_C0 (JS_PMA0_LANE1_BASE + 4*0xE5) //Attributes : RW #define JS_PMA0_LANE1_EQ_INIT_CN1 (JS_PMA0_LANE1_BASE + 4*0xE6) //Attributes : RW #define JS_PMA0_LANE1_EQ_INIT_CP1 (JS_PMA0_LANE1_BASE + 4*0xE7) //Attributes : RW #define JS_PMA0_LANE1_EQ_RULE_CTRL_1 (JS_PMA0_LANE1_BASE + 4*0xE8) //Attributes : RW #define JS_PMA0_LANE1_EQ_RULE_CTRL_2 (JS_PMA0_LANE1_BASE + 4*0xE9) //Attributes : RW #define JS_PMA0_LANE1_EQ_RULE_CTRL_3 (JS_PMA0_LANE1_BASE + 4*0xEA) //Attributes : RW #define JS_PMA0_LANE1_EQ_RULE_CTRL_4 (JS_PMA0_LANE1_BASE + 4*0xEB) //Attributes : RW #define JS_PMA0_LANE1_EQ_ALGORITHM_CTRL (JS_PMA0_LANE1_BASE + 4*0xEC) //Attributes : RW #define JS_PMA0_LANE1_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xED) //Attributes : RW #define JS_PMA0_LANE1_EQ_ADJ_INTERVAL (JS_PMA0_LANE1_BASE + 4*0xEE) //Attributes : RW #define JS_PMA0_LANE1_EQ_RX_REQ_CTRL (JS_PMA0_LANE1_BASE + 4*0xEF) //Attributes : RW #define JS_PMA0_LANE1_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_LANE1_EQ_RX_RESET_CYCLE (JS_PMA0_LANE1_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_LANE1_RPCS_KTR_STATUS (JS_PMA0_LANE1_BASE + 4*0xF2) //Attributes : RO #define JS_PMA0_LANE1_EQ_FSM (JS_PMA0_LANE1_BASE + 4*0xF3) //Attributes : RO #define JS_PMA0_LANE1_ETH_RX_LOS (JS_PMA0_LANE1_BASE + 4*0xF4) //Attributes : RW #define JS_PMA0_LANE1_EQ_PRESET_C0 (JS_PMA0_LANE1_BASE + 4*0xF5) //Attributes : RW #define JS_PMA0_LANE1_EQ_PRESET_CN1 (JS_PMA0_LANE1_BASE + 4*0xF6) //Attributes : RW #define JS_PMA0_LANE1_EQ_PRESET_CP1 (JS_PMA0_LANE1_BASE + 4*0xF7) //Attributes : RW #define JS_PMA0_LANE1_EQ_SUCC_MASK (JS_PMA0_LANE1_BASE + 4*0xF8) //Attributes : RW #define JS_PMA0_LANE1_PMA_COM_SCRATCH (JS_PMA0_LANE1_BASE + 4*0xff) //Attributes : RW #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x101) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x102) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x103) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x104) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x105) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x106) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x108) //Attributes : RW #define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT #define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x10D) //Attributes : RW #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x111) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x112) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x113) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x114) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x115) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x116) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x118) //Attributes : RW #define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x11D) //Attributes : RW #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x121) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x122) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x123) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x124) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x125) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x126) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x128) //Attributes : RW #define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x12D) //Attributes : RW #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x131) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x132) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x133) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x134) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x135) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x136) //Attributes : RO_EXT #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x138) //Attributes : RW #define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L #define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT #define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x13D) //Attributes : RW #define JS_PMA0_LANE2_PMA_LOOPBACK_CTRL (JS_PMA0_LANE2_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ (JS_PMA0_LANE2_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x02) //Attributes : RO #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE2_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE2_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE2_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE2_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE2_BASE + 4*0x07) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE2_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE2_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE2_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_ADAPT_REQ (JS_PMA0_LANE2_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x11) //Attributes : RO #define JS_PMA0_LANE2_RECEIVER_ADAPT_DIR (JS_PMA0_LANE2_BASE + 4*0x12) //Attributes : RO #define JS_PMA0_LANE2_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE2_BASE + 4*0x13) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x14) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_DATAPATH_EN (JS_PMA0_LANE2_BASE + 4*0x20) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE2_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE2_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE2_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE2_BASE + 4*0x24) //Attributes : RO #define JS_PMA0_LANE2_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE2_BASE + 4*0x25) //Attributes : RO #define JS_PMA0_LANE2_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x26) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_RESET (JS_PMA0_LANE2_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_CONTROL (JS_PMA0_LANE2_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x32) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_RECAL_CTRL (JS_PMA0_LANE2_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_LANE2_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_REQ (JS_PMA0_LANE2_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_LANE2_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE2_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE2_BASE + 4*0x53) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x55) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE2_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE2_BASE + 4*0x61) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE2_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x63) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_CONTROL1 (JS_PMA0_LANE2_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_CONTROL2 (JS_PMA0_LANE2_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_EQ1 (JS_PMA0_LANE2_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_EQ2 (JS_PMA0_LANE2_BASE + 4*0x81) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_EQ3 (JS_PMA0_LANE2_BASE + 4*0x82) //Attributes : RW #define JS_PMA0_LANE2_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x83) //Attributes : RW #define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE2_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE2_BASE + 4*0x91) //Attributes : RW #define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE2_BASE + 4*0x92) //Attributes : RW #define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE2_BASE + 4*0x93) //Attributes : RW #define JS_PMA0_LANE2_CONTEXT_RESTORE_MUX (JS_PMA0_LANE2_BASE + 4*0x94) //Attributes : RW #define JS_PMA0_LANE2_LANE_REFCLK_SEL (JS_PMA0_LANE2_BASE + 4*0xA0) //Attributes : RW #define JS_PMA0_LANE2_ETH_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xB0) //Attributes : RW #define JS_PMA0_LANE2_ETH_CLK_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xB1) //Attributes : RW #define JS_PMA0_LANE2_RX_ADAPT_CTRL (JS_PMA0_LANE2_BASE + 4*0xC0) //Attributes : RW #define JS_PMA0_LANE2_RX_DCC_CTRL (JS_PMA0_LANE2_BASE + 4*0xC1) //Attributes : RW #define JS_PMA0_LANE2_RX_EQ_CTRL1 (JS_PMA0_LANE2_BASE + 4*0xC2) //Attributes : RW #define JS_PMA0_LANE2_RX_EQ_CTRL2 (JS_PMA0_LANE2_BASE + 4*0xC3) //Attributes : RW #define JS_PMA0_LANE2_RX_MARGIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xC4) //Attributes : RW #define JS_PMA0_LANE2_RX_MARGIN_ERROR (JS_PMA0_LANE2_BASE + 4*0xC5) //Attributes : RO #define JS_PMA0_LANE2_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xC6) //Attributes : RW #define JS_PMA0_LANE2_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE2_BASE + 4*0xC8) //Attributes : RW #define JS_PMA0_LANE2_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xC9) //Attributes : RW #define JS_PMA0_LANE2_RX_DIV_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xCA) //Attributes : RW #define JS_PMA0_LANE2_TX_DIV_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xCB) //Attributes : RW #define JS_PMA0_LANE2_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xCC) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_CTRL1 (JS_PMA0_LANE2_BASE + 4*0xD0) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_CTRL2 (JS_PMA0_LANE2_BASE + 4*0xD1) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_CTRL3 (JS_PMA0_LANE2_BASE + 4*0xD2) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_CTRL4 (JS_PMA0_LANE2_BASE + 4*0xD3) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_CTRL5 (JS_PMA0_LANE2_BASE + 4*0xD4) //Attributes : RW #define JS_PMA0_LANE2_TRANS_REQ_MUX (JS_PMA0_LANE2_BASE + 4*0xD5) //Attributes : RW #define JS_PMA0_LANE2_TRANS_INTERFACE_CTRL (JS_PMA0_LANE2_BASE + 4*0xD6) //Attributes : RW #define JS_PMA0_LANE2_TRANS_INTERFACE_MUX (JS_PMA0_LANE2_BASE + 4*0xD7) //Attributes : RW #define JS_PMA0_LANE2_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE2_BASE + 4*0xD8) //Attributes : RW #define JS_PMA0_LANE2_TRANS_PLL_STATE (JS_PMA0_LANE2_BASE + 4*0xD9) //Attributes : RO #define JS_PMA0_LANE2_PLL_STATE_MUX (JS_PMA0_LANE2_BASE + 4*0xDA) //Attributes : RW #define JS_PMA0_LANE2_RX_VALID_PHY (JS_PMA0_LANE2_BASE + 4*0xDF) //Attributes : RO #define JS_PMA0_LANE2_RX_VALID_MUX (JS_PMA0_LANE2_BASE + 4*0xE0) //Attributes : RW #define JS_PMA0_LANE2_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE2_BASE + 4*0xE1) //Attributes : RW #define JS_PMA0_LANE2_SRIO_DEGRADED (JS_PMA0_LANE2_BASE + 4*0xE2) //Attributes : RW #define JS_PMA0_LANE2_SRIO_RETRAIN (JS_PMA0_LANE2_BASE + 4*0xE3) //Attributes : RW #define JS_PMA0_LANE2_SRIO_SHORT_RUN (JS_PMA0_LANE2_BASE + 4*0xE4) //Attributes : RW #define JS_PMA0_LANE2_EQ_INIT_C0 (JS_PMA0_LANE2_BASE + 4*0xE5) //Attributes : RW #define JS_PMA0_LANE2_EQ_INIT_CN1 (JS_PMA0_LANE2_BASE + 4*0xE6) //Attributes : RW #define JS_PMA0_LANE2_EQ_INIT_CP1 (JS_PMA0_LANE2_BASE + 4*0xE7) //Attributes : RW #define JS_PMA0_LANE2_EQ_RULE_CTRL_1 (JS_PMA0_LANE2_BASE + 4*0xE8) //Attributes : RW #define JS_PMA0_LANE2_EQ_RULE_CTRL_2 (JS_PMA0_LANE2_BASE + 4*0xE9) //Attributes : RW #define JS_PMA0_LANE2_EQ_RULE_CTRL_3 (JS_PMA0_LANE2_BASE + 4*0xEA) //Attributes : RW #define JS_PMA0_LANE2_EQ_RULE_CTRL_4 (JS_PMA0_LANE2_BASE + 4*0xEB) //Attributes : RW #define JS_PMA0_LANE2_EQ_ALGORITHM_CTRL (JS_PMA0_LANE2_BASE + 4*0xEC) //Attributes : RW #define JS_PMA0_LANE2_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xED) //Attributes : RW #define JS_PMA0_LANE2_EQ_ADJ_INTERVAL (JS_PMA0_LANE2_BASE + 4*0xEE) //Attributes : RW #define JS_PMA0_LANE2_EQ_RX_REQ_CTRL (JS_PMA0_LANE2_BASE + 4*0xEF) //Attributes : RW #define JS_PMA0_LANE2_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_LANE2_EQ_RX_RESET_CYCLE (JS_PMA0_LANE2_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_LANE2_RPCS_KTR_STATUS (JS_PMA0_LANE2_BASE + 4*0xF2) //Attributes : RO #define JS_PMA0_LANE2_EQ_FSM (JS_PMA0_LANE2_BASE + 4*0xF3) //Attributes : RO #define JS_PMA0_LANE2_ETH_RX_LOS (JS_PMA0_LANE2_BASE + 4*0xF4) //Attributes : RW #define JS_PMA0_LANE2_EQ_PRESET_C0 (JS_PMA0_LANE2_BASE + 4*0xF5) //Attributes : RW #define JS_PMA0_LANE2_EQ_PRESET_CN1 (JS_PMA0_LANE2_BASE + 4*0xF6) //Attributes : RW #define JS_PMA0_LANE2_EQ_PRESET_CP1 (JS_PMA0_LANE2_BASE + 4*0xF7) //Attributes : RW #define JS_PMA0_LANE2_EQ_SUCC_MASK (JS_PMA0_LANE2_BASE + 4*0xF8) //Attributes : RW #define JS_PMA0_LANE2_PMA_COM_SCRATCH (JS_PMA0_LANE2_BASE + 4*0xFF) //Attributes : RW #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x101) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x102) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x103) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x104) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x105) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x106) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x108) //Attributes : RW #define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT #define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x10D) //Attributes : RW #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x111) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x112) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x113) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x114) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x115) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x116) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x118) //Attributes : RW #define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x11D) //Attributes : RW #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x121) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x122) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x123) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x124) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x125) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x126) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x128) //Attributes : RW #define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x12D) //Attributes : RW #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x131) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x132) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x133) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x134) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x135) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x136) //Attributes : RO_EXT #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x138) //Attributes : RW #define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L #define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT #define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x13D) //Attributes : RW #define JS_PMA0_LANE3_PMA_LOOPBACK_CTRL (JS_PMA0_LANE3_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ (JS_PMA0_LANE3_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x02) //Attributes : RO #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE3_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE3_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE3_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE3_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE3_BASE + 4*0x07) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE3_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE3_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE3_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_ADAPT_REQ (JS_PMA0_LANE3_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x11) //Attributes : RO #define JS_PMA0_LANE3_RECEIVER_ADAPT_DIR (JS_PMA0_LANE3_BASE + 4*0x12) //Attributes : RO #define JS_PMA0_LANE3_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE3_BASE + 4*0x13) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x14) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_DATAPATH_EN (JS_PMA0_LANE3_BASE + 4*0x20) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE3_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE3_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE3_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE3_BASE + 4*0x24) //Attributes : RO #define JS_PMA0_LANE3_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE3_BASE + 4*0x25) //Attributes : RO #define JS_PMA0_LANE3_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x26) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_RESET (JS_PMA0_LANE3_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_CONTROL (JS_PMA0_LANE3_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x32) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_RECAL_CTRL (JS_PMA0_LANE3_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_LANE3_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_REQ (JS_PMA0_LANE3_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_LANE3_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE3_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE3_BASE + 4*0x53) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x55) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE3_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE3_BASE + 4*0x61) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE3_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x63) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_CONTROL1 (JS_PMA0_LANE3_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_CONTROL2 (JS_PMA0_LANE3_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_EQ1 (JS_PMA0_LANE3_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_EQ2 (JS_PMA0_LANE3_BASE + 4*0x81) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_EQ3 (JS_PMA0_LANE3_BASE + 4*0x82) //Attributes : RW #define JS_PMA0_LANE3_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x83) //Attributes : RW #define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE3_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE3_BASE + 4*0x91) //Attributes : RW #define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE3_BASE + 4*0x92) //Attributes : RW #define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE3_BASE + 4*0x93) //Attributes : RW #define JS_PMA0_LANE3_CONTEXT_RESTORE_MUX (JS_PMA0_LANE3_BASE + 4*0x94) //Attributes : RW #define JS_PMA0_LANE3_LANE_REFCLK_SEL (JS_PMA0_LANE3_BASE + 4*0xA0) //Attributes : RW #define JS_PMA0_LANE3_ETH_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xB0) //Attributes : RW #define JS_PMA0_LANE3_ETH_CLK_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xB1) //Attributes : RW #define JS_PMA0_LANE3_RX_ADAPT_CTRL (JS_PMA0_LANE3_BASE + 4*0xC0) //Attributes : RW #define JS_PMA0_LANE3_RX_DCC_CTRL (JS_PMA0_LANE3_BASE + 4*0xC1) //Attributes : RW #define JS_PMA0_LANE3_RX_EQ_CTRL1 (JS_PMA0_LANE3_BASE + 4*0xC2) //Attributes : RW #define JS_PMA0_LANE3_RX_EQ_CTRL2 (JS_PMA0_LANE3_BASE + 4*0xC3) //Attributes : RW #define JS_PMA0_LANE3_RX_MARGIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xC4) //Attributes : RW #define JS_PMA0_LANE3_RX_MARGIN_ERROR (JS_PMA0_LANE3_BASE + 4*0xC5) //Attributes : RO #define JS_PMA0_LANE3_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xC6) //Attributes : RW #define JS_PMA0_LANE3_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE3_BASE + 4*0xC8) //Attributes : RW #define JS_PMA0_LANE3_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xC9) //Attributes : RW #define JS_PMA0_LANE3_RX_DIV_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xCA) //Attributes : RW #define JS_PMA0_LANE3_TX_DIV_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xCB) //Attributes : RW #define JS_PMA0_LANE3_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xCC) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_CTRL1 (JS_PMA0_LANE3_BASE + 4*0xD0) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_CTRL2 (JS_PMA0_LANE3_BASE + 4*0xD1) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_CTRL3 (JS_PMA0_LANE3_BASE + 4*0xD2) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_CTRL4 (JS_PMA0_LANE3_BASE + 4*0xD3) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_CTRL5 (JS_PMA0_LANE3_BASE + 4*0xD4) //Attributes : RW #define JS_PMA0_LANE3_TRANS_REQ_MUX (JS_PMA0_LANE3_BASE + 4*0xD5) //Attributes : RW #define JS_PMA0_LANE3_TRANS_INTERFACE_CTRL (JS_PMA0_LANE3_BASE + 4*0xD6) //Attributes : RW #define JS_PMA0_LANE3_TRANS_INTERFACE_MUX (JS_PMA0_LANE3_BASE + 4*0xD7) //Attributes : RW #define JS_PMA0_LANE3_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE3_BASE + 4*0xD8) //Attributes : RW #define JS_PMA0_LANE3_TRANS_PLL_STATE (JS_PMA0_LANE3_BASE + 4*0xD9) //Attributes : RO #define JS_PMA0_LANE3_PLL_STATE_MUX (JS_PMA0_LANE3_BASE + 4*0xDA) //Attributes : RW #define JS_PMA0_LANE3_RX_VALID_PHY (JS_PMA0_LANE3_BASE + 4*0xDF) //Attributes : RO #define JS_PMA0_LANE3_RX_VALID_MUX (JS_PMA0_LANE3_BASE + 4*0xE0) //Attributes : RW #define JS_PMA0_LANE3_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE3_BASE + 4*0xE1) //Attributes : RW #define JS_PMA0_LANE3_SRIO_DEGRADED (JS_PMA0_LANE3_BASE + 4*0xE2) //Attributes : RW #define JS_PMA0_LANE3_SRIO_RETRAIN (JS_PMA0_LANE3_BASE + 4*0xE3) //Attributes : RW #define JS_PMA0_LANE3_SRIO_SHORT_RUN (JS_PMA0_LANE3_BASE + 4*0xE4) //Attributes : RW #define JS_PMA0_LANE3_EQ_INIT_C0 (JS_PMA0_LANE3_BASE + 4*0xE5) //Attributes : RW #define JS_PMA0_LANE3_EQ_INIT_CN1 (JS_PMA0_LANE3_BASE + 4*0xE6) //Attributes : RW #define JS_PMA0_LANE3_EQ_INIT_CP1 (JS_PMA0_LANE3_BASE + 4*0xE7) //Attributes : RW #define JS_PMA0_LANE3_EQ_RULE_CTRL_1 (JS_PMA0_LANE3_BASE + 4*0xE8) //Attributes : RW #define JS_PMA0_LANE3_EQ_RULE_CTRL_2 (JS_PMA0_LANE3_BASE + 4*0xE9) //Attributes : RW #define JS_PMA0_LANE3_EQ_RULE_CTRL_3 (JS_PMA0_LANE3_BASE + 4*0xEA) //Attributes : RW #define JS_PMA0_LANE3_EQ_RULE_CTRL_4 (JS_PMA0_LANE3_BASE + 4*0xEB) //Attributes : RW #define JS_PMA0_LANE3_EQ_ALGORITHM_CTRL (JS_PMA0_LANE3_BASE + 4*0xEC) //Attributes : RW #define JS_PMA0_LANE3_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xED) //Attributes : RW #define JS_PMA0_LANE3_EQ_ADJ_INTERVAL (JS_PMA0_LANE3_BASE + 4*0xEE) //Attributes : RW #define JS_PMA0_LANE3_EQ_RX_REQ_CTRL (JS_PMA0_LANE3_BASE + 4*0xEF) //Attributes : RW #define JS_PMA0_LANE3_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_LANE3_EQ_RX_RESET_CYCLE (JS_PMA0_LANE3_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_LANE3_RPCS_KTR_STATUS (JS_PMA0_LANE3_BASE + 4*0xF2) //Attributes : RO #define JS_PMA0_LANE3_EQ_FSM (JS_PMA0_LANE3_BASE + 4*0xF3) //Attributes : RO #define JS_PMA0_LANE3_ETH_RX_LOS (JS_PMA0_LANE3_BASE + 4*0xF4) //Attributes : RW #define JS_PMA0_LANE3_EQ_PRESET_C0 (JS_PMA0_LANE3_BASE + 4*0xF5) //Attributes : RW #define JS_PMA0_LANE3_EQ_PRESET_CN1 (JS_PMA0_LANE3_BASE + 4*0xF6) //Attributes : RW #define JS_PMA0_LANE3_EQ_PRESET_CP1 (JS_PMA0_LANE3_BASE + 4*0xF7) //Attributes : RW #define JS_PMA0_LANE3_EQ_SUCC_MASK (JS_PMA0_LANE3_BASE + 4*0xF8) //Attributes : RW #define JS_PMA0_LANE3_PMA_COM_SCRATCH (JS_PMA0_LANE3_BASE + 4*0xff) //Attributes : RW #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x101) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x102) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x103) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x104) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x105) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x106) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x108) //Attributes : RW #define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT #define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x10D) //Attributes : RW #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x111) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x112) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x113) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x114) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x115) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x116) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x118) //Attributes : RW #define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x11D) //Attributes : RW #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x121) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x122) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x123) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x124) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x125) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x126) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x128) //Attributes : RW #define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x12D) //Attributes : RW #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x131) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x132) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x133) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x134) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x135) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x136) //Attributes : RO_EXT #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x138) //Attributes : RW #define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L #define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT #define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x13D) //Attributes : RW #define JS_PMA0_BROADCAST_PMA_LOOPBACK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ (JS_PMA0_BROADCAST_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x02) //Attributes : RO #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM2 (JS_PMA0_BROADCAST_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM3 (JS_PMA0_BROADCAST_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM4 (JS_PMA0_BROADCAST_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM5 (JS_PMA0_BROADCAST_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM6 (JS_PMA0_BROADCAST_BASE + 4*0x07) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7 (JS_PMA0_BROADCAST_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM8 (JS_PMA0_BROADCAST_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM9 (JS_PMA0_BROADCAST_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_REQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_ADAPT_REQ (JS_PMA0_BROADCAST_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x11) //Attributes : RO #define JS_PMA0_BROADCAST_RECEIVER_ADAPT_DIR (JS_PMA0_BROADCAST_BASE + 4*0x12) //Attributes : RO #define JS_PMA0_BROADCAST_RECEIVER_ADAPT_SETTING (JS_PMA0_BROADCAST_BASE + 4*0x13) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x14) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_EN (JS_PMA0_BROADCAST_BASE + 4*0x20) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_BROADCAST_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_BROADCAST_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_BROADCAST_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_BROADCAST_BASE + 4*0x24) //Attributes : RO #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_BROADCAST_BASE + 4*0x25) //Attributes : RO #define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x26) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_RESET (JS_PMA0_BROADCAST_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_CONTROL (JS_PMA0_BROADCAST_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x32) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_RECAL_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_BROADCAST_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_REQ (JS_PMA0_BROADCAST_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1 (JS_PMA0_BROADCAST_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM2 (JS_PMA0_BROADCAST_BASE + 4*0x53) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x55) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_EN (JS_PMA0_BROADCAST_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_BROADCAST_BASE + 4*0x61) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_BROADCAST_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x63) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL1 (JS_PMA0_BROADCAST_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL2 (JS_PMA0_BROADCAST_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_EQ1 (JS_PMA0_BROADCAST_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_EQ2 (JS_PMA0_BROADCAST_BASE + 4*0x81) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_EQ3 (JS_PMA0_BROADCAST_BASE + 4*0x82) //Attributes : RW #define JS_PMA0_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x83) //Attributes : RW #define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0x91) //Attributes : RW #define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL3 (JS_PMA0_BROADCAST_BASE + 4*0x92) //Attributes : RW #define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL4 (JS_PMA0_BROADCAST_BASE + 4*0x93) //Attributes : RW #define JS_PMA0_BROADCAST_CONTEXT_RESTORE_MUX (JS_PMA0_BROADCAST_BASE + 4*0x94) //Attributes : RW #define JS_PMA0_BROADCAST_LANE_REFCLK_SEL (JS_PMA0_BROADCAST_BASE + 4*0xA0) //Attributes : RW #define JS_PMA0_BROADCAST_ETH_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xB0) //Attributes : RW #define JS_PMA0_BROADCAST_ETH_CLK_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xB1) //Attributes : RW #define JS_PMA0_BROADCAST_RX_ADAPT_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC0) //Attributes : RW #define JS_PMA0_BROADCAST_RX_DCC_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC1) //Attributes : RW #define JS_PMA0_BROADCAST_RX_EQ_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0xC2) //Attributes : RW #define JS_PMA0_BROADCAST_RX_EQ_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0xC3) //Attributes : RW #define JS_PMA0_BROADCAST_RX_MARGIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC4) //Attributes : RW #define JS_PMA0_BROADCAST_RX_MARGIN_ERROR (JS_PMA0_BROADCAST_BASE + 4*0xC5) //Attributes : RO #define JS_PMA0_BROADCAST_RECV_REQUEST_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xC6) //Attributes : RW #define JS_PMA0_BROADCAST_RX_COARSE_ADAPT_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC8) //Attributes : RW #define JS_PMA0_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xC9) //Attributes : RW #define JS_PMA0_BROADCAST_RX_DIV_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xCA) //Attributes : RW #define JS_PMA0_BROADCAST_TX_DIV_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xCB) //Attributes : RW #define JS_PMA0_BROADCAST_MULTI_CLK_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xCC) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0xD0) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0xD1) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_CTRL3 (JS_PMA0_BROADCAST_BASE + 4*0xD2) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_CTRL4 (JS_PMA0_BROADCAST_BASE + 4*0xD3) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_CTRL5 (JS_PMA0_BROADCAST_BASE + 4*0xD4) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_REQ_MUX (JS_PMA0_BROADCAST_BASE + 4*0xD5) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_INTERFACE_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xD6) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_INTERFACE_MUX (JS_PMA0_BROADCAST_BASE + 4*0xD7) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_MASTER_PLL_STATE (JS_PMA0_BROADCAST_BASE + 4*0xD8) //Attributes : RW #define JS_PMA0_BROADCAST_TRANS_PLL_STATE (JS_PMA0_BROADCAST_BASE + 4*0xD9) //Attributes : RO #define JS_PMA0_BROADCAST_PLL_STATE_MUX (JS_PMA0_BROADCAST_BASE + 4*0xDA) //Attributes : RW #define JS_PMA0_BROADCAST_RX_VALID_PHY (JS_PMA0_BROADCAST_BASE + 4*0xDF) //Attributes : RO #define JS_PMA0_BROADCAST_RX_VALID_MUX (JS_PMA0_BROADCAST_BASE + 4*0xE0) //Attributes : RW #define JS_PMA0_BROADCAST_RX_SRIO_SIGDET_MUX (JS_PMA0_BROADCAST_BASE + 4*0xE1) //Attributes : RW #define JS_PMA0_BROADCAST_SRIO_DEGRADED (JS_PMA0_BROADCAST_BASE + 4*0xE2) //Attributes : RW #define JS_PMA0_BROADCAST_SRIO_RETRAIN (JS_PMA0_BROADCAST_BASE + 4*0xE3) //Attributes : RW #define JS_PMA0_BROADCAST_SRIO_SHORT_RUN (JS_PMA0_BROADCAST_BASE + 4*0xE4) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_INIT_C0 (JS_PMA0_BROADCAST_BASE + 4*0xE5) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_INIT_CN1 (JS_PMA0_BROADCAST_BASE + 4*0xE6) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_INIT_CP1 (JS_PMA0_BROADCAST_BASE + 4*0xE7) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RULE_CTRL_1 (JS_PMA0_BROADCAST_BASE + 4*0xE8) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RULE_CTRL_2 (JS_PMA0_BROADCAST_BASE + 4*0xE9) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RULE_CTRL_3 (JS_PMA0_BROADCAST_BASE + 4*0xEA) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RULE_CTRL_4 (JS_PMA0_BROADCAST_BASE + 4*0xEB) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_ALGORITHM_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xEC) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_TX_TRAIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xED) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_ADJ_INTERVAL (JS_PMA0_BROADCAST_BASE + 4*0xEE) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RX_REQ_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xEF) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RX_TRAIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RX_RESET_CYCLE (JS_PMA0_BROADCAST_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_BROADCAST_RPCS_KTR_STATUS (JS_PMA0_BROADCAST_BASE + 4*0xF2) //Attributes : RO #define JS_PMA0_BROADCAST_EQ_FSM (JS_PMA0_BROADCAST_BASE + 4*0xF3) //Attributes : RO #define JS_PMA0_BROADCAST_ETH_RX_LOS (JS_PMA0_BROADCAST_BASE + 4*0xF4) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_PRESET_C0 (JS_PMA0_BROADCAST_BASE + 4*0xF5) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_PRESET_CN1 (JS_PMA0_BROADCAST_BASE + 4*0xF6) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_PRESET_CP1 (JS_PMA0_BROADCAST_BASE + 4*0xF7) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_SUCC_MASK (JS_PMA0_BROADCAST_BASE + 4*0xF8) //Attributes : RW #define JS_PMA0_BROADCAST_PMA_COM_SCRATCH (JS_PMA0_BROADCAST_BASE + 4*0xff) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x108) //Attributes : RW #define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x10D) //Attributes : RW #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x118) //Attributes : RW #define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x11D) //Attributes : RW #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x128) //Attributes : RW #define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x12D) //Attributes : RW #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x138) //Attributes : RW #define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L #define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT #define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x13D) //Attributes : RW //The PMA COMMON Register #define JS_PMA0_MPLLA_PARAM1 (JS_PMA0_COMMON_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_MPLLA_PARAM2 (JS_PMA0_COMMON_BASE + 4*0x01) //Attributes : RW #define JS_PMA0_MPLLA_PARAM3 (JS_PMA0_COMMON_BASE + 4*0x02) //Attributes : RW #define JS_PMA0_MPLLA_PARAM4 (JS_PMA0_COMMON_BASE + 4*0x03) //Attributes : RW #define JS_PMA0_MPLLA_PARAM5 (JS_PMA0_COMMON_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_MPLLA_PARAM6 (JS_PMA0_COMMON_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_MPLLA_FORCE_EN (JS_PMA0_COMMON_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_MPLLA_FORCE_ACK (JS_PMA0_COMMON_BASE + 4*0x07) //Attributes : RO #define JS_PMA0_MPLLB_PARAM1 (JS_PMA0_COMMON_BASE + 4*0x08) //Attributes : RW #define JS_PMA0_MPLLB_PARAM2 (JS_PMA0_COMMON_BASE + 4*0x09) //Attributes : RW #define JS_PMA0_MPLLB_PARAM3 (JS_PMA0_COMMON_BASE + 4*0x0A) //Attributes : RW #define JS_PMA0_MPLLB_PARAM4 (JS_PMA0_COMMON_BASE + 4*0x0B) //Attributes : RW #define JS_PMA0_MPLLB_PARAM5 (JS_PMA0_COMMON_BASE + 4*0x0C) //Attributes : RW #define JS_PMA0_MPLLB_PARAM6 (JS_PMA0_COMMON_BASE + 4*0x0D) //Attributes : RW #define JS_PMA0_MPLLB_FORCE_EN (JS_PMA0_COMMON_BASE + 4*0x0E) //Attributes : RW #define JS_PMA0_MPLLB_FORCE_ACK (JS_PMA0_COMMON_BASE + 4*0x0F) //Attributes : RO #define JS_PMA0_SUP_MISC (JS_PMA0_COMMON_BASE + 4*0x16) //Attributes : RW #define JS_PMA0_MPLLA_FRAC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x17) //Attributes : RW #define JS_PMA0_MPLLA_FRAC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x18) //Attributes : RW #define JS_PMA0_MPLLA_FRAC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x19) //Attributes : RW #define JS_PMA0_MPLLA_FRAC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x1A) //Attributes : RW #define JS_PMA0_MPLLA_SSC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x1B) //Attributes : RW #define JS_PMA0_MPLLA_SSC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L #define JS_PMA0_MPLLA_SSC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H #define JS_PMA0_MPLLA_SSC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x1E) //Attributes : RW #define JS_PMA0_MPLLA_SSC_CTRL5 (JS_PMA0_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L #define JS_PMA0_MPLLA_SSC_CTRL6 (JS_PMA0_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H #define JS_PMA0_MPLLB_FRAC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x21) //Attributes : RW #define JS_PMA0_MPLLB_FRAC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_MPLLB_FRAC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x23) //Attributes : RW #define JS_PMA0_MPLLB_FRAC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x24) //Attributes : RW #define JS_PMA0_MPLLB_SSC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x25) //Attributes : RW #define JS_PMA0_MPLLB_SSC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L #define JS_PMA0_MPLLB_SSC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H #define JS_PMA0_MPLLB_SSC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x28) //Attributes : RW #define JS_PMA0_MPLLB_SSC_CTRL5 (JS_PMA0_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L #define JS_PMA0_MPLLB_SSC_CTRL6 (JS_PMA0_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H #define JS_PMA0_MPLLA_RECAL_CTRL (JS_PMA0_COMMON_BASE + 4*0x2B) //Attributes : RW #define JS_PMA0_MPLLB_RECAL_CTRL (JS_PMA0_COMMON_BASE + 4*0x2C) //Attributes : RW #define JS_PMA0_MPLL_CTRL_MUX (JS_PMA0_COMMON_BASE + 4*0x2D) //Attributes : RW #define JS_PMA0_POWER_SUPPLY_SEL (JS_PMA0_COMMON_BASE + 4*0x30) //Attributes : RW #define JS_PMA0_PHY_RESET (JS_PMA0_COMMON_BASE + 4*0x31) //Attributes : RW #define JS_PMA0_REF_CLK_CTRL (JS_PMA0_COMMON_BASE + 4*0x40) //Attributes : RW #define JS_PMA0_REFA_CLK_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x41) //Attributes : RW #define JS_PMA0_REFA_CLK_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x42) //Attributes : RW #define JS_PMA0_REFA_CLK_STATUS (JS_PMA0_COMMON_BASE + 4*0x43) //Attributes : RO #define JS_PMA0_REFB_CLK_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x44) //Attributes : RW #define JS_PMA0_REFB_CLK_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x45) //Attributes : RW #define JS_PMA0_REFB_CLK_STATUS (JS_PMA0_COMMON_BASE + 4*0x46) //Attributes : RO #define JS_PMA0_REF_CLK_MUX (JS_PMA0_COMMON_BASE + 4*0x47) //Attributes : RW #define JS_PMA0_RES_ACK_IN (JS_PMA0_COMMON_BASE + 4*0x50) //Attributes : RW #define JS_PMA0_RES_ACK_OUT (JS_PMA0_COMMON_BASE + 4*0x51) //Attributes : RO #define JS_PMA0_RES_REQ_IN (JS_PMA0_COMMON_BASE + 4*0x52) //Attributes : RW #define JS_PMA0_RES_REQ_OUT (JS_PMA0_COMMON_BASE + 4*0x53) //Attributes : RO #define JS_PMA0_RTUNE_REQ (JS_PMA0_COMMON_BASE + 4*0x54) //Attributes : RW #define JS_PMA0_RTUNE_ACK (JS_PMA0_COMMON_BASE + 4*0x55) //Attributes : RO #define JS_PMA0_RTUNE_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x56) //Attributes : RW #define JS_PMA0_RTUNE_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x57) //Attributes : RW #define JS_PMA0_RTUNE_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x58) //Attributes : RW #define JS_PMA0_RX_BIAS_CURRENT_CTRL (JS_PMA0_COMMON_BASE + 4*0x59) //Attributes : RW #define JS_PMA0_CR_PARA_SEL (JS_PMA0_COMMON_BASE + 4*0x90) //Attributes : RW #define JS_PMA0_POWER_GATING_SIGNAL1 (JS_PMA0_COMMON_BASE + 4*0x60) //Attributes : RW #define JS_PMA0_POWER_GATING_SIGNAL2 (JS_PMA0_COMMON_BASE + 4*0x61) //Attributes : RO #define JS_PMA0_POWER_GATING_SIGNAL3 (JS_PMA0_COMMON_BASE + 4*0x62) //Attributes : RW #define JS_PMA0_SRAM_CTRL (JS_PMA0_COMMON_BASE + 4*0x68) //Attributes : RW #define JS_PMA0_SRAM_STATUS (JS_PMA0_COMMON_BASE + 4*0x69) //Attributes : RO #define JS_PMA0_SRIO_RST_REQ (JS_PMA0_COMMON_BASE + 4*0x6A) //Attributes : RO #define JS_PMA0_SRIO_GEN3_EN (JS_PMA0_COMMON_BASE + 4*0x6C) //Attributes : RW #define JS_PMA0_SRIO_RATE_OUT (JS_PMA0_COMMON_BASE + 4*0x6D) //Attributes : RW #define JS_PMA0_CPRI_RST_REQ (JS_PMA0_COMMON_BASE + 4*0x70) //Attributes : RW #define JS_PMA0_CPRI_RX_LOS (JS_PMA0_COMMON_BASE + 4*0x71) //Attributes : RW #define JS_PMA0_CPRI_SIGNAL_OK (JS_PMA0_COMMON_BASE + 4*0x72) //Attributes : RW #define JS_PMA0_CPRI_ENERGY_DET (JS_PMA0_COMMON_BASE + 4*0x73) //Attributes : RW #define JS_PMA0_CPRI_SIGDET (JS_PMA0_COMMON_BASE + 4*0x74) //Attributes : RW #define JS_PMA0_CPRI_PCS_STATUS (JS_PMA0_COMMON_BASE + 4*0x75) //Attributes : RO #define JS_PMA0_CPRI_PCS_STATUS_CTRL (JS_PMA0_COMMON_BASE + 4*0x76) //Attributes : RW #define JS_PMA0_ETH_ENERGY_DET (JS_PMA0_COMMON_BASE + 4*0x80) //Attributes : RW #define JS_PMA0_ETH_SPEED_CTRL (JS_PMA0_COMMON_BASE + 4*0x81) //Attributes : RO #define JS_PMA0_TX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF0) //Attributes : RW #define JS_PMA0_RPCS_TX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF1) //Attributes : RW #define JS_PMA0_RPCS_RX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF2) //Attributes : RW #define JS_PMA0_PMA_COM_SCRATCH (JS_PMA0_COMMON_BASE + 4*0xff) //Attributes : RW //The PMA PCS Register #define JS_PMA0_PCS_SOFT_RESET (JS_PMA0_PCS_BASE + 4*0x00) //Attributes : RW #define JS_PMA0_PCS_LOOPBACK_CTRL (JS_PMA0_PCS_BASE + 4*0x04) //Attributes : RW #define JS_PMA0_PCS_PRBS_UDP_SEND (JS_PMA0_PCS_BASE + 4*0x05) //Attributes : RW #define JS_PMA0_PCS_PRBS_SEND_ERRINS (JS_PMA0_PCS_BASE + 4*0x06) //Attributes : RW #define JS_PMA0_PCS_TXUDP_0 (JS_PMA0_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L #define JS_PMA0_PCS_TXUDP_1 (JS_PMA0_PCS_BASE + 4*0x08) //Attributes : RW_EXT #define JS_PMA0_PCS_TXUDP_2 (JS_PMA0_PCS_BASE + 4*0x09) //Attributes : RW_EXT #define JS_PMA0_PCS_TXUDP_3 (JS_PMA0_PCS_BASE + 4*0x0A) //Attributes : RW_EXT #define JS_PMA0_PCS_TXUDP_4 (JS_PMA0_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H #define JS_PMA0_PCS_PRBS_UDP_CHK (JS_PMA0_PCS_BASE + 4*0x10) //Attributes : RW #define JS_PMA0_PCS_RXUDP_0 (JS_PMA0_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L #define JS_PMA0_PCS_RXUDP_1 (JS_PMA0_PCS_BASE + 4*0x12) //Attributes : RW_EXT #define JS_PMA0_PCS_RXUDP_2 (JS_PMA0_PCS_BASE + 4*0x13) //Attributes : RW_EXT #define JS_PMA0_PCS_RXUDP_3 (JS_PMA0_PCS_BASE + 4*0x14) //Attributes : RW_EXT #define JS_PMA0_PCS_RXUDP_4 (JS_PMA0_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H #define JS_PMA0_PCS_RXPRBS_ERRCNT_L0 (JS_PMA0_PCS_BASE + 4*0x16) //Attributes : RO #define JS_PMA0_PCS_RXPRBS_ERRCNT_L1 (JS_PMA0_PCS_BASE + 4*0x17) //Attributes : RO #define JS_PMA0_PCS_RXPRBS_ERRCNT_L2 (JS_PMA0_PCS_BASE + 4*0x18) //Attributes : RO #define JS_PMA0_PCS_RXPRBS_ERRCNT_L3 (JS_PMA0_PCS_BASE + 4*0x19) //Attributes : RO #define JS_PMA0_PCS_NELP_FIFO_STATUS (JS_PMA0_PCS_BASE + 4*0x20) //Attributes : RO #define JS_PMA0_PCS_FELP_FIFO_STATUS (JS_PMA0_PCS_BASE + 4*0x21) //Attributes : RO #define JS_PMA0_PCS_BIT_REV_CTRL (JS_PMA0_PCS_BASE + 4*0x22) //Attributes : RW #define JS_PMA0_PCS_SOFT_PON_RST (JS_PMA0_PCS_BASE + 4*0xfe) //Attributes : RW #define JS_PMA0_PCS_PCS_SCRATCH (JS_PMA0_PCS_BASE + 4*0xff) //Attributes : RW //------------------------JS1 SUBSYSTEM -------------------------// //The PMA Lane Config Base Addr #define JECS_PMA1_LANE0_BASE JECS_PMA1_CFG + 0x10000*4 #define JECS_PMA1_LANE1_BASE JECS_PMA1_CFG + 0x10800*4 #define JECS_PMA1_LANE2_BASE JECS_PMA1_CFG + 0x11000*4 #define JECS_PMA1_LANE3_BASE JECS_PMA1_CFG + 0x11800*4 #define JECS_PMA1_BROADCAST_BASE JECS_PMA1_CFG + 0x12000*4 //The PMA COMMON Base Addr #define JECS_PMA1_COMMON_BASE JECS_PMA1_CFG + 0x14000*4 //The PMA PCS Addr #define JECS_PMA1_PCS_BASE JECS_PMA1_CFG + 0x18000*4 //The PMA Lane Config Register #define JECS_PMA1_LANE0_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE0_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ (JECS_PMA1_LANE0_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x02) //Attributes : RO #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE0_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE0_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE0_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE0_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE0_BASE + 4*0x07) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE0_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE0_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE0_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE0_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x11) //Attributes : RO #define JECS_PMA1_LANE0_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE0_BASE + 4*0x12) //Attributes : RO #define JECS_PMA1_LANE0_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE0_BASE + 4*0x13) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x14) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE0_BASE + 4*0x20) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE0_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE0_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE0_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE0_BASE + 4*0x24) //Attributes : RO #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE0_BASE + 4*0x25) //Attributes : RO #define JECS_PMA1_LANE0_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x26) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_RESET (JECS_PMA1_LANE0_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_CONTROL (JECS_PMA1_LANE0_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x32) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE0_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_LANE0_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_REQ (JECS_PMA1_LANE0_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE0_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE0_BASE + 4*0x53) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x55) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE0_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE0_BASE + 4*0x61) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE0_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x63) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE0_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE0_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_EQ1 (JECS_PMA1_LANE0_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_EQ2 (JECS_PMA1_LANE0_BASE + 4*0x81) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_EQ3 (JECS_PMA1_LANE0_BASE + 4*0x82) //Attributes : RW #define JECS_PMA1_LANE0_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x83) //Attributes : RW #define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0x91) //Attributes : RW #define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE0_BASE + 4*0x92) //Attributes : RW #define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE0_BASE + 4*0x93) //Attributes : RW #define JECS_PMA1_LANE0_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE0_BASE + 4*0x94) //Attributes : RW #define JECS_PMA1_LANE0_LANE_REFCLK_SEL (JECS_PMA1_LANE0_BASE + 4*0xA0) //Attributes : RW #define JECS_PMA1_LANE0_ETH_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xB0) //Attributes : RW #define JECS_PMA1_LANE0_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xB1) //Attributes : RW #define JECS_PMA1_LANE0_RX_ADAPT_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC0) //Attributes : RW #define JECS_PMA1_LANE0_RX_DCC_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC1) //Attributes : RW #define JECS_PMA1_LANE0_RX_EQ_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0xC2) //Attributes : RW #define JECS_PMA1_LANE0_RX_EQ_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0xC3) //Attributes : RW #define JECS_PMA1_LANE0_RX_MARGIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC4) //Attributes : RW #define JECS_PMA1_LANE0_RX_MARGIN_ERROR (JECS_PMA1_LANE0_BASE + 4*0xC5) //Attributes : RO #define JECS_PMA1_LANE0_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xC6) //Attributes : RW #define JECS_PMA1_LANE0_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC8) //Attributes : RW #define JECS_PMA1_LANE0_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xC9) //Attributes : RW #define JECS_PMA1_LANE0_RX_DIV_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xCA) //Attributes : RW #define JECS_PMA1_LANE0_TX_DIV_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xCB) //Attributes : RW #define JECS_PMA1_LANE0_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xCC) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0xD0) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0xD1) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_CTRL3 (JECS_PMA1_LANE0_BASE + 4*0xD2) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_CTRL4 (JECS_PMA1_LANE0_BASE + 4*0xD3) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_CTRL5 (JECS_PMA1_LANE0_BASE + 4*0xD4) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_REQ_MUX (JECS_PMA1_LANE0_BASE + 4*0xD5) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE0_BASE + 4*0xD6) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_INTERFACE_MUX (JECS_PMA1_LANE0_BASE + 4*0xD7) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE0_BASE + 4*0xD8) //Attributes : RW #define JECS_PMA1_LANE0_TRANS_PLL_STATE (JECS_PMA1_LANE0_BASE + 4*0xD9) //Attributes : RO #define JECS_PMA1_LANE0_PLL_STATE_MUX (JECS_PMA1_LANE0_BASE + 4*0xDA) //Attributes : RW #define JECS_PMA1_LANE0_RX_VALID_PHY (JECS_PMA1_LANE0_BASE + 4*0xDF) //Attributes : RO #define JECS_PMA1_LANE0_RX_VALID_MUX (JECS_PMA1_LANE0_BASE + 4*0xE0) //Attributes : RW #define JECS_PMA1_LANE0_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE0_BASE + 4*0xE1) //Attributes : RW #define JECS_PMA1_LANE0_SRIO_DEGRADED (JECS_PMA1_LANE0_BASE + 4*0xE2) //Attributes : RW #define JECS_PMA1_LANE0_SRIO_RETRAIN (JECS_PMA1_LANE0_BASE + 4*0xE3) //Attributes : RW #define JECS_PMA1_LANE0_SRIO_SHORT_RUN (JECS_PMA1_LANE0_BASE + 4*0xE4) //Attributes : RW #define JECS_PMA1_LANE0_EQ_INIT_C0 (JECS_PMA1_LANE0_BASE + 4*0xE5) //Attributes : RW #define JECS_PMA1_LANE0_EQ_INIT_CN1 (JECS_PMA1_LANE0_BASE + 4*0xE6) //Attributes : RW #define JECS_PMA1_LANE0_EQ_INIT_CP1 (JECS_PMA1_LANE0_BASE + 4*0xE7) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RULE_CTRL_1 (JECS_PMA1_LANE0_BASE + 4*0xE8) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RULE_CTRL_2 (JECS_PMA1_LANE0_BASE + 4*0xE9) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RULE_CTRL_3 (JECS_PMA1_LANE0_BASE + 4*0xEA) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RULE_CTRL_4 (JECS_PMA1_LANE0_BASE + 4*0xEB) //Attributes : RW #define JECS_PMA1_LANE0_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE0_BASE + 4*0xEC) //Attributes : RW #define JECS_PMA1_LANE0_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xED) //Attributes : RW #define JECS_PMA1_LANE0_EQ_ADJ_INTERVAL (JECS_PMA1_LANE0_BASE + 4*0xEE) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RX_REQ_CTRL (JECS_PMA1_LANE0_BASE + 4*0xEF) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE0_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_LANE0_RPCS_KTR_STATUS (JECS_PMA1_LANE0_BASE + 4*0xF2) //Attributes : RO #define JECS_PMA1_LANE0_EQ_FSM (JECS_PMA1_LANE0_BASE + 4*0xF3) //Attributes : RO #define JECS_PMA1_LANE0_ETH_RX_LOS (JECS_PMA1_LANE0_BASE + 4*0xF4) //Attributes : RW #define JECS_PMA1_LANE0_EQ_PRESET_C0 (JECS_PMA1_LANE0_BASE + 4*0xF5) //Attributes : RW #define JECS_PMA1_LANE0_EQ_PRESET_CN1 (JECS_PMA1_LANE0_BASE + 4*0xF6) //Attributes : RW #define JECS_PMA1_LANE0_EQ_PRESET_CP1 (JECS_PMA1_LANE0_BASE + 4*0xF7) //Attributes : RW #define JECS_PMA1_LANE0_EQ_SUCC_MASK (JECS_PMA1_LANE0_BASE + 4*0xF8) //Attributes : RW #define JECS_PMA1_LANE0_PMA_COM_SCRATCH (JECS_PMA1_LANE0_BASE + 4*0xff) //Attributes : RW #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x101) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x102) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x103) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x104) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x105) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x106) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x108) //Attributes : RW #define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT #define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x10D) //Attributes : RW #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x111) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x112) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x113) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x114) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x115) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x116) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x118) //Attributes : RW #define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x11D) //Attributes : RW #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x121) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x122) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x123) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x124) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x125) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x126) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x128) //Attributes : RW #define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x12D) //Attributes : RW #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x131) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x132) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x133) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x134) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x135) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x136) //Attributes : RO_EXT #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x138) //Attributes : RW #define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L #define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT #define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x13D) //Attributes : RW #define JECS_PMA1_LANE1_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE1_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ (JECS_PMA1_LANE1_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x02) //Attributes : RO #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE1_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE1_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE1_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE1_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE1_BASE + 4*0x07) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE1_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE1_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE1_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE1_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x11) //Attributes : RO #define JECS_PMA1_LANE1_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE1_BASE + 4*0x12) //Attributes : RO #define JECS_PMA1_LANE1_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE1_BASE + 4*0x13) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x14) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE1_BASE + 4*0x20) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE1_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE1_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE1_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE1_BASE + 4*0x24) //Attributes : RO #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE1_BASE + 4*0x25) //Attributes : RO #define JECS_PMA1_LANE1_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x26) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_RESET (JECS_PMA1_LANE1_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_CONTROL (JECS_PMA1_LANE1_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x32) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE1_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_LANE1_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_REQ (JECS_PMA1_LANE1_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_LANE1_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE1_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE1_BASE + 4*0x53) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x55) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE1_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE1_BASE + 4*0x61) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE1_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x63) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE1_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE1_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_EQ1 (JECS_PMA1_LANE1_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_EQ2 (JECS_PMA1_LANE1_BASE + 4*0x81) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_EQ3 (JECS_PMA1_LANE1_BASE + 4*0x82) //Attributes : RW #define JECS_PMA1_LANE1_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x83) //Attributes : RW #define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0x91) //Attributes : RW #define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE1_BASE + 4*0x92) //Attributes : RW #define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE1_BASE + 4*0x93) //Attributes : RW #define JECS_PMA1_LANE1_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE1_BASE + 4*0x94) //Attributes : RW #define JECS_PMA1_LANE1_LANE_REFCLK_SEL (JECS_PMA1_LANE1_BASE + 4*0xA0) //Attributes : RW #define JECS_PMA1_LANE1_ETH_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xB0) //Attributes : RW #define JECS_PMA1_LANE1_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xB1) //Attributes : RW #define JECS_PMA1_LANE1_RX_ADAPT_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC0) //Attributes : RW #define JECS_PMA1_LANE1_RX_DCC_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC1) //Attributes : RW #define JECS_PMA1_LANE1_RX_EQ_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0xC2) //Attributes : RW #define JECS_PMA1_LANE1_RX_EQ_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0xC3) //Attributes : RW #define JECS_PMA1_LANE1_RX_MARGIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC4) //Attributes : RW #define JECS_PMA1_LANE1_RX_MARGIN_ERROR (JECS_PMA1_LANE1_BASE + 4*0xC5) //Attributes : RO #define JECS_PMA1_LANE1_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xC6) //Attributes : RW #define JECS_PMA1_LANE1_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC8) //Attributes : RW #define JECS_PMA1_LANE1_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xC9) //Attributes : RW #define JECS_PMA1_LANE1_RX_DIV_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xCA) //Attributes : RW #define JECS_PMA1_LANE1_TX_DIV_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xCB) //Attributes : RW #define JECS_PMA1_LANE1_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xCC) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0xD0) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0xD1) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_CTRL3 (JECS_PMA1_LANE1_BASE + 4*0xD2) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_CTRL4 (JECS_PMA1_LANE1_BASE + 4*0xD3) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_CTRL5 (JECS_PMA1_LANE1_BASE + 4*0xD4) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_REQ_MUX (JECS_PMA1_LANE1_BASE + 4*0xD5) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE1_BASE + 4*0xD6) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_INTERFACE_MUX (JECS_PMA1_LANE1_BASE + 4*0xD7) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE1_BASE + 4*0xD8) //Attributes : RW #define JECS_PMA1_LANE1_TRANS_PLL_STATE (JECS_PMA1_LANE1_BASE + 4*0xD9) //Attributes : RO #define JECS_PMA1_LANE1_PLL_STATE_MUX (JECS_PMA1_LANE1_BASE + 4*0xDA) //Attributes : RW #define JECS_PMA1_LANE1_RX_VALID_PHY (JECS_PMA1_LANE1_BASE + 4*0xDF) //Attributes : RO #define JECS_PMA1_LANE1_RX_VALID_MUX (JECS_PMA1_LANE1_BASE + 4*0xE0) //Attributes : RW #define JECS_PMA1_LANE1_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE1_BASE + 4*0xE1) //Attributes : RW #define JECS_PMA1_LANE1_SRIO_DEGRADED (JECS_PMA1_LANE1_BASE + 4*0xE2) //Attributes : RW #define JECS_PMA1_LANE1_SRIO_RETRAIN (JECS_PMA1_LANE1_BASE + 4*0xE3) //Attributes : RW #define JECS_PMA1_LANE1_SRIO_SHORT_RUN (JECS_PMA1_LANE1_BASE + 4*0xE4) //Attributes : RW #define JECS_PMA1_LANE1_EQ_INIT_C0 (JECS_PMA1_LANE1_BASE + 4*0xE5) //Attributes : RW #define JECS_PMA1_LANE1_EQ_INIT_CN1 (JECS_PMA1_LANE1_BASE + 4*0xE6) //Attributes : RW #define JECS_PMA1_LANE1_EQ_INIT_CP1 (JECS_PMA1_LANE1_BASE + 4*0xE7) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RULE_CTRL_1 (JECS_PMA1_LANE1_BASE + 4*0xE8) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RULE_CTRL_2 (JECS_PMA1_LANE1_BASE + 4*0xE9) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RULE_CTRL_3 (JECS_PMA1_LANE1_BASE + 4*0xEA) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RULE_CTRL_4 (JECS_PMA1_LANE1_BASE + 4*0xEB) //Attributes : RW #define JECS_PMA1_LANE1_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE1_BASE + 4*0xEC) //Attributes : RW #define JECS_PMA1_LANE1_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xED) //Attributes : RW #define JECS_PMA1_LANE1_EQ_ADJ_INTERVAL (JECS_PMA1_LANE1_BASE + 4*0xEE) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RX_REQ_CTRL (JECS_PMA1_LANE1_BASE + 4*0xEF) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE1_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_LANE1_RPCS_KTR_STATUS (JECS_PMA1_LANE1_BASE + 4*0xF2) //Attributes : RO #define JECS_PMA1_LANE1_EQ_FSM (JECS_PMA1_LANE1_BASE + 4*0xF3) //Attributes : RO #define JECS_PMA1_LANE1_ETH_RX_LOS (JECS_PMA1_LANE1_BASE + 4*0xF4) //Attributes : RW #define JECS_PMA1_LANE1_EQ_PRESET_C0 (JECS_PMA1_LANE1_BASE + 4*0xF5) //Attributes : RW #define JECS_PMA1_LANE1_EQ_PRESET_CN1 (JECS_PMA1_LANE1_BASE + 4*0xF6) //Attributes : RW #define JECS_PMA1_LANE1_EQ_PRESET_CP1 (JECS_PMA1_LANE1_BASE + 4*0xF7) //Attributes : RW #define JECS_PMA1_LANE1_EQ_SUCC_MASK (JECS_PMA1_LANE1_BASE + 4*0xF8) //Attributes : RW #define JECS_PMA1_LANE1_PMA_COM_SCRATCH (JECS_PMA1_LANE1_BASE + 4*0xff) //Attributes : RW #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x101) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x102) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x103) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x104) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x105) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x106) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x108) //Attributes : RW #define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT #define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x10D) //Attributes : RW #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x111) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x112) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x113) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x114) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x115) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x116) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x118) //Attributes : RW #define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x11D) //Attributes : RW #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x121) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x122) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x123) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x124) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x125) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x126) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x128) //Attributes : RW #define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x12D) //Attributes : RW #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x131) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x132) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x133) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x134) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x135) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x136) //Attributes : RO_EXT #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x138) //Attributes : RW #define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L #define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT #define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x13D) //Attributes : RW #define JECS_PMA1_LANE2_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE2_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ (JECS_PMA1_LANE2_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x02) //Attributes : RO #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE2_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE2_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE2_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE2_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE2_BASE + 4*0x07) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE2_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE2_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE2_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE2_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x11) //Attributes : RO #define JECS_PMA1_LANE2_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE2_BASE + 4*0x12) //Attributes : RO #define JECS_PMA1_LANE2_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE2_BASE + 4*0x13) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x14) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE2_BASE + 4*0x20) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE2_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE2_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE2_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE2_BASE + 4*0x24) //Attributes : RO #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE2_BASE + 4*0x25) //Attributes : RO #define JECS_PMA1_LANE2_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x26) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_RESET (JECS_PMA1_LANE2_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_CONTROL (JECS_PMA1_LANE2_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x32) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE2_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_LANE2_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_REQ (JECS_PMA1_LANE2_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_LANE2_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE2_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE2_BASE + 4*0x53) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x55) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE2_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE2_BASE + 4*0x61) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE2_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x63) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE2_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE2_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_EQ1 (JECS_PMA1_LANE2_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_EQ2 (JECS_PMA1_LANE2_BASE + 4*0x81) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_EQ3 (JECS_PMA1_LANE2_BASE + 4*0x82) //Attributes : RW #define JECS_PMA1_LANE2_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x83) //Attributes : RW #define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0x91) //Attributes : RW #define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE2_BASE + 4*0x92) //Attributes : RW #define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE2_BASE + 4*0x93) //Attributes : RW #define JECS_PMA1_LANE2_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE2_BASE + 4*0x94) //Attributes : RW #define JECS_PMA1_LANE2_LANE_REFCLK_SEL (JECS_PMA1_LANE2_BASE + 4*0xA0) //Attributes : RW #define JECS_PMA1_LANE2_ETH_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xB0) //Attributes : RW #define JECS_PMA1_LANE2_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xB1) //Attributes : RW #define JECS_PMA1_LANE2_RX_ADAPT_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC0) //Attributes : RW #define JECS_PMA1_LANE2_RX_DCC_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC1) //Attributes : RW #define JECS_PMA1_LANE2_RX_EQ_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0xC2) //Attributes : RW #define JECS_PMA1_LANE2_RX_EQ_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0xC3) //Attributes : RW #define JECS_PMA1_LANE2_RX_MARGIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC4) //Attributes : RW #define JECS_PMA1_LANE2_RX_MARGIN_ERROR (JECS_PMA1_LANE2_BASE + 4*0xC5) //Attributes : RO #define JECS_PMA1_LANE2_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xC6) //Attributes : RW #define JECS_PMA1_LANE2_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC8) //Attributes : RW #define JECS_PMA1_LANE2_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xC9) //Attributes : RW #define JECS_PMA1_LANE2_RX_DIV_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xCA) //Attributes : RW #define JECS_PMA1_LANE2_TX_DIV_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xCB) //Attributes : RW #define JECS_PMA1_LANE2_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xCC) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0xD0) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0xD1) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_CTRL3 (JECS_PMA1_LANE2_BASE + 4*0xD2) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_CTRL4 (JECS_PMA1_LANE2_BASE + 4*0xD3) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_CTRL5 (JECS_PMA1_LANE2_BASE + 4*0xD4) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_REQ_MUX (JECS_PMA1_LANE2_BASE + 4*0xD5) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE2_BASE + 4*0xD6) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_INTERFACE_MUX (JECS_PMA1_LANE2_BASE + 4*0xD7) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE2_BASE + 4*0xD8) //Attributes : RW #define JECS_PMA1_LANE2_TRANS_PLL_STATE (JECS_PMA1_LANE2_BASE + 4*0xD9) //Attributes : RO #define JECS_PMA1_LANE2_PLL_STATE_MUX (JECS_PMA1_LANE2_BASE + 4*0xDA) //Attributes : RW #define JECS_PMA1_LANE2_RX_VALID_PHY (JECS_PMA1_LANE2_BASE + 4*0xDF) //Attributes : RO #define JECS_PMA1_LANE2_RX_VALID_MUX (JECS_PMA1_LANE2_BASE + 4*0xE0) //Attributes : RW #define JECS_PMA1_LANE2_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE2_BASE + 4*0xE1) //Attributes : RW #define JECS_PMA1_LANE2_SRIO_DEGRADED (JECS_PMA1_LANE2_BASE + 4*0xE2) //Attributes : RW #define JECS_PMA1_LANE2_SRIO_RETRAIN (JECS_PMA1_LANE2_BASE + 4*0xE3) //Attributes : RW #define JECS_PMA1_LANE2_SRIO_SHORT_RUN (JECS_PMA1_LANE2_BASE + 4*0xE4) //Attributes : RW #define JECS_PMA1_LANE2_EQ_INIT_C0 (JECS_PMA1_LANE2_BASE + 4*0xE5) //Attributes : RW #define JECS_PMA1_LANE2_EQ_INIT_CN1 (JECS_PMA1_LANE2_BASE + 4*0xE6) //Attributes : RW #define JECS_PMA1_LANE2_EQ_INIT_CP1 (JECS_PMA1_LANE2_BASE + 4*0xE7) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RULE_CTRL_1 (JECS_PMA1_LANE2_BASE + 4*0xE8) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RULE_CTRL_2 (JECS_PMA1_LANE2_BASE + 4*0xE9) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RULE_CTRL_3 (JECS_PMA1_LANE2_BASE + 4*0xEA) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RULE_CTRL_4 (JECS_PMA1_LANE2_BASE + 4*0xEB) //Attributes : RW #define JECS_PMA1_LANE2_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE2_BASE + 4*0xEC) //Attributes : RW #define JECS_PMA1_LANE2_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xED) //Attributes : RW #define JECS_PMA1_LANE2_EQ_ADJ_INTERVAL (JECS_PMA1_LANE2_BASE + 4*0xEE) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RX_REQ_CTRL (JECS_PMA1_LANE2_BASE + 4*0xEF) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE2_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_LANE2_RPCS_KTR_STATUS (JECS_PMA1_LANE2_BASE + 4*0xF2) //Attributes : RO #define JECS_PMA1_LANE2_EQ_FSM (JECS_PMA1_LANE2_BASE + 4*0xF3) //Attributes : RO #define JECS_PMA1_LANE2_ETH_RX_LOS (JECS_PMA1_LANE2_BASE + 4*0xF4) //Attributes : RW #define JECS_PMA1_LANE2_EQ_PRESET_C0 (JECS_PMA1_LANE2_BASE + 4*0xF5) //Attributes : RW #define JECS_PMA1_LANE2_EQ_PRESET_CN1 (JECS_PMA1_LANE2_BASE + 4*0xF6) //Attributes : RW #define JECS_PMA1_LANE2_EQ_PRESET_CP1 (JECS_PMA1_LANE2_BASE + 4*0xF7) //Attributes : RW #define JECS_PMA1_LANE2_EQ_SUCC_MASK (JECS_PMA1_LANE2_BASE + 4*0xF8) //Attributes : RW #define JECS_PMA1_LANE2_PMA_COM_SCRATCH (JECS_PMA1_LANE2_BASE + 4*0xff) //Attributes : RW #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x101) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x102) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x103) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x104) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x105) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x106) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x108) //Attributes : RW #define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT #define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x10D) //Attributes : RW #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x111) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x112) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x113) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x114) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x115) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x116) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x118) //Attributes : RW #define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x11D) //Attributes : RW #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x121) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x122) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x123) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x124) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x125) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x126) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x128) //Attributes : RW #define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x12D) //Attributes : RW #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x131) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x132) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x133) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x134) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x135) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x136) //Attributes : RO_EXT #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x138) //Attributes : RW #define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L #define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT #define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x13D) //Attributes : RW #define JECS_PMA1_LANE3_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE3_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ (JECS_PMA1_LANE3_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x02) //Attributes : RO #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE3_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE3_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE3_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE3_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE3_BASE + 4*0x07) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE3_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE3_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE3_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE3_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x11) //Attributes : RO #define JECS_PMA1_LANE3_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE3_BASE + 4*0x12) //Attributes : RO #define JECS_PMA1_LANE3_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE3_BASE + 4*0x13) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x14) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE3_BASE + 4*0x20) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE3_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE3_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE3_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE3_BASE + 4*0x24) //Attributes : RO #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE3_BASE + 4*0x25) //Attributes : RO #define JECS_PMA1_LANE3_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x26) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_RESET (JECS_PMA1_LANE3_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_CONTROL (JECS_PMA1_LANE3_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x32) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE3_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_LANE3_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_REQ (JECS_PMA1_LANE3_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_LANE3_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE3_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE3_BASE + 4*0x53) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x55) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE3_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE3_BASE + 4*0x61) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE3_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x63) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE3_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE3_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_EQ1 (JECS_PMA1_LANE3_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_EQ2 (JECS_PMA1_LANE3_BASE + 4*0x81) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_EQ3 (JECS_PMA1_LANE3_BASE + 4*0x82) //Attributes : RW #define JECS_PMA1_LANE3_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x83) //Attributes : RW #define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0x91) //Attributes : RW #define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE3_BASE + 4*0x92) //Attributes : RW #define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE3_BASE + 4*0x93) //Attributes : RW #define JECS_PMA1_LANE3_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE3_BASE + 4*0x94) //Attributes : RW #define JECS_PMA1_LANE3_LANE_REFCLK_SEL (JECS_PMA1_LANE3_BASE + 4*0xA0) //Attributes : RW #define JECS_PMA1_LANE3_ETH_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xB0) //Attributes : RW #define JECS_PMA1_LANE3_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xB1) //Attributes : RW #define JECS_PMA1_LANE3_RX_ADAPT_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC0) //Attributes : RW #define JECS_PMA1_LANE3_RX_DCC_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC1) //Attributes : RW #define JECS_PMA1_LANE3_RX_EQ_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0xC2) //Attributes : RW #define JECS_PMA1_LANE3_RX_EQ_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0xC3) //Attributes : RW #define JECS_PMA1_LANE3_RX_MARGIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC4) //Attributes : RW #define JECS_PMA1_LANE3_RX_MARGIN_ERROR (JECS_PMA1_LANE3_BASE + 4*0xC5) //Attributes : RO #define JECS_PMA1_LANE3_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xC6) //Attributes : RW #define JECS_PMA1_LANE3_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC8) //Attributes : RW #define JECS_PMA1_LANE3_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xC9) //Attributes : RW #define JECS_PMA1_LANE3_RX_DIV_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xCA) //Attributes : RW #define JECS_PMA1_LANE3_TX_DIV_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xCB) //Attributes : RW #define JECS_PMA1_LANE3_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xCC) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0xD0) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0xD1) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_CTRL3 (JECS_PMA1_LANE3_BASE + 4*0xD2) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_CTRL4 (JECS_PMA1_LANE3_BASE + 4*0xD3) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_CTRL5 (JECS_PMA1_LANE3_BASE + 4*0xD4) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_REQ_MUX (JECS_PMA1_LANE3_BASE + 4*0xD5) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE3_BASE + 4*0xD6) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_INTERFACE_MUX (JECS_PMA1_LANE3_BASE + 4*0xD7) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE3_BASE + 4*0xD8) //Attributes : RW #define JECS_PMA1_LANE3_TRANS_PLL_STATE (JECS_PMA1_LANE3_BASE + 4*0xD9) //Attributes : RO #define JECS_PMA1_LANE3_PLL_STATE_MUX (JECS_PMA1_LANE3_BASE + 4*0xDA) //Attributes : RW #define JECS_PMA1_LANE3_RX_VALID_PHY (JECS_PMA1_LANE3_BASE + 4*0xDF) //Attributes : RO #define JECS_PMA1_LANE3_RX_VALID_MUX (JECS_PMA1_LANE3_BASE + 4*0xE0) //Attributes : RW #define JECS_PMA1_LANE3_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE3_BASE + 4*0xE1) //Attributes : RW #define JECS_PMA1_LANE3_SRIO_DEGRADED (JECS_PMA1_LANE3_BASE + 4*0xE2) //Attributes : RW #define JECS_PMA1_LANE3_SRIO_RETRAIN (JECS_PMA1_LANE3_BASE + 4*0xE3) //Attributes : RW #define JECS_PMA1_LANE3_SRIO_SHORT_RUN (JECS_PMA1_LANE3_BASE + 4*0xE4) //Attributes : RW #define JECS_PMA1_LANE3_EQ_INIT_C0 (JECS_PMA1_LANE3_BASE + 4*0xE5) //Attributes : RW #define JECS_PMA1_LANE3_EQ_INIT_CN1 (JECS_PMA1_LANE3_BASE + 4*0xE6) //Attributes : RW #define JECS_PMA1_LANE3_EQ_INIT_CP1 (JECS_PMA1_LANE3_BASE + 4*0xE7) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RULE_CTRL_1 (JECS_PMA1_LANE3_BASE + 4*0xE8) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RULE_CTRL_2 (JECS_PMA1_LANE3_BASE + 4*0xE9) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RULE_CTRL_3 (JECS_PMA1_LANE3_BASE + 4*0xEA) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RULE_CTRL_4 (JECS_PMA1_LANE3_BASE + 4*0xEB) //Attributes : RW #define JECS_PMA1_LANE3_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE3_BASE + 4*0xEC) //Attributes : RW #define JECS_PMA1_LANE3_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xED) //Attributes : RW #define JECS_PMA1_LANE3_EQ_ADJ_INTERVAL (JECS_PMA1_LANE3_BASE + 4*0xEE) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RX_REQ_CTRL (JECS_PMA1_LANE3_BASE + 4*0xEF) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE3_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_LANE3_RPCS_KTR_STATUS (JECS_PMA1_LANE3_BASE + 4*0xF2) //Attributes : RO #define JECS_PMA1_LANE3_EQ_FSM (JECS_PMA1_LANE3_BASE + 4*0xF3) //Attributes : RO #define JECS_PMA1_LANE3_ETH_RX_LOS (JECS_PMA1_LANE3_BASE + 4*0xF4) //Attributes : RW #define JECS_PMA1_LANE3_EQ_PRESET_C0 (JECS_PMA1_LANE3_BASE + 4*0xF5) //Attributes : RW #define JECS_PMA1_LANE3_EQ_PRESET_CN1 (JECS_PMA1_LANE3_BASE + 4*0xF6) //Attributes : RW #define JECS_PMA1_LANE3_EQ_PRESET_CP1 (JECS_PMA1_LANE3_BASE + 4*0xF7) //Attributes : RW #define JECS_PMA1_LANE3_EQ_SUCC_MASK (JECS_PMA1_LANE3_BASE + 4*0xF8) //Attributes : RW #define JECS_PMA1_LANE3_PMA_COM_SCRATCH (JECS_PMA1_LANE3_BASE + 4*0xff) //Attributes : RW #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x101) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x102) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x103) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x104) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x105) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x106) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x108) //Attributes : RW #define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT #define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x10D) //Attributes : RW #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x111) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x112) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x113) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x114) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x115) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x116) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x118) //Attributes : RW #define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x11D) //Attributes : RW #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x121) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x122) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x123) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x124) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x125) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x126) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x128) //Attributes : RW #define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x12D) //Attributes : RW #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x131) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x132) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x133) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x134) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x135) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x136) //Attributes : RO_EXT #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x138) //Attributes : RW #define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L #define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT #define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x13D) //Attributes : RW #define JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x02) //Attributes : RO #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2 (JECS_PMA1_BROADCAST_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3 (JECS_PMA1_BROADCAST_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4 (JECS_PMA1_BROADCAST_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5 (JECS_PMA1_BROADCAST_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6 (JECS_PMA1_BROADCAST_BASE + 4*0x07) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7 (JECS_PMA1_BROADCAST_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8 (JECS_PMA1_BROADCAST_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9 (JECS_PMA1_BROADCAST_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x11) //Attributes : RO #define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_DIR (JECS_PMA1_BROADCAST_BASE + 4*0x12) //Attributes : RO #define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING (JECS_PMA1_BROADCAST_BASE + 4*0x13) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x14) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_EN (JECS_PMA1_BROADCAST_BASE + 4*0x20) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_BROADCAST_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_BROADCAST_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_BROADCAST_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_BROADCAST_BASE + 4*0x24) //Attributes : RO #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_BROADCAST_BASE + 4*0x25) //Attributes : RO #define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x26) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_RESET (JECS_PMA1_BROADCAST_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_CONTROL (JECS_PMA1_BROADCAST_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x32) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_RECAL_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_BROADCAST_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_BROADCAST_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_BROADCAST_BASE + 4*0x53) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x55) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_EN (JECS_PMA1_BROADCAST_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_BROADCAST_BASE + 4*0x61) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_BROADCAST_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x63) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL1 (JECS_PMA1_BROADCAST_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2 (JECS_PMA1_BROADCAST_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_EQ1 (JECS_PMA1_BROADCAST_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_EQ2 (JECS_PMA1_BROADCAST_BASE + 4*0x81) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_EQ3 (JECS_PMA1_BROADCAST_BASE + 4*0x82) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x83) //Attributes : RW #define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0x91) //Attributes : RW #define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_BROADCAST_BASE + 4*0x92) //Attributes : RW #define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_BROADCAST_BASE + 4*0x93) //Attributes : RW #define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0x94) //Attributes : RW #define JECS_PMA1_BROADCAST_LANE_REFCLK_SEL (JECS_PMA1_BROADCAST_BASE + 4*0xA0) //Attributes : RW #define JECS_PMA1_BROADCAST_ETH_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xB0) //Attributes : RW #define JECS_PMA1_BROADCAST_ETH_CLK_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xB1) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_ADAPT_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC0) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_DCC_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC1) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_EQ_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0xC2) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_EQ_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0xC3) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_MARGIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC4) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_MARGIN_ERROR (JECS_PMA1_BROADCAST_BASE + 4*0xC5) //Attributes : RO #define JECS_PMA1_BROADCAST_RECV_REQUEST_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xC6) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_COARSE_ADAPT_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC8) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xC9) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xCA) //Attributes : RW #define JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xCB) //Attributes : RW #define JECS_PMA1_BROADCAST_MULTI_CLK_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xCC) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0xD0) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0xD1) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 (JECS_PMA1_BROADCAST_BASE + 4*0xD2) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 (JECS_PMA1_BROADCAST_BASE + 4*0xD3) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 (JECS_PMA1_BROADCAST_BASE + 4*0xD4) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_REQ_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xD5) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xD6) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_INTERFACE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xD7) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_MASTER_PLL_STATE (JECS_PMA1_BROADCAST_BASE + 4*0xD8) //Attributes : RW #define JECS_PMA1_BROADCAST_TRANS_PLL_STATE (JECS_PMA1_BROADCAST_BASE + 4*0xD9) //Attributes : RO #define JECS_PMA1_BROADCAST_PLL_STATE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xDA) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_VALID_PHY (JECS_PMA1_BROADCAST_BASE + 4*0xDF) //Attributes : RO #define JECS_PMA1_BROADCAST_RX_VALID_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xE0) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_SRIO_SIGDET_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xE1) //Attributes : RW #define JECS_PMA1_BROADCAST_SRIO_DEGRADED (JECS_PMA1_BROADCAST_BASE + 4*0xE2) //Attributes : RW #define JECS_PMA1_BROADCAST_SRIO_RETRAIN (JECS_PMA1_BROADCAST_BASE + 4*0xE3) //Attributes : RW #define JECS_PMA1_BROADCAST_SRIO_SHORT_RUN (JECS_PMA1_BROADCAST_BASE + 4*0xE4) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_INIT_C0 (JECS_PMA1_BROADCAST_BASE + 4*0xE5) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_INIT_CN1 (JECS_PMA1_BROADCAST_BASE + 4*0xE6) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_INIT_CP1 (JECS_PMA1_BROADCAST_BASE + 4*0xE7) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_1 (JECS_PMA1_BROADCAST_BASE + 4*0xE8) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_2 (JECS_PMA1_BROADCAST_BASE + 4*0xE9) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_3 (JECS_PMA1_BROADCAST_BASE + 4*0xEA) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_4 (JECS_PMA1_BROADCAST_BASE + 4*0xEB) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_ALGORITHM_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xEC) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_TX_TRAIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xED) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_ADJ_INTERVAL (JECS_PMA1_BROADCAST_BASE + 4*0xEE) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RX_REQ_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xEF) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RX_TRAIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RX_RESET_CYCLE (JECS_PMA1_BROADCAST_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_BROADCAST_RPCS_KTR_STATUS (JECS_PMA1_BROADCAST_BASE + 4*0xF2) //Attributes : RO #define JECS_PMA1_BROADCAST_EQ_FSM (JECS_PMA1_BROADCAST_BASE + 4*0xF3) //Attributes : RO #define JECS_PMA1_BROADCAST_ETH_RX_LOS (JECS_PMA1_BROADCAST_BASE + 4*0xF4) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_PRESET_C0 (JECS_PMA1_BROADCAST_BASE + 4*0xF5) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_PRESET_CN1 (JECS_PMA1_BROADCAST_BASE + 4*0xF6) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_PRESET_CP1 (JECS_PMA1_BROADCAST_BASE + 4*0xF7) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_SUCC_MASK (JECS_PMA1_BROADCAST_BASE + 4*0xF8) //Attributes : RW #define JECS_PMA1_BROADCAST_PMA_COM_SCRATCH (JECS_PMA1_BROADCAST_BASE + 4*0xff) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x108) //Attributes : RW #define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x10D) //Attributes : RW #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x118) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x11D) //Attributes : RW #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x128) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x12D) //Attributes : RW #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x138) //Attributes : RW #define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L #define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT #define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H #define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x13D) //Attributes : RW //The PMA COMMON Register #define JECS_PMA1_MPLLA_PARAM1 (JECS_PMA1_COMMON_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_MPLLA_PARAM2 (JECS_PMA1_COMMON_BASE + 4*0x01) //Attributes : RW #define JECS_PMA1_MPLLA_PARAM3 (JECS_PMA1_COMMON_BASE + 4*0x02) //Attributes : RW #define JECS_PMA1_MPLLA_PARAM4 (JECS_PMA1_COMMON_BASE + 4*0x03) //Attributes : RW #define JECS_PMA1_MPLLA_PARAM5 (JECS_PMA1_COMMON_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_MPLLA_PARAM6 (JECS_PMA1_COMMON_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_MPLLA_FORCE_EN (JECS_PMA1_COMMON_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_MPLLA_FORCE_ACK (JECS_PMA1_COMMON_BASE + 4*0x07) //Attributes : RO #define JECS_PMA1_MPLLB_PARAM1 (JECS_PMA1_COMMON_BASE + 4*0x08) //Attributes : RW #define JECS_PMA1_MPLLB_PARAM2 (JECS_PMA1_COMMON_BASE + 4*0x09) //Attributes : RW #define JECS_PMA1_MPLLB_PARAM3 (JECS_PMA1_COMMON_BASE + 4*0x0A) //Attributes : RW #define JECS_PMA1_MPLLB_PARAM4 (JECS_PMA1_COMMON_BASE + 4*0x0B) //Attributes : RW #define JECS_PMA1_MPLLB_PARAM5 (JECS_PMA1_COMMON_BASE + 4*0x0C) //Attributes : RW #define JECS_PMA1_MPLLB_PARAM6 (JECS_PMA1_COMMON_BASE + 4*0x0D) //Attributes : RW #define JECS_PMA1_MPLLB_FORCE_EN (JECS_PMA1_COMMON_BASE + 4*0x0E) //Attributes : RW #define JECS_PMA1_MPLLB_FORCE_ACK (JECS_PMA1_COMMON_BASE + 4*0x0F) //Attributes : RO #define JECS_PMA1_SUP_MISC (JECS_PMA1_COMMON_BASE + 4*0x16) //Attributes : RW #define JECS_PMA1_MPLLA_FRAC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x17) //Attributes : RW #define JECS_PMA1_MPLLA_FRAC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x18) //Attributes : RW #define JECS_PMA1_MPLLA_FRAC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x19) //Attributes : RW #define JECS_PMA1_MPLLA_FRAC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x1A) //Attributes : RW #define JECS_PMA1_MPLLA_SSC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x1B) //Attributes : RW #define JECS_PMA1_MPLLA_SSC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L #define JECS_PMA1_MPLLA_SSC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H #define JECS_PMA1_MPLLA_SSC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x1E) //Attributes : RW #define JECS_PMA1_MPLLA_SSC_CTRL5 (JECS_PMA1_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L #define JECS_PMA1_MPLLA_SSC_CTRL6 (JECS_PMA1_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H #define JECS_PMA1_MPLLB_FRAC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x21) //Attributes : RW #define JECS_PMA1_MPLLB_FRAC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_MPLLB_FRAC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x23) //Attributes : RW #define JECS_PMA1_MPLLB_FRAC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x24) //Attributes : RW #define JECS_PMA1_MPLLB_SSC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x25) //Attributes : RW #define JECS_PMA1_MPLLB_SSC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L #define JECS_PMA1_MPLLB_SSC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H #define JECS_PMA1_MPLLB_SSC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x28) //Attributes : RW #define JECS_PMA1_MPLLB_SSC_CTRL5 (JECS_PMA1_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L #define JECS_PMA1_MPLLB_SSC_CTRL6 (JECS_PMA1_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H #define JECS_PMA1_MPLLA_RECAL_CTRL (JECS_PMA1_COMMON_BASE + 4*0x2B) //Attributes : RW #define JECS_PMA1_MPLLB_RECAL_CTRL (JECS_PMA1_COMMON_BASE + 4*0x2C) //Attributes : RW #define JECS_PMA1_MPLL_CTRL_MUX (JECS_PMA1_COMMON_BASE + 4*0x2D) //Attributes : RW #define JECS_PMA1_POWER_SUPPLY_SEL (JECS_PMA1_COMMON_BASE + 4*0x30) //Attributes : RW #define JECS_PMA1_PHY_RESET (JECS_PMA1_COMMON_BASE + 4*0x31) //Attributes : RW #define JECS_PMA1_REF_CLK_CTRL (JECS_PMA1_COMMON_BASE + 4*0x40) //Attributes : RW #define JECS_PMA1_REFA_CLK_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x41) //Attributes : RW #define JECS_PMA1_REFA_CLK_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x42) //Attributes : RW #define JECS_PMA1_REFA_CLK_STATUS (JECS_PMA1_COMMON_BASE + 4*0x43) //Attributes : RO #define JECS_PMA1_REFB_CLK_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x44) //Attributes : RW #define JECS_PMA1_REFB_CLK_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x45) //Attributes : RW #define JECS_PMA1_REFB_CLK_STATUS (JECS_PMA1_COMMON_BASE + 4*0x46) //Attributes : RO #define JECS_PMA1_REF_CLK_MUX (JECS_PMA1_COMMON_BASE + 4*0x47) //Attributes : RW #define JECS_PMA1_RES_ACK_IN (JECS_PMA1_COMMON_BASE + 4*0x50) //Attributes : RW #define JECS_PMA1_RES_ACK_OUT (JECS_PMA1_COMMON_BASE + 4*0x51) //Attributes : RO #define JECS_PMA1_RES_REQ_IN (JECS_PMA1_COMMON_BASE + 4*0x52) //Attributes : RW #define JECS_PMA1_RES_REQ_OUT (JECS_PMA1_COMMON_BASE + 4*0x53) //Attributes : RO #define JECS_PMA1_RTUNE_REQ (JECS_PMA1_COMMON_BASE + 4*0x54) //Attributes : RW #define JECS_PMA1_RTUNE_ACK (JECS_PMA1_COMMON_BASE + 4*0x55) //Attributes : RO #define JECS_PMA1_RTUNE_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x56) //Attributes : RW #define JECS_PMA1_RTUNE_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x57) //Attributes : RW #define JECS_PMA1_RTUNE_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x58) //Attributes : RW #define JECS_PMA1_RX_BIAS_CURRENT_CTRL (JECS_PMA1_COMMON_BASE + 4*0x59) //Attributes : RW #define JECS_PMA1_CR_PARA_SEL (JECS_PMA1_COMMON_BASE + 4*0x90) //Attributes : RW #define JECS_PMA1_POWER_GATING_SIGNAL1 (JECS_PMA1_COMMON_BASE + 4*0x60) //Attributes : RW #define JECS_PMA1_POWER_GATING_SIGNAL2 (JECS_PMA1_COMMON_BASE + 4*0x61) //Attributes : RO #define JECS_PMA1_POWER_GATING_SIGNAL3 (JECS_PMA1_COMMON_BASE + 4*0x62) //Attributes : RW #define JECS_PMA1_SRAM_CTRL (JECS_PMA1_COMMON_BASE + 4*0x68) //Attributes : RW #define JECS_PMA1_SRAM_STATUS (JECS_PMA1_COMMON_BASE + 4*0x69) //Attributes : RO #define JECS_PMA1_SRIO_RST_REQ (JECS_PMA1_COMMON_BASE + 4*0x6A) //Attributes : RO #define JECS_PMA1_SRIO_GEN3_EN (JECS_PMA1_COMMON_BASE + 4*0x6C) //Attributes : RW #define JECS_PMA1_SRIO_RATE_OUT (JECS_PMA1_COMMON_BASE + 4*0x6D) //Attributes : RW #define JECS_PMA1_CPRI_RST_REQ (JECS_PMA1_COMMON_BASE + 4*0x70) //Attributes : RW #define JECS_PMA1_CPRI_RX_LOS (JECS_PMA1_COMMON_BASE + 4*0x71) //Attributes : RW #define JECS_PMA1_CPRI_SIGNAL_OK (JECS_PMA1_COMMON_BASE + 4*0x72) //Attributes : RW #define JECS_PMA1_CPRI_ENERGY_DET (JECS_PMA1_COMMON_BASE + 4*0x73) //Attributes : RW #define JECS_PMA1_CPRI_SIGDET (JECS_PMA1_COMMON_BASE + 4*0x74) //Attributes : RW #define JECS_PMA1_CPRI_PCS_STATUS (JECS_PMA1_COMMON_BASE + 4*0x75) //Attributes : RO #define JECS_PMA1_CPRI_PCS_STATUS_CTRL (JECS_PMA1_COMMON_BASE + 4*0x76) //Attributes : RW #define JECS_PMA1_ETH_ENERGY_DET (JECS_PMA1_COMMON_BASE + 4*0x80) //Attributes : RW #define JECS_PMA1_ETH_SPEED_CTRL (JECS_PMA1_COMMON_BASE + 4*0x81) //Attributes : RO #define JECS_PMA1_TX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF0) //Attributes : RW #define JECS_PMA1_RPCS_TX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF1) //Attributes : RW #define JECS_PMA1_RPCS_RX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF2) //Attributes : RW #define JECS_PMA1_PMA_COM_SCRATCH (JECS_PMA1_COMMON_BASE + 4*0xff) //Attributes : RW //The PMA PCS Register #define JECS_PMA1_PCS_SOFT_RESET (JECS_PMA1_PCS_BASE + 4*0x00) //Attributes : RW #define JECS_PMA1_PCS_LOOPBACK_CTRL (JECS_PMA1_PCS_BASE + 4*0x04) //Attributes : RW #define JECS_PMA1_PCS_PRBS_UDP_SEND (JECS_PMA1_PCS_BASE + 4*0x05) //Attributes : RW #define JECS_PMA1_PCS_PRBS_SEND_ERRINS (JECS_PMA1_PCS_BASE + 4*0x06) //Attributes : RW #define JECS_PMA1_PCS_TXUDP_0 (JECS_PMA1_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L #define JECS_PMA1_PCS_TXUDP_1 (JECS_PMA1_PCS_BASE + 4*0x08) //Attributes : RW_EXT #define JECS_PMA1_PCS_TXUDP_2 (JECS_PMA1_PCS_BASE + 4*0x09) //Attributes : RW_EXT #define JECS_PMA1_PCS_TXUDP_3 (JECS_PMA1_PCS_BASE + 4*0x0A) //Attributes : RW_EXT #define JECS_PMA1_PCS_TXUDP_4 (JECS_PMA1_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H #define JECS_PMA1_PCS_PRBS_UDP_CHK (JECS_PMA1_PCS_BASE + 4*0x10) //Attributes : RW #define JECS_PMA1_PCS_RXUDP_0 (JECS_PMA1_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L #define JECS_PMA1_PCS_RXUDP_1 (JECS_PMA1_PCS_BASE + 4*0x12) //Attributes : RW_EXT #define JECS_PMA1_PCS_RXUDP_2 (JECS_PMA1_PCS_BASE + 4*0x13) //Attributes : RW_EXT #define JECS_PMA1_PCS_RXUDP_3 (JECS_PMA1_PCS_BASE + 4*0x14) //Attributes : RW_EXT #define JECS_PMA1_PCS_RXUDP_4 (JECS_PMA1_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H #define JECS_PMA1_PCS_RXPRBS_ERRCNT_L0 (JECS_PMA1_PCS_BASE + 4*0x16) //Attributes : RO #define JECS_PMA1_PCS_RXPRBS_ERRCNT_L1 (JECS_PMA1_PCS_BASE + 4*0x17) //Attributes : RO #define JECS_PMA1_PCS_RXPRBS_ERRCNT_L2 (JECS_PMA1_PCS_BASE + 4*0x18) //Attributes : RO #define JECS_PMA1_PCS_RXPRBS_ERRCNT_L3 (JECS_PMA1_PCS_BASE + 4*0x19) //Attributes : RO #define JECS_PMA1_PCS_NELP_FIFO_STATUS (JECS_PMA1_PCS_BASE + 4*0x20) //Attributes : RO #define JECS_PMA1_PCS_FELP_FIFO_STATUS (JECS_PMA1_PCS_BASE + 4*0x21) //Attributes : RO #define JECS_PMA1_PCS_BIT_REV_CTRL (JECS_PMA1_PCS_BASE + 4*0x22) //Attributes : RW #define JECS_PMA1_PCS_SOFT_PON_RST (JECS_PMA1_PCS_BASE + 4*0xfe) //Attributes : RW #define JECS_PMA1_PCS_PCS_SCRATCH (JECS_PMA1_PCS_BASE + 4*0xff) //Attributes : RW //------------------------PET SUBSYSTEM -------------------------// //The PMA Lane Config Base Addr #define PET_PMA3_LANE0_BASE PET_PMA3_CFG + 0x10000*4 #define PET_PMA3_LANE1_BASE PET_PMA3_CFG + 0x10800*4 #define PET_PMA3_LANE2_BASE PET_PMA3_CFG + 0x11000*4 #define PET_PMA3_LANE3_BASE PET_PMA3_CFG + 0x11800*4 #define PET_PMA3_BROADCAST_BASE PET_PMA3_CFG + 0x12000*4 //The PMA COMMON Base Addr #define PET_PMA3_COMMON_BASE PET_PMA3_CFG + 0x14000*4 //The PMA PCS Addr #define PET_PMA3_PCS_BASE PET_PMA3_CFG + 0x18000*4 //The PMA Lane Config Register #define PET_PMA3_LANE0_PMA_LOOPBACK_CTRL (PET_PMA3_LANE0_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ (PET_PMA3_LANE0_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x02) //Attributes : RO #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE0_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE0_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE0_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE0_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE0_BASE + 4*0x07) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE0_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE0_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE0_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_ADAPT_REQ (PET_PMA3_LANE0_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x11) //Attributes : RO #define PET_PMA3_LANE0_RECEIVER_ADAPT_DIR (PET_PMA3_LANE0_BASE + 4*0x12) //Attributes : RO #define PET_PMA3_LANE0_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE0_BASE + 4*0x13) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x14) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_DATAPATH_EN (PET_PMA3_LANE0_BASE + 4*0x20) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE0_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE0_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE0_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE0_BASE + 4*0x24) //Attributes : RO #define PET_PMA3_LANE0_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE0_BASE + 4*0x25) //Attributes : RO #define PET_PMA3_LANE0_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x26) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_RESET (PET_PMA3_LANE0_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_CONTROL (PET_PMA3_LANE0_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x32) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_RECAL_CTRL (PET_PMA3_LANE0_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_LANE0_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_REQ (PET_PMA3_LANE0_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_LANE0_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE0_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE0_BASE + 4*0x53) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x55) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE0_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE0_BASE + 4*0x61) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE0_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x63) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_CONTROL1 (PET_PMA3_LANE0_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_CONTROL2 (PET_PMA3_LANE0_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_EQ1 (PET_PMA3_LANE0_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_EQ2 (PET_PMA3_LANE0_BASE + 4*0x81) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_EQ3 (PET_PMA3_LANE0_BASE + 4*0x82) //Attributes : RW #define PET_PMA3_LANE0_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x83) //Attributes : RW #define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE0_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE0_BASE + 4*0x91) //Attributes : RW #define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE0_BASE + 4*0x92) //Attributes : RW #define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE0_BASE + 4*0x93) //Attributes : RW #define PET_PMA3_LANE0_CONTEXT_RESTORE_MUX (PET_PMA3_LANE0_BASE + 4*0x94) //Attributes : RW #define PET_PMA3_LANE0_LANE_REFCLK_SEL (PET_PMA3_LANE0_BASE + 4*0xA0) //Attributes : RW #define PET_PMA3_LANE0_ETH_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xB0) //Attributes : RW #define PET_PMA3_LANE0_ETH_CLK_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xB1) //Attributes : RW #define PET_PMA3_LANE0_RX_ADAPT_CTRL (PET_PMA3_LANE0_BASE + 4*0xC0) //Attributes : RW #define PET_PMA3_LANE0_RX_DCC_CTRL (PET_PMA3_LANE0_BASE + 4*0xC1) //Attributes : RW #define PET_PMA3_LANE0_RX_EQ_CTRL1 (PET_PMA3_LANE0_BASE + 4*0xC2) //Attributes : RW #define PET_PMA3_LANE0_RX_EQ_CTRL2 (PET_PMA3_LANE0_BASE + 4*0xC3) //Attributes : RW #define PET_PMA3_LANE0_RX_MARGIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xC4) //Attributes : RW #define PET_PMA3_LANE0_RX_MARGIN_ERROR (PET_PMA3_LANE0_BASE + 4*0xC5) //Attributes : RO #define PET_PMA3_LANE0_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xC6) //Attributes : RW #define PET_PMA3_LANE0_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE0_BASE + 4*0xC8) //Attributes : RW #define PET_PMA3_LANE0_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xC9) //Attributes : RW #define PET_PMA3_LANE0_RX_DIV_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xCA) //Attributes : RW #define PET_PMA3_LANE0_TX_DIV_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xCB) //Attributes : RW #define PET_PMA3_LANE0_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xCC) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_CTRL1 (PET_PMA3_LANE0_BASE + 4*0xD0) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_CTRL2 (PET_PMA3_LANE0_BASE + 4*0xD1) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_CTRL3 (PET_PMA3_LANE0_BASE + 4*0xD2) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_CTRL4 (PET_PMA3_LANE0_BASE + 4*0xD3) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_CTRL5 (PET_PMA3_LANE0_BASE + 4*0xD4) //Attributes : RW #define PET_PMA3_LANE0_TRANS_REQ_MUX (PET_PMA3_LANE0_BASE + 4*0xD5) //Attributes : RW #define PET_PMA3_LANE0_TRANS_INTERFACE_CTRL (PET_PMA3_LANE0_BASE + 4*0xD6) //Attributes : RW #define PET_PMA3_LANE0_TRANS_INTERFACE_MUX (PET_PMA3_LANE0_BASE + 4*0xD7) //Attributes : RW #define PET_PMA3_LANE0_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE0_BASE + 4*0xD8) //Attributes : RW #define PET_PMA3_LANE0_TRANS_PLL_STATE (PET_PMA3_LANE0_BASE + 4*0xD9) //Attributes : RO #define PET_PMA3_LANE0_PLL_STATE_MUX (PET_PMA3_LANE0_BASE + 4*0xDA) //Attributes : RW #define PET_PMA3_LANE0_RX_VALID_PHY (PET_PMA3_LANE0_BASE + 4*0xDF) //Attributes : RO #define PET_PMA3_LANE0_RX_VALID_MUX (PET_PMA3_LANE0_BASE + 4*0xE0) //Attributes : RW #define PET_PMA3_LANE0_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE0_BASE + 4*0xE1) //Attributes : RW #define PET_PMA3_LANE0_SRIO_DEGRADED (PET_PMA3_LANE0_BASE + 4*0xE2) //Attributes : RW #define PET_PMA3_LANE0_SRIO_RETRAIN (PET_PMA3_LANE0_BASE + 4*0xE3) //Attributes : RW #define PET_PMA3_LANE0_SRIO_SHORT_RUN (PET_PMA3_LANE0_BASE + 4*0xE4) //Attributes : RW #define PET_PMA3_LANE0_EQ_INIT_C0 (PET_PMA3_LANE0_BASE + 4*0xE5) //Attributes : RW #define PET_PMA3_LANE0_EQ_INIT_CN1 (PET_PMA3_LANE0_BASE + 4*0xE6) //Attributes : RW #define PET_PMA3_LANE0_EQ_INIT_CP1 (PET_PMA3_LANE0_BASE + 4*0xE7) //Attributes : RW #define PET_PMA3_LANE0_EQ_RULE_CTRL_1 (PET_PMA3_LANE0_BASE + 4*0xE8) //Attributes : RW #define PET_PMA3_LANE0_EQ_RULE_CTRL_2 (PET_PMA3_LANE0_BASE + 4*0xE9) //Attributes : RW #define PET_PMA3_LANE0_EQ_RULE_CTRL_3 (PET_PMA3_LANE0_BASE + 4*0xEA) //Attributes : RW #define PET_PMA3_LANE0_EQ_RULE_CTRL_4 (PET_PMA3_LANE0_BASE + 4*0xEB) //Attributes : RW #define PET_PMA3_LANE0_EQ_ALGORITHM_CTRL (PET_PMA3_LANE0_BASE + 4*0xEC) //Attributes : RW #define PET_PMA3_LANE0_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xED) //Attributes : RW #define PET_PMA3_LANE0_EQ_ADJ_INTERVAL (PET_PMA3_LANE0_BASE + 4*0xEE) //Attributes : RW #define PET_PMA3_LANE0_EQ_RX_REQ_CTRL (PET_PMA3_LANE0_BASE + 4*0xEF) //Attributes : RW #define PET_PMA3_LANE0_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_LANE0_EQ_RX_RESET_CYCLE (PET_PMA3_LANE0_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_LANE0_RPCS_KTR_STATUS (PET_PMA3_LANE0_BASE + 4*0xF2) //Attributes : RO #define PET_PMA3_LANE0_EQ_FSM (PET_PMA3_LANE0_BASE + 4*0xF3) //Attributes : RO #define PET_PMA3_LANE0_ETH_RX_LOS (PET_PMA3_LANE0_BASE + 4*0xF4) //Attributes : RW #define PET_PMA3_LANE0_EQ_PRESET_C0 (PET_PMA3_LANE0_BASE + 4*0xF5) //Attributes : RW #define PET_PMA3_LANE0_EQ_PRESET_CN1 (PET_PMA3_LANE0_BASE + 4*0xF6) //Attributes : RW #define PET_PMA3_LANE0_EQ_PRESET_CP1 (PET_PMA3_LANE0_BASE + 4*0xF7) //Attributes : RW #define PET_PMA3_LANE0_EQ_SUCC_MASK (PET_PMA3_LANE0_BASE + 4*0xF8) //Attributes : RW #define PET_PMA3_LANE0_PMA_COM_SCRATCH (PET_PMA3_LANE0_BASE + 4*0xff) //Attributes : RW #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x101) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x102) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x103) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x104) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x105) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x106) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x108) //Attributes : RW #define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT #define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x10D) //Attributes : RW #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x111) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x112) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x113) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x114) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x115) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x116) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x118) //Attributes : RW #define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x11D) //Attributes : RW #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x121) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x122) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x123) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x124) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x125) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x126) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x128) //Attributes : RW #define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x12D) //Attributes : RW #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x131) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x132) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x133) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x134) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x135) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x136) //Attributes : RO_EXT #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x138) //Attributes : RW #define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L #define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT #define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H #define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x13D) //Attributes : RW #define PET_PMA3_LANE1_PMA_LOOPBACK_CTRL (PET_PMA3_LANE1_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ (PET_PMA3_LANE1_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x02) //Attributes : RO #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE1_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE1_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE1_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE1_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE1_BASE + 4*0x07) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE1_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE1_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE1_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_ADAPT_REQ (PET_PMA3_LANE1_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x11) //Attributes : RO #define PET_PMA3_LANE1_RECEIVER_ADAPT_DIR (PET_PMA3_LANE1_BASE + 4*0x12) //Attributes : RO #define PET_PMA3_LANE1_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE1_BASE + 4*0x13) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x14) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_DATAPATH_EN (PET_PMA3_LANE1_BASE + 4*0x20) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE1_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE1_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE1_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE1_BASE + 4*0x24) //Attributes : RO #define PET_PMA3_LANE1_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE1_BASE + 4*0x25) //Attributes : RO #define PET_PMA3_LANE1_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x26) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_RESET (PET_PMA3_LANE1_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_CONTROL (PET_PMA3_LANE1_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x32) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_RECAL_CTRL (PET_PMA3_LANE1_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_LANE1_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_REQ (PET_PMA3_LANE1_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_LANE1_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE1_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE1_BASE + 4*0x53) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x55) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE1_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE1_BASE + 4*0x61) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE1_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x63) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_CONTROL1 (PET_PMA3_LANE1_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_CONTROL2 (PET_PMA3_LANE1_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_EQ1 (PET_PMA3_LANE1_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_EQ2 (PET_PMA3_LANE1_BASE + 4*0x81) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_EQ3 (PET_PMA3_LANE1_BASE + 4*0x82) //Attributes : RW #define PET_PMA3_LANE1_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x83) //Attributes : RW #define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE1_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE1_BASE + 4*0x91) //Attributes : RW #define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE1_BASE + 4*0x92) //Attributes : RW #define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE1_BASE + 4*0x93) //Attributes : RW #define PET_PMA3_LANE1_CONTEXT_RESTORE_MUX (PET_PMA3_LANE1_BASE + 4*0x94) //Attributes : RW #define PET_PMA3_LANE1_LANE_REFCLK_SEL (PET_PMA3_LANE1_BASE + 4*0xA0) //Attributes : RW #define PET_PMA3_LANE1_ETH_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xB0) //Attributes : RW #define PET_PMA3_LANE1_ETH_CLK_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xB1) //Attributes : RW #define PET_PMA3_LANE1_RX_ADAPT_CTRL (PET_PMA3_LANE1_BASE + 4*0xC0) //Attributes : RW #define PET_PMA3_LANE1_RX_DCC_CTRL (PET_PMA3_LANE1_BASE + 4*0xC1) //Attributes : RW #define PET_PMA3_LANE1_RX_EQ_CTRL1 (PET_PMA3_LANE1_BASE + 4*0xC2) //Attributes : RW #define PET_PMA3_LANE1_RX_EQ_CTRL2 (PET_PMA3_LANE1_BASE + 4*0xC3) //Attributes : RW #define PET_PMA3_LANE1_RX_MARGIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xC4) //Attributes : RW #define PET_PMA3_LANE1_RX_MARGIN_ERROR (PET_PMA3_LANE1_BASE + 4*0xC5) //Attributes : RO #define PET_PMA3_LANE1_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xC6) //Attributes : RW #define PET_PMA3_LANE1_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE1_BASE + 4*0xC8) //Attributes : RW #define PET_PMA3_LANE1_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xC9) //Attributes : RW #define PET_PMA3_LANE1_RX_DIV_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xCA) //Attributes : RW #define PET_PMA3_LANE1_TX_DIV_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xCB) //Attributes : RW #define PET_PMA3_LANE1_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xCC) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_CTRL1 (PET_PMA3_LANE1_BASE + 4*0xD0) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_CTRL2 (PET_PMA3_LANE1_BASE + 4*0xD1) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_CTRL3 (PET_PMA3_LANE1_BASE + 4*0xD2) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_CTRL4 (PET_PMA3_LANE1_BASE + 4*0xD3) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_CTRL5 (PET_PMA3_LANE1_BASE + 4*0xD4) //Attributes : RW #define PET_PMA3_LANE1_TRANS_REQ_MUX (PET_PMA3_LANE1_BASE + 4*0xD5) //Attributes : RW #define PET_PMA3_LANE1_TRANS_INTERFACE_CTRL (PET_PMA3_LANE1_BASE + 4*0xD6) //Attributes : RW #define PET_PMA3_LANE1_TRANS_INTERFACE_MUX (PET_PMA3_LANE1_BASE + 4*0xD7) //Attributes : RW #define PET_PMA3_LANE1_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE1_BASE + 4*0xD8) //Attributes : RW #define PET_PMA3_LANE1_TRANS_PLL_STATE (PET_PMA3_LANE1_BASE + 4*0xD9) //Attributes : RO #define PET_PMA3_LANE1_PLL_STATE_MUX (PET_PMA3_LANE1_BASE + 4*0xDA) //Attributes : RW #define PET_PMA3_LANE1_RX_VALID_PHY (PET_PMA3_LANE1_BASE + 4*0xDF) //Attributes : RO #define PET_PMA3_LANE1_RX_VALID_MUX (PET_PMA3_LANE1_BASE + 4*0xE0) //Attributes : RW #define PET_PMA3_LANE1_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE1_BASE + 4*0xE1) //Attributes : RW #define PET_PMA3_LANE1_SRIO_DEGRADED (PET_PMA3_LANE1_BASE + 4*0xE2) //Attributes : RW #define PET_PMA3_LANE1_SRIO_RETRAIN (PET_PMA3_LANE1_BASE + 4*0xE3) //Attributes : RW #define PET_PMA3_LANE1_SRIO_SHORT_RUN (PET_PMA3_LANE1_BASE + 4*0xE4) //Attributes : RW #define PET_PMA3_LANE1_EQ_INIT_C0 (PET_PMA3_LANE1_BASE + 4*0xE5) //Attributes : RW #define PET_PMA3_LANE1_EQ_INIT_CN1 (PET_PMA3_LANE1_BASE + 4*0xE6) //Attributes : RW #define PET_PMA3_LANE1_EQ_INIT_CP1 (PET_PMA3_LANE1_BASE + 4*0xE7) //Attributes : RW #define PET_PMA3_LANE1_EQ_RULE_CTRL_1 (PET_PMA3_LANE1_BASE + 4*0xE8) //Attributes : RW #define PET_PMA3_LANE1_EQ_RULE_CTRL_2 (PET_PMA3_LANE1_BASE + 4*0xE9) //Attributes : RW #define PET_PMA3_LANE1_EQ_RULE_CTRL_3 (PET_PMA3_LANE1_BASE + 4*0xEA) //Attributes : RW #define PET_PMA3_LANE1_EQ_RULE_CTRL_4 (PET_PMA3_LANE1_BASE + 4*0xEB) //Attributes : RW #define PET_PMA3_LANE1_EQ_ALGORITHM_CTRL (PET_PMA3_LANE1_BASE + 4*0xEC) //Attributes : RW #define PET_PMA3_LANE1_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xED) //Attributes : RW #define PET_PMA3_LANE1_EQ_ADJ_INTERVAL (PET_PMA3_LANE1_BASE + 4*0xEE) //Attributes : RW #define PET_PMA3_LANE1_EQ_RX_REQ_CTRL (PET_PMA3_LANE1_BASE + 4*0xEF) //Attributes : RW #define PET_PMA3_LANE1_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_LANE1_EQ_RX_RESET_CYCLE (PET_PMA3_LANE1_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_LANE1_RPCS_KTR_STATUS (PET_PMA3_LANE1_BASE + 4*0xF2) //Attributes : RO #define PET_PMA3_LANE1_EQ_FSM (PET_PMA3_LANE1_BASE + 4*0xF3) //Attributes : RO #define PET_PMA3_LANE1_ETH_RX_LOS (PET_PMA3_LANE1_BASE + 4*0xF4) //Attributes : RW #define PET_PMA3_LANE1_EQ_PRESET_C0 (PET_PMA3_LANE1_BASE + 4*0xF5) //Attributes : RW #define PET_PMA3_LANE1_EQ_PRESET_CN1 (PET_PMA3_LANE1_BASE + 4*0xF6) //Attributes : RW #define PET_PMA3_LANE1_EQ_PRESET_CP1 (PET_PMA3_LANE1_BASE + 4*0xF7) //Attributes : RW #define PET_PMA3_LANE1_EQ_SUCC_MASK (PET_PMA3_LANE1_BASE + 4*0xF8) //Attributes : RW #define PET_PMA3_LANE1_PMA_COM_SCRATCH (PET_PMA3_LANE1_BASE + 4*0xff) //Attributes : RW #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x101) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x102) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x103) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x104) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x105) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x106) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x108) //Attributes : RW #define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT #define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x10D) //Attributes : RW #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x111) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x112) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x113) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x114) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x115) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x116) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x118) //Attributes : RW #define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x11D) //Attributes : RW #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x121) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x122) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x123) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x124) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x125) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x126) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x128) //Attributes : RW #define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x12D) //Attributes : RW #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x131) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x132) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x133) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x134) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x135) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x136) //Attributes : RO_EXT #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x138) //Attributes : RW #define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L #define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT #define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H #define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x13D) //Attributes : RW #define PET_PMA3_LANE2_PMA_LOOPBACK_CTRL (PET_PMA3_LANE2_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ (PET_PMA3_LANE2_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x02) //Attributes : RO #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE2_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE2_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE2_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE2_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE2_BASE + 4*0x07) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE2_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE2_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE2_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_ADAPT_REQ (PET_PMA3_LANE2_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x11) //Attributes : RO #define PET_PMA3_LANE2_RECEIVER_ADAPT_DIR (PET_PMA3_LANE2_BASE + 4*0x12) //Attributes : RO #define PET_PMA3_LANE2_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE2_BASE + 4*0x13) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x14) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_DATAPATH_EN (PET_PMA3_LANE2_BASE + 4*0x20) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE2_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE2_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE2_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE2_BASE + 4*0x24) //Attributes : RO #define PET_PMA3_LANE2_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE2_BASE + 4*0x25) //Attributes : RO #define PET_PMA3_LANE2_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x26) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_RESET (PET_PMA3_LANE2_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_CONTROL (PET_PMA3_LANE2_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x32) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_RECAL_CTRL (PET_PMA3_LANE2_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_LANE2_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_REQ (PET_PMA3_LANE2_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_LANE2_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE2_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE2_BASE + 4*0x53) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x55) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE2_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE2_BASE + 4*0x61) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE2_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x63) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_CONTROL1 (PET_PMA3_LANE2_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_CONTROL2 (PET_PMA3_LANE2_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_EQ1 (PET_PMA3_LANE2_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_EQ2 (PET_PMA3_LANE2_BASE + 4*0x81) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_EQ3 (PET_PMA3_LANE2_BASE + 4*0x82) //Attributes : RW #define PET_PMA3_LANE2_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x83) //Attributes : RW #define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE2_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE2_BASE + 4*0x91) //Attributes : RW #define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE2_BASE + 4*0x92) //Attributes : RW #define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE2_BASE + 4*0x93) //Attributes : RW #define PET_PMA3_LANE2_CONTEXT_RESTORE_MUX (PET_PMA3_LANE2_BASE + 4*0x94) //Attributes : RW #define PET_PMA3_LANE2_LANE_REFCLK_SEL (PET_PMA3_LANE2_BASE + 4*0xA0) //Attributes : RW #define PET_PMA3_LANE2_ETH_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xB0) //Attributes : RW #define PET_PMA3_LANE2_ETH_CLK_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xB1) //Attributes : RW #define PET_PMA3_LANE2_RX_ADAPT_CTRL (PET_PMA3_LANE2_BASE + 4*0xC0) //Attributes : RW #define PET_PMA3_LANE2_RX_DCC_CTRL (PET_PMA3_LANE2_BASE + 4*0xC1) //Attributes : RW #define PET_PMA3_LANE2_RX_EQ_CTRL1 (PET_PMA3_LANE2_BASE + 4*0xC2) //Attributes : RW #define PET_PMA3_LANE2_RX_EQ_CTRL2 (PET_PMA3_LANE2_BASE + 4*0xC3) //Attributes : RW #define PET_PMA3_LANE2_RX_MARGIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xC4) //Attributes : RW #define PET_PMA3_LANE2_RX_MARGIN_ERROR (PET_PMA3_LANE2_BASE + 4*0xC5) //Attributes : RO #define PET_PMA3_LANE2_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xC6) //Attributes : RW #define PET_PMA3_LANE2_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE2_BASE + 4*0xC8) //Attributes : RW #define PET_PMA3_LANE2_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xC9) //Attributes : RW #define PET_PMA3_LANE2_RX_DIV_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xCA) //Attributes : RW #define PET_PMA3_LANE2_TX_DIV_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xCB) //Attributes : RW #define PET_PMA3_LANE2_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xCC) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_CTRL1 (PET_PMA3_LANE2_BASE + 4*0xD0) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_CTRL2 (PET_PMA3_LANE2_BASE + 4*0xD1) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_CTRL3 (PET_PMA3_LANE2_BASE + 4*0xD2) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_CTRL4 (PET_PMA3_LANE2_BASE + 4*0xD3) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_CTRL5 (PET_PMA3_LANE2_BASE + 4*0xD4) //Attributes : RW #define PET_PMA3_LANE2_TRANS_REQ_MUX (PET_PMA3_LANE2_BASE + 4*0xD5) //Attributes : RW #define PET_PMA3_LANE2_TRANS_INTERFACE_CTRL (PET_PMA3_LANE2_BASE + 4*0xD6) //Attributes : RW #define PET_PMA3_LANE2_TRANS_INTERFACE_MUX (PET_PMA3_LANE2_BASE + 4*0xD7) //Attributes : RW #define PET_PMA3_LANE2_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE2_BASE + 4*0xD8) //Attributes : RW #define PET_PMA3_LANE2_TRANS_PLL_STATE (PET_PMA3_LANE2_BASE + 4*0xD9) //Attributes : RO #define PET_PMA3_LANE2_PLL_STATE_MUX (PET_PMA3_LANE2_BASE + 4*0xDA) //Attributes : RW #define PET_PMA3_LANE2_RX_VALID_PHY (PET_PMA3_LANE2_BASE + 4*0xDF) //Attributes : RO #define PET_PMA3_LANE2_RX_VALID_MUX (PET_PMA3_LANE2_BASE + 4*0xE0) //Attributes : RW #define PET_PMA3_LANE2_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE2_BASE + 4*0xE1) //Attributes : RW #define PET_PMA3_LANE2_SRIO_DEGRADED (PET_PMA3_LANE2_BASE + 4*0xE2) //Attributes : RW #define PET_PMA3_LANE2_SRIO_RETRAIN (PET_PMA3_LANE2_BASE + 4*0xE3) //Attributes : RW #define PET_PMA3_LANE2_SRIO_SHORT_RUN (PET_PMA3_LANE2_BASE + 4*0xE4) //Attributes : RW #define PET_PMA3_LANE2_EQ_INIT_C0 (PET_PMA3_LANE2_BASE + 4*0xE5) //Attributes : RW #define PET_PMA3_LANE2_EQ_INIT_CN1 (PET_PMA3_LANE2_BASE + 4*0xE6) //Attributes : RW #define PET_PMA3_LANE2_EQ_INIT_CP1 (PET_PMA3_LANE2_BASE + 4*0xE7) //Attributes : RW #define PET_PMA3_LANE2_EQ_RULE_CTRL_1 (PET_PMA3_LANE2_BASE + 4*0xE8) //Attributes : RW #define PET_PMA3_LANE2_EQ_RULE_CTRL_2 (PET_PMA3_LANE2_BASE + 4*0xE9) //Attributes : RW #define PET_PMA3_LANE2_EQ_RULE_CTRL_3 (PET_PMA3_LANE2_BASE + 4*0xEA) //Attributes : RW #define PET_PMA3_LANE2_EQ_RULE_CTRL_4 (PET_PMA3_LANE2_BASE + 4*0xEB) //Attributes : RW #define PET_PMA3_LANE2_EQ_ALGORITHM_CTRL (PET_PMA3_LANE2_BASE + 4*0xEC) //Attributes : RW #define PET_PMA3_LANE2_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xED) //Attributes : RW #define PET_PMA3_LANE2_EQ_ADJ_INTERVAL (PET_PMA3_LANE2_BASE + 4*0xEE) //Attributes : RW #define PET_PMA3_LANE2_EQ_RX_REQ_CTRL (PET_PMA3_LANE2_BASE + 4*0xEF) //Attributes : RW #define PET_PMA3_LANE2_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_LANE2_EQ_RX_RESET_CYCLE (PET_PMA3_LANE2_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_LANE2_RPCS_KTR_STATUS (PET_PMA3_LANE2_BASE + 4*0xF2) //Attributes : RO #define PET_PMA3_LANE2_EQ_FSM (PET_PMA3_LANE2_BASE + 4*0xF3) //Attributes : RO #define PET_PMA3_LANE2_ETH_RX_LOS (PET_PMA3_LANE2_BASE + 4*0xF4) //Attributes : RW #define PET_PMA3_LANE2_EQ_PRESET_C0 (PET_PMA3_LANE2_BASE + 4*0xF5) //Attributes : RW #define PET_PMA3_LANE2_EQ_PRESET_CN1 (PET_PMA3_LANE2_BASE + 4*0xF6) //Attributes : RW #define PET_PMA3_LANE2_EQ_PRESET_CP1 (PET_PMA3_LANE2_BASE + 4*0xF7) //Attributes : RW #define PET_PMA3_LANE2_EQ_SUCC_MASK (PET_PMA3_LANE2_BASE + 4*0xF8) //Attributes : RW #define PET_PMA3_LANE2_PMA_COM_SCRATCH (PET_PMA3_LANE2_BASE + 4*0xff) //Attributes : RW #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x101) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x102) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x103) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x104) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x105) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x106) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x108) //Attributes : RW #define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT #define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x10D) //Attributes : RW #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x111) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x112) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x113) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x114) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x115) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x116) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x118) //Attributes : RW #define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x11D) //Attributes : RW #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x121) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x122) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x123) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x124) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x125) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x126) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x128) //Attributes : RW #define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x12D) //Attributes : RW #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x131) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x132) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x133) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x134) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x135) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x136) //Attributes : RO_EXT #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x138) //Attributes : RW #define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L #define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT #define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H #define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x13D) //Attributes : RW #define PET_PMA3_LANE3_PMA_LOOPBACK_CTRL (PET_PMA3_LANE3_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ (PET_PMA3_LANE3_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x02) //Attributes : RO #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE3_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE3_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE3_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE3_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE3_BASE + 4*0x07) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE3_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE3_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE3_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_ADAPT_REQ (PET_PMA3_LANE3_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x11) //Attributes : RO #define PET_PMA3_LANE3_RECEIVER_ADAPT_DIR (PET_PMA3_LANE3_BASE + 4*0x12) //Attributes : RO #define PET_PMA3_LANE3_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE3_BASE + 4*0x13) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x14) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_DATAPATH_EN (PET_PMA3_LANE3_BASE + 4*0x20) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE3_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE3_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE3_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE3_BASE + 4*0x24) //Attributes : RO #define PET_PMA3_LANE3_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE3_BASE + 4*0x25) //Attributes : RO #define PET_PMA3_LANE3_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x26) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_RESET (PET_PMA3_LANE3_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_CONTROL (PET_PMA3_LANE3_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x32) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_RECAL_CTRL (PET_PMA3_LANE3_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_LANE3_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_REQ (PET_PMA3_LANE3_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_LANE3_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE3_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE3_BASE + 4*0x53) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x55) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE3_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE3_BASE + 4*0x61) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE3_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x63) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_CONTROL1 (PET_PMA3_LANE3_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_CONTROL2 (PET_PMA3_LANE3_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_EQ1 (PET_PMA3_LANE3_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_EQ2 (PET_PMA3_LANE3_BASE + 4*0x81) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_EQ3 (PET_PMA3_LANE3_BASE + 4*0x82) //Attributes : RW #define PET_PMA3_LANE3_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x83) //Attributes : RW #define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE3_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE3_BASE + 4*0x91) //Attributes : RW #define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE3_BASE + 4*0x92) //Attributes : RW #define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE3_BASE + 4*0x93) //Attributes : RW #define PET_PMA3_LANE3_CONTEXT_RESTORE_MUX (PET_PMA3_LANE3_BASE + 4*0x94) //Attributes : RW #define PET_PMA3_LANE3_LANE_REFCLK_SEL (PET_PMA3_LANE3_BASE + 4*0xA0) //Attributes : RW #define PET_PMA3_LANE3_ETH_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xB0) //Attributes : RW #define PET_PMA3_LANE3_ETH_CLK_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xB1) //Attributes : RW #define PET_PMA3_LANE3_RX_ADAPT_CTRL (PET_PMA3_LANE3_BASE + 4*0xC0) //Attributes : RW #define PET_PMA3_LANE3_RX_DCC_CTRL (PET_PMA3_LANE3_BASE + 4*0xC1) //Attributes : RW #define PET_PMA3_LANE3_RX_EQ_CTRL1 (PET_PMA3_LANE3_BASE + 4*0xC2) //Attributes : RW #define PET_PMA3_LANE3_RX_EQ_CTRL2 (PET_PMA3_LANE3_BASE + 4*0xC3) //Attributes : RW #define PET_PMA3_LANE3_RX_MARGIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xC4) //Attributes : RW #define PET_PMA3_LANE3_RX_MARGIN_ERROR (PET_PMA3_LANE3_BASE + 4*0xC5) //Attributes : RO #define PET_PMA3_LANE3_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xC6) //Attributes : RW #define PET_PMA3_LANE3_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE3_BASE + 4*0xC8) //Attributes : RW #define PET_PMA3_LANE3_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xC9) //Attributes : RW #define PET_PMA3_LANE3_RX_DIV_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xCA) //Attributes : RW #define PET_PMA3_LANE3_TX_DIV_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xCB) //Attributes : RW #define PET_PMA3_LANE3_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xCC) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_CTRL1 (PET_PMA3_LANE3_BASE + 4*0xD0) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_CTRL2 (PET_PMA3_LANE3_BASE + 4*0xD1) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_CTRL3 (PET_PMA3_LANE3_BASE + 4*0xD2) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_CTRL4 (PET_PMA3_LANE3_BASE + 4*0xD3) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_CTRL5 (PET_PMA3_LANE3_BASE + 4*0xD4) //Attributes : RW #define PET_PMA3_LANE3_TRANS_REQ_MUX (PET_PMA3_LANE3_BASE + 4*0xD5) //Attributes : RW #define PET_PMA3_LANE3_TRANS_INTERFACE_CTRL (PET_PMA3_LANE3_BASE + 4*0xD6) //Attributes : RW #define PET_PMA3_LANE3_TRANS_INTERFACE_MUX (PET_PMA3_LANE3_BASE + 4*0xD7) //Attributes : RW #define PET_PMA3_LANE3_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE3_BASE + 4*0xD8) //Attributes : RW #define PET_PMA3_LANE3_TRANS_PLL_STATE (PET_PMA3_LANE3_BASE + 4*0xD9) //Attributes : RO #define PET_PMA3_LANE3_PLL_STATE_MUX (PET_PMA3_LANE3_BASE + 4*0xDA) //Attributes : RW #define PET_PMA3_LANE3_RX_VALID_PHY (PET_PMA3_LANE3_BASE + 4*0xDF) //Attributes : RO #define PET_PMA3_LANE3_RX_VALID_MUX (PET_PMA3_LANE3_BASE + 4*0xE0) //Attributes : RW #define PET_PMA3_LANE3_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE3_BASE + 4*0xE1) //Attributes : RW #define PET_PMA3_LANE3_SRIO_DEGRADED (PET_PMA3_LANE3_BASE + 4*0xE2) //Attributes : RW #define PET_PMA3_LANE3_SRIO_RETRAIN (PET_PMA3_LANE3_BASE + 4*0xE3) //Attributes : RW #define PET_PMA3_LANE3_SRIO_SHORT_RUN (PET_PMA3_LANE3_BASE + 4*0xE4) //Attributes : RW #define PET_PMA3_LANE3_EQ_INIT_C0 (PET_PMA3_LANE3_BASE + 4*0xE5) //Attributes : RW #define PET_PMA3_LANE3_EQ_INIT_CN1 (PET_PMA3_LANE3_BASE + 4*0xE6) //Attributes : RW #define PET_PMA3_LANE3_EQ_INIT_CP1 (PET_PMA3_LANE3_BASE + 4*0xE7) //Attributes : RW #define PET_PMA3_LANE3_EQ_RULE_CTRL_1 (PET_PMA3_LANE3_BASE + 4*0xE8) //Attributes : RW #define PET_PMA3_LANE3_EQ_RULE_CTRL_2 (PET_PMA3_LANE3_BASE + 4*0xE9) //Attributes : RW #define PET_PMA3_LANE3_EQ_RULE_CTRL_3 (PET_PMA3_LANE3_BASE + 4*0xEA) //Attributes : RW #define PET_PMA3_LANE3_EQ_RULE_CTRL_4 (PET_PMA3_LANE3_BASE + 4*0xEB) //Attributes : RW #define PET_PMA3_LANE3_EQ_ALGORITHM_CTRL (PET_PMA3_LANE3_BASE + 4*0xEC) //Attributes : RW #define PET_PMA3_LANE3_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xED) //Attributes : RW #define PET_PMA3_LANE3_EQ_ADJ_INTERVAL (PET_PMA3_LANE3_BASE + 4*0xEE) //Attributes : RW #define PET_PMA3_LANE3_EQ_RX_REQ_CTRL (PET_PMA3_LANE3_BASE + 4*0xEF) //Attributes : RW #define PET_PMA3_LANE3_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_LANE3_EQ_RX_RESET_CYCLE (PET_PMA3_LANE3_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_LANE3_RPCS_KTR_STATUS (PET_PMA3_LANE3_BASE + 4*0xF2) //Attributes : RO #define PET_PMA3_LANE3_EQ_FSM (PET_PMA3_LANE3_BASE + 4*0xF3) //Attributes : RO #define PET_PMA3_LANE3_ETH_RX_LOS (PET_PMA3_LANE3_BASE + 4*0xF4) //Attributes : RW #define PET_PMA3_LANE3_EQ_PRESET_C0 (PET_PMA3_LANE3_BASE + 4*0xF5) //Attributes : RW #define PET_PMA3_LANE3_EQ_PRESET_CN1 (PET_PMA3_LANE3_BASE + 4*0xF6) //Attributes : RW #define PET_PMA3_LANE3_EQ_PRESET_CP1 (PET_PMA3_LANE3_BASE + 4*0xF7) //Attributes : RW #define PET_PMA3_LANE3_EQ_SUCC_MASK (PET_PMA3_LANE3_BASE + 4*0xF8) //Attributes : RW #define PET_PMA3_LANE3_PMA_COM_SCRATCH (PET_PMA3_LANE3_BASE + 4*0xff) //Attributes : RW #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x101) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x102) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x103) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x104) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x105) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x106) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x108) //Attributes : RW #define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT #define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x10D) //Attributes : RW #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x111) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x112) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x113) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x114) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x115) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x116) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x118) //Attributes : RW #define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x11D) //Attributes : RW #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x121) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x122) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x123) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x124) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x125) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x126) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x128) //Attributes : RW #define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x12D) //Attributes : RW #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x131) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x132) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x133) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x134) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x135) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x136) //Attributes : RO_EXT #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x138) //Attributes : RW #define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L #define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT #define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H #define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x13D) //Attributes : RW #define PET_PMA3_BROADCAST_PMA_LOOPBACK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ (PET_PMA3_BROADCAST_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x02) //Attributes : RO #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM2 (PET_PMA3_BROADCAST_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM3 (PET_PMA3_BROADCAST_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM4 (PET_PMA3_BROADCAST_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM5 (PET_PMA3_BROADCAST_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM6 (PET_PMA3_BROADCAST_BASE + 4*0x07) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM7 (PET_PMA3_BROADCAST_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM8 (PET_PMA3_BROADCAST_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM9 (PET_PMA3_BROADCAST_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_REQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_ADAPT_REQ (PET_PMA3_BROADCAST_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x11) //Attributes : RO #define PET_PMA3_BROADCAST_RECEIVER_ADAPT_DIR (PET_PMA3_BROADCAST_BASE + 4*0x12) //Attributes : RO #define PET_PMA3_BROADCAST_RECEIVER_ADAPT_SETTING (PET_PMA3_BROADCAST_BASE + 4*0x13) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x14) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_EN (PET_PMA3_BROADCAST_BASE + 4*0x20) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_BROADCAST_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_BROADCAST_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_BROADCAST_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_BROADCAST_BASE + 4*0x24) //Attributes : RO #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_BROADCAST_BASE + 4*0x25) //Attributes : RO #define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x26) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_RESET (PET_PMA3_BROADCAST_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_CONTROL (PET_PMA3_BROADCAST_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x32) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_RECAL_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_BROADCAST_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_REQ (PET_PMA3_BROADCAST_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM1 (PET_PMA3_BROADCAST_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM2 (PET_PMA3_BROADCAST_BASE + 4*0x53) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x55) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_EN (PET_PMA3_BROADCAST_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_BROADCAST_BASE + 4*0x61) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_BROADCAST_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x63) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL1 (PET_PMA3_BROADCAST_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL2 (PET_PMA3_BROADCAST_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_EQ1 (PET_PMA3_BROADCAST_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_EQ2 (PET_PMA3_BROADCAST_BASE + 4*0x81) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_EQ3 (PET_PMA3_BROADCAST_BASE + 4*0x82) //Attributes : RW #define PET_PMA3_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x83) //Attributes : RW #define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0x91) //Attributes : RW #define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL3 (PET_PMA3_BROADCAST_BASE + 4*0x92) //Attributes : RW #define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL4 (PET_PMA3_BROADCAST_BASE + 4*0x93) //Attributes : RW #define PET_PMA3_BROADCAST_CONTEXT_RESTORE_MUX (PET_PMA3_BROADCAST_BASE + 4*0x94) //Attributes : RW #define PET_PMA3_BROADCAST_LANE_REFCLK_SEL (PET_PMA3_BROADCAST_BASE + 4*0xA0) //Attributes : RW #define PET_PMA3_BROADCAST_ETH_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xB0) //Attributes : RW #define PET_PMA3_BROADCAST_ETH_CLK_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xB1) //Attributes : RW #define PET_PMA3_BROADCAST_RX_ADAPT_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC0) //Attributes : RW #define PET_PMA3_BROADCAST_RX_DCC_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC1) //Attributes : RW #define PET_PMA3_BROADCAST_RX_EQ_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0xC2) //Attributes : RW #define PET_PMA3_BROADCAST_RX_EQ_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0xC3) //Attributes : RW #define PET_PMA3_BROADCAST_RX_MARGIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC4) //Attributes : RW #define PET_PMA3_BROADCAST_RX_MARGIN_ERROR (PET_PMA3_BROADCAST_BASE + 4*0xC5) //Attributes : RO #define PET_PMA3_BROADCAST_RECV_REQUEST_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xC6) //Attributes : RW #define PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC8) //Attributes : RW #define PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xC9) //Attributes : RW #define PET_PMA3_BROADCAST_RX_DIV_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xCA) //Attributes : RW #define PET_PMA3_BROADCAST_TX_DIV_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xCB) //Attributes : RW #define PET_PMA3_BROADCAST_MULTI_CLK_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xCC) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0xD0) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0xD1) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_CTRL3 (PET_PMA3_BROADCAST_BASE + 4*0xD2) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_CTRL4 (PET_PMA3_BROADCAST_BASE + 4*0xD3) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_CTRL5 (PET_PMA3_BROADCAST_BASE + 4*0xD4) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_REQ_MUX (PET_PMA3_BROADCAST_BASE + 4*0xD5) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_INTERFACE_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xD6) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_INTERFACE_MUX (PET_PMA3_BROADCAST_BASE + 4*0xD7) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_MASTER_PLL_STATE (PET_PMA3_BROADCAST_BASE + 4*0xD8) //Attributes : RW #define PET_PMA3_BROADCAST_TRANS_PLL_STATE (PET_PMA3_BROADCAST_BASE + 4*0xD9) //Attributes : RO #define PET_PMA3_BROADCAST_PLL_STATE_MUX (PET_PMA3_BROADCAST_BASE + 4*0xDA) //Attributes : RW #define PET_PMA3_BROADCAST_RX_VALID_PHY (PET_PMA3_BROADCAST_BASE + 4*0xDF) //Attributes : RO #define PET_PMA3_BROADCAST_RX_VALID_MUX (PET_PMA3_BROADCAST_BASE + 4*0xE0) //Attributes : RW #define PET_PMA3_BROADCAST_RX_SRIO_SIGDET_MUX (PET_PMA3_BROADCAST_BASE + 4*0xE1) //Attributes : RW #define PET_PMA3_BROADCAST_SRIO_DEGRADED (PET_PMA3_BROADCAST_BASE + 4*0xE2) //Attributes : RW #define PET_PMA3_BROADCAST_SRIO_RETRAIN (PET_PMA3_BROADCAST_BASE + 4*0xE3) //Attributes : RW #define PET_PMA3_BROADCAST_SRIO_SHORT_RUN (PET_PMA3_BROADCAST_BASE + 4*0xE4) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_INIT_C0 (PET_PMA3_BROADCAST_BASE + 4*0xE5) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_INIT_CN1 (PET_PMA3_BROADCAST_BASE + 4*0xE6) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_INIT_CP1 (PET_PMA3_BROADCAST_BASE + 4*0xE7) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RULE_CTRL_1 (PET_PMA3_BROADCAST_BASE + 4*0xE8) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RULE_CTRL_2 (PET_PMA3_BROADCAST_BASE + 4*0xE9) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RULE_CTRL_3 (PET_PMA3_BROADCAST_BASE + 4*0xEA) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RULE_CTRL_4 (PET_PMA3_BROADCAST_BASE + 4*0xEB) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_ALGORITHM_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xEC) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_TX_TRAIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xED) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_ADJ_INTERVAL (PET_PMA3_BROADCAST_BASE + 4*0xEE) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RX_REQ_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xEF) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RX_TRAIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RX_RESET_CYCLE (PET_PMA3_BROADCAST_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_BROADCAST_RPCS_KTR_STATUS (PET_PMA3_BROADCAST_BASE + 4*0xF2) //Attributes : RO #define PET_PMA3_BROADCAST_EQ_FSM (PET_PMA3_BROADCAST_BASE + 4*0xF3) //Attributes : RO #define PET_PMA3_BROADCAST_ETH_RX_LOS (PET_PMA3_BROADCAST_BASE + 4*0xF4) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_PRESET_C0 (PET_PMA3_BROADCAST_BASE + 4*0xF5) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_PRESET_CN1 (PET_PMA3_BROADCAST_BASE + 4*0xF6) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_PRESET_CP1 (PET_PMA3_BROADCAST_BASE + 4*0xF7) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_SUCC_MASK (PET_PMA3_BROADCAST_BASE + 4*0xF8) //Attributes : RW #define PET_PMA3_BROADCAST_PMA_COM_SCRATCH (PET_PMA3_BROADCAST_BASE + 4*0xff) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x108) //Attributes : RW #define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x10D) //Attributes : RW #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x118) //Attributes : RW #define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x11D) //Attributes : RW #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x128) //Attributes : RW #define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x12D) //Attributes : RW #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x138) //Attributes : RW #define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L #define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT #define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H #define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x13D) //Attributes : RW //The PMA COMMON Register #define PET_PMA3_MPLLA_PARAM1 (PET_PMA3_COMMON_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_MPLLA_PARAM2 (PET_PMA3_COMMON_BASE + 4*0x01) //Attributes : RW #define PET_PMA3_MPLLA_PARAM3 (PET_PMA3_COMMON_BASE + 4*0x02) //Attributes : RW #define PET_PMA3_MPLLA_PARAM4 (PET_PMA3_COMMON_BASE + 4*0x03) //Attributes : RW #define PET_PMA3_MPLLA_PARAM5 (PET_PMA3_COMMON_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_MPLLA_PARAM6 (PET_PMA3_COMMON_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_MPLLA_FORCE_EN (PET_PMA3_COMMON_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_MPLLA_FORCE_ACK (PET_PMA3_COMMON_BASE + 4*0x07) //Attributes : RO #define PET_PMA3_MPLLB_PARAM1 (PET_PMA3_COMMON_BASE + 4*0x08) //Attributes : RW #define PET_PMA3_MPLLB_PARAM2 (PET_PMA3_COMMON_BASE + 4*0x09) //Attributes : RW #define PET_PMA3_MPLLB_PARAM3 (PET_PMA3_COMMON_BASE + 4*0x0A) //Attributes : RW #define PET_PMA3_MPLLB_PARAM4 (PET_PMA3_COMMON_BASE + 4*0x0B) //Attributes : RW #define PET_PMA3_MPLLB_PARAM5 (PET_PMA3_COMMON_BASE + 4*0x0C) //Attributes : RW #define PET_PMA3_MPLLB_PARAM6 (PET_PMA3_COMMON_BASE + 4*0x0D) //Attributes : RW #define PET_PMA3_MPLLB_FORCE_EN (PET_PMA3_COMMON_BASE + 4*0x0E) //Attributes : RW #define PET_PMA3_MPLLB_FORCE_ACK (PET_PMA3_COMMON_BASE + 4*0x0F) //Attributes : RO #define PET_PMA3_SUP_MISC (PET_PMA3_COMMON_BASE + 4*0x16) //Attributes : RW #define PET_PMA3_MPLLA_FRAC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x17) //Attributes : RW #define PET_PMA3_MPLLA_FRAC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x18) //Attributes : RW #define PET_PMA3_MPLLA_FRAC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x19) //Attributes : RW #define PET_PMA3_MPLLA_FRAC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x1A) //Attributes : RW #define PET_PMA3_MPLLA_SSC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x1B) //Attributes : RW #define PET_PMA3_MPLLA_SSC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L #define PET_PMA3_MPLLA_SSC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H #define PET_PMA3_MPLLA_SSC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x1E) //Attributes : RW #define PET_PMA3_MPLLA_SSC_CTRL5 (PET_PMA3_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L #define PET_PMA3_MPLLA_SSC_CTRL6 (PET_PMA3_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H #define PET_PMA3_MPLLB_FRAC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x21) //Attributes : RW #define PET_PMA3_MPLLB_FRAC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_MPLLB_FRAC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x23) //Attributes : RW #define PET_PMA3_MPLLB_FRAC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x24) //Attributes : RW #define PET_PMA3_MPLLB_SSC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x25) //Attributes : RW #define PET_PMA3_MPLLB_SSC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L #define PET_PMA3_MPLLB_SSC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H #define PET_PMA3_MPLLB_SSC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x28) //Attributes : RW #define PET_PMA3_MPLLB_SSC_CTRL5 (PET_PMA3_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L #define PET_PMA3_MPLLB_SSC_CTRL6 (PET_PMA3_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H #define PET_PMA3_MPLLA_RECAL_CTRL (PET_PMA3_COMMON_BASE + 4*0x2B) //Attributes : RW #define PET_PMA3_MPLLB_RECAL_CTRL (PET_PMA3_COMMON_BASE + 4*0x2C) //Attributes : RW #define PET_PMA3_MPLL_CTRL_MUX (PET_PMA3_COMMON_BASE + 4*0x2D) //Attributes : RW #define PET_PMA3_POWER_SUPPLY_SEL (PET_PMA3_COMMON_BASE + 4*0x30) //Attributes : RW #define PET_PMA3_PHY_RESET (PET_PMA3_COMMON_BASE + 4*0x31) //Attributes : RW #define PET_PMA3_REF_CLK_CTRL (PET_PMA3_COMMON_BASE + 4*0x40) //Attributes : RW #define PET_PMA3_REFA_CLK_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x41) //Attributes : RW #define PET_PMA3_REFA_CLK_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x42) //Attributes : RW #define PET_PMA3_REFA_CLK_STATUS (PET_PMA3_COMMON_BASE + 4*0x43) //Attributes : RO #define PET_PMA3_REFB_CLK_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x44) //Attributes : RW #define PET_PMA3_REFB_CLK_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x45) //Attributes : RW #define PET_PMA3_REFB_CLK_STATUS (PET_PMA3_COMMON_BASE + 4*0x46) //Attributes : RO #define PET_PMA3_REF_CLK_MUX (PET_PMA3_COMMON_BASE + 4*0x47) //Attributes : RW #define PET_PMA3_RES_ACK_IN (PET_PMA3_COMMON_BASE + 4*0x50) //Attributes : RW #define PET_PMA3_RES_ACK_OUT (PET_PMA3_COMMON_BASE + 4*0x51) //Attributes : RO #define PET_PMA3_RES_REQ_IN (PET_PMA3_COMMON_BASE + 4*0x52) //Attributes : RW #define PET_PMA3_RES_REQ_OUT (PET_PMA3_COMMON_BASE + 4*0x53) //Attributes : RO #define PET_PMA3_RTUNE_REQ (PET_PMA3_COMMON_BASE + 4*0x54) //Attributes : RW #define PET_PMA3_RTUNE_ACK (PET_PMA3_COMMON_BASE + 4*0x55) //Attributes : RO #define PET_PMA3_RTUNE_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x56) //Attributes : RW #define PET_PMA3_RTUNE_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x57) //Attributes : RW #define PET_PMA3_RTUNE_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x58) //Attributes : RW #define PET_PMA3_RX_BIAS_CURRENT_CTRL (PET_PMA3_COMMON_BASE + 4*0x59) //Attributes : RW #define PET_PMA3_CR_PARA_SEL (PET_PMA3_COMMON_BASE + 4*0x90) //Attributes : RW #define PET_PMA3_POWER_GATING_SIGNAL1 (PET_PMA3_COMMON_BASE + 4*0x60) //Attributes : RW #define PET_PMA3_POWER_GATING_SIGNAL2 (PET_PMA3_COMMON_BASE + 4*0x61) //Attributes : RO #define PET_PMA3_POWER_GATING_SIGNAL3 (PET_PMA3_COMMON_BASE + 4*0x62) //Attributes : RW #define PET_PMA3_SRAM_CTRL (PET_PMA3_COMMON_BASE + 4*0x68) //Attributes : RW #define PET_PMA3_SRAM_STATUS (PET_PMA3_COMMON_BASE + 4*0x69) //Attributes : RO #define PET_PMA3_SRIO_RST_REQ (PET_PMA3_COMMON_BASE + 4*0x6A) //Attributes : RO #define PET_PMA3_SRIO_GEN3_EN (PET_PMA3_COMMON_BASE + 4*0x6C) //Attributes : RW #define PET_PMA3_SRIO_RATE_OUT (PET_PMA3_COMMON_BASE + 4*0x6D) //Attributes : RW #define PET_PMA3_CPRI_RST_REQ (PET_PMA3_COMMON_BASE + 4*0x70) //Attributes : RW #define PET_PMA3_CPRI_RX_LOS (PET_PMA3_COMMON_BASE + 4*0x71) //Attributes : RW #define PET_PMA3_CPRI_SIGNAL_OK (PET_PMA3_COMMON_BASE + 4*0x72) //Attributes : RW #define PET_PMA3_CPRI_ENERGY_DET (PET_PMA3_COMMON_BASE + 4*0x73) //Attributes : RW #define PET_PMA3_CPRI_SIGDET (PET_PMA3_COMMON_BASE + 4*0x74) //Attributes : RW #define PET_PMA3_CPRI_PCS_STATUS (PET_PMA3_COMMON_BASE + 4*0x75) //Attributes : RO #define PET_PMA3_CPRI_PCS_STATUS_CTRL (PET_PMA3_COMMON_BASE + 4*0x76) //Attributes : RW #define PET_PMA3_ETH_ENERGY_DET (PET_PMA3_COMMON_BASE + 4*0x80) //Attributes : RW #define PET_PMA3_ETH_SPEED_CTRL (PET_PMA3_COMMON_BASE + 4*0x81) //Attributes : RO #define PET_PMA3_TX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF0) //Attributes : RW #define PET_PMA3_RPCS_TX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF1) //Attributes : RW #define PET_PMA3_RPCS_RX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF2) //Attributes : RW #define PET_PMA3_PMA_COM_SCRATCH (PET_PMA3_COMMON_BASE + 4*0xff) //Attributes : RW //The PMA PCS Register #define PET_PMA3_PCS_SOFT_RESET (PET_PMA3_PCS_BASE + 4*0x00) //Attributes : RW #define PET_PMA3_PCS_LOOPBACK_CTRL (PET_PMA3_PCS_BASE + 4*0x04) //Attributes : RW #define PET_PMA3_PCS_PRBS_UDP_SEND (PET_PMA3_PCS_BASE + 4*0x05) //Attributes : RW #define PET_PMA3_PCS_PRBS_SEND_ERRINS (PET_PMA3_PCS_BASE + 4*0x06) //Attributes : RW #define PET_PMA3_PCS_TXUDP_0 (PET_PMA3_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L #define PET_PMA3_PCS_TXUDP_1 (PET_PMA3_PCS_BASE + 4*0x08) //Attributes : RW_EXT #define PET_PMA3_PCS_TXUDP_2 (PET_PMA3_PCS_BASE + 4*0x09) //Attributes : RW_EXT #define PET_PMA3_PCS_TXUDP_3 (PET_PMA3_PCS_BASE + 4*0x0A) //Attributes : RW_EXT #define PET_PMA3_PCS_TXUDP_4 (PET_PMA3_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H #define PET_PMA3_PCS_PRBS_UDP_CHK (PET_PMA3_PCS_BASE + 4*0x10) //Attributes : RW #define PET_PMA3_PCS_RXUDP_0 (PET_PMA3_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L #define PET_PMA3_PCS_RXUDP_1 (PET_PMA3_PCS_BASE + 4*0x12) //Attributes : RW_EXT #define PET_PMA3_PCS_RXUDP_2 (PET_PMA3_PCS_BASE + 4*0x13) //Attributes : RW_EXT #define PET_PMA3_PCS_RXUDP_3 (PET_PMA3_PCS_BASE + 4*0x14) //Attributes : RW_EXT #define PET_PMA3_PCS_RXUDP_4 (PET_PMA3_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H #define PET_PMA3_PCS_RXPRBS_ERRCNT_L0 (PET_PMA3_PCS_BASE + 4*0x16) //Attributes : RO #define PET_PMA3_PCS_RXPRBS_ERRCNT_L1 (PET_PMA3_PCS_BASE + 4*0x17) //Attributes : RO #define PET_PMA3_PCS_RXPRBS_ERRCNT_L2 (PET_PMA3_PCS_BASE + 4*0x18) //Attributes : RO #define PET_PMA3_PCS_RXPRBS_ERRCNT_L3 (PET_PMA3_PCS_BASE + 4*0x19) //Attributes : RO #define PET_PMA3_PCS_NELP_FIFO_STATUS (PET_PMA3_PCS_BASE + 4*0x20) //Attributes : RO #define PET_PMA3_PCS_FELP_FIFO_STATUS (PET_PMA3_PCS_BASE + 4*0x21) //Attributes : RO #define PET_PMA3_PCS_BIT_REV_CTRL (PET_PMA3_PCS_BASE + 4*0x22) //Attributes : RW #define PET_PMA3_PCS_SOFT_PON_RST (PET_PMA3_PCS_BASE + 4*0xfe) //Attributes : RW #define PET_PMA3_PCS_PCS_SCRATCH (PET_PMA3_PCS_BASE + 4*0xff) //Attributes : RW #endif