// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : ospSwQueue.h
// Author        : 
// Created On    : 2023-01-19
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#ifndef __OSP_SW_QUEUE_H__
#define __OSP_SW_QUEUE_H__

#define SPU_APE_RFM_QUE_SIG_SIZE    (512)       /* 软件队列一个单位的长度为512字节 */
#define OSP_APE_RFM_SHELL_QUE_DEP   (80)         /* Shell软件队列的深度为8 */
#define OSP_APE_RFM_QUE_DEP         (256)
#define OSP_APE_RFM_MSG_QUE_DEP     (128)

#define OSP_APE_RFM_LOG_NUM         (12)
#define OSP_APE_RFM_SHELL_NUM       (24)

typedef enum OSP_SW_QUEUE_INDEX
{
    SW_LOG_APE0 = 0,
    SW_LOG_APE1,
    SW_LOG_APE2,
    SW_LOG_APE3,
    SW_LOG_APE4,
    SW_LOG_APE5,
    SW_LOG_APE6,
    SW_LOG_APE7,
    SW_LOG_PET_RFM0,
    SW_LOG_PET_RFM1,
    SW_LOG_ECS_RFM0,
    SW_LOG_ECS_RFM1,

    SW_SHELL_APE0, //12
    SW_SHELL_APE1,
    SW_SHELL_APE2,
    SW_SHELL_APE3,
    SW_SHELL_APE4,
    SW_SHELL_APE5,
    SW_SHELL_APE6,
    SW_SHELL_APE7,
    SW_SHELL_PET_RFM0,
    SW_SHELL_PET_RFM1,
    SW_SHELL_ECS_RFM0,
    SW_SHELL_ECS_RFM1,

    SW_SHELL_ECHO_APE0, //24
    SW_SHELL_ECHO_APE1,
    SW_SHELL_ECHO_APE2,
    SW_SHELL_ECHO_APE3,
    SW_SHELL_ECHO_APE4,
    SW_SHELL_ECHO_APE5,
    SW_SHELL_ECHO_APE6,
    SW_SHELL_ECHO_APE7,
    SW_SHELL_ECHO_PET_RFM0,
    SW_SHELL_ECHO_PET_RFM1,
    SW_SHELL_ECHO_ECS_RFM0,
    SW_SHELL_ECHO_ECS_RFM1,

    SW_QUEUE_MAX_INDEX,
}osp_sw_queue_index_e;

typedef enum OSP_SW_QUEUE_TYPE
{
    OSP_SW_QUEUE_LOG,       /* Log软件队列 */
    OSP_SW_QUEUE_SHELL,     /* Shell软件队列 */
    OSP_SW_QUEUE_MAX,       /* 软件队列最大类型 */
}osp_sw_queue_type_e;

typedef struct SPU_SW_QUEUE_MEM
{
    void*    pvaddr;
    uint16_t u16queue_id;
    uint16_t u16queue_type;
    uint8_t  u8queue_offset;
    uint8_t  u8queue_padding;
    uint16_t u16queue_mem_idx;
    uint16_t u16queue_dep;
    uint16_t u16queue_mask;
    uint16_t u16queue_padding;
    uint32_t u32queue_full_count;
    uint32_t u32queue_empty_count;
}spu_sw_queue_mem_t;

typedef struct SPU_SW_QUEUE_SHARE_INFO
{
    volatile uint16_t u16queue_deque_idx;
    volatile uint16_t u16queue_enque_idx;
    volatile uint16_t u16queue_alloc_idx;
    volatile uint16_t u16queue_free_idx;
    //volatile uint16_t u16queue_deque_count;
    //volatile uint16_t u16queue_enque_count;
    volatile uint16_t u16queue_msg[OSP_APE_RFM_QUE_DEP];
}spu_sw_queue_share_info_t;

#define SPU_SW_QUEUE_SHARE_INFO_SIZE    (sizeof(spu_sw_queue_share_info_t))

typedef enum OSP_SW_MSG_PKT_TYPE
{
    PKT_TYPE_LOG = 0x60,
    PKT_TYPE_STR_LOG = 0x61,
}osp_sw_msg_pkt_type_e;

typedef struct OSP_SW_MSG_INFO
{
    uint8_t  u8Head[2];
    uint16_t u16DataLen;
    uint8_t  u8PktType;
    uint8_t  u8CoreId;
    uint16_t u16Tail;
    int8_t   i8Data[0];
}osp_sw_msg_info_t;

#define OSP_SW_MSG_INFO_HEAD1   (0xAB)
#define OSP_SW_MSG_INFO_HEAD2   (0xEF)
#define OSP_SW_MSG_INFO_SIZE    sizeof(osp_sw_msg_info_t)

uint8_t osp_sw_queue_init(void);

uint8_t osp_sw_enque(osp_sw_queue_index_e emqueue_idx, int8_t *pi8addr);
uint8_t osp_sw_deque(osp_sw_queue_index_e emqueue_idx, osp_sw_msg_info_t **pstmsg_info);
int8_t *osp_sw_mem_malloc(osp_sw_queue_index_e emqueue_idx);


#endif /* __OSP_SW_QUEUE_H__ */