2023-07-12 14:14:31 +08:00

74 lines
1.6 KiB
C

// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : arm_csu.h
// Author : xinxin.li
// Created On : 2022-11-23
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef _ARM_CSU_H_
#define _ARM_CSU_H_
#include "typedef.h"
#define CSU_DEV_MAP_LEN 0xA00
#define VIR_ADDR_VAL(base, offset) (*((volatile uint32_t*)(base+offset)))
typedef struct _tagCsuDmaReg
{
uint32_t dmaAddrL;
uint32_t dmaAddrH;
uint32_t dmaYStepL;
uint32_t dmaYStepH;
uint32_t dmaZStepL;
uint32_t dmaZStepH;
uint32_t dmaXNum;
uint32_t dmaYNum;
uint32_t dmaAllNum : 24;
uint32_t dmaGran : 4;
uint32_t dmaSize : 4;
}stCsuDmaReg;
typedef struct _tagCsuDmaCmdL
{
uint32_t rCmd : 2;
uint32_t wCmd : 2;
uint32_t dmaType : 1;
uint32_t cacheMode : 1;
uint32_t continueNext : 1;
uint32_t continueLast : 1;
uint32_t idSrc : 5;
uint32_t idDst : 5;
uint32_t dmaTag : 5;
uint32_t flush : 1;
uint32_t ecpriEnd : 3;
uint32_t zNumValid : 1;
uint32_t allOrYNum : 2;
uint32_t allNumSel : 1;
uint32_t stall : 1;
}stCsuDmaCmdL;
int arm_csu_init();
// 0: not finished, 1: finished
int get_arm_csu_status(uint8_t tag);
int arm_csu_wait_done(uint8_t tag);
int arm_csu_wait_all_done(void);
int get_free_reg_group(uint8_t tag);
int get_free_channel();
int arm_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t dataLen);
#endif