268 lines
5.8 KiB
C
268 lines
5.8 KiB
C
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
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// FileName : ucp_api_rfic.h
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// Author : Boheng Lin bhlin919@126.com
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// Date First Issued : 2023-03-04 17:39:00 PM
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// Last Modified :
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef UCP_API_RFIC_H_
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#define UCP_API_RFIC_H_
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#include <stdio.h>
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#include <stdlib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \brief define board type
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*/
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enum {
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HW_UNKNOW = 0,
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HW_EVMT,
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HW_EVMF,
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HW_EVB,
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HW_EVMY,
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HW_OTHER = 254,
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HW_MAX = 255
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};
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/**
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* \brief define some paras for cell init
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*/
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enum {
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CFG_SAMPLERATE_61_44MHZ = 61440000,
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CFG_SAMPLERATE_122_88MHZ = 122880000,
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CFG_SAMPLERATE_245_76MHZ = 245760000
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};
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enum {
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CFG_BW_20MHZ = 20000000,
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CFG_BW_50MHZ = 50000000,
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CFG_BW_100MHZ = 100000000,
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CFG_BW_200MHZ = 200000000,
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CFG_BW_240MHZ = 240000000
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};
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enum {
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CFG_1ANT = 1,
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CFG_2ANT = 2,
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CFG_3ANT = 3,
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CFG_4ANT = 4,
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CFG_5ANT = 5,
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CFG_6ANT = 6,
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CFG_7ANT = 7,
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CFG_8ANT = 8
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};
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enum {
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CFG_TDD = 0,
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CFG_FDD = 1
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};
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enum {
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CFG_NORX = 0,
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CFG_TLO_ORX = 1,
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CFG_ALO_ORX = 2,
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CFG_RLO_ORX = 3
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};
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enum {
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CFG_204B= 0,
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CFG_204C = 1
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};
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enum {
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CFG_NONE_LOG = 0,
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CFG_LOG = 1
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};
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/**
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* \brief define cal para struct
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*/
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typedef struct ucp_rfic_calPara
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{
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int16_t calOrxGainIndex;
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int16_t calChAttPara[16];
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} ucp_rfic_calPara_t;
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//**********************************************************************************
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// system option layer
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/**
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* \brief Sets up the cell's default config
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*
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* \param sampleRate is Transceiver's sample Rate (Unit hz. 122.88Mhz 245.76Mhz or 61.44Mhz).
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* \param bw is bandwidth (Unit hz).
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* \param antNumb is the number of antennas (range 1 ~ 8).
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* \param enFdd (0: TDD mode, 1: FDD mode).
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* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo).
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* \param en204C(0: 204B mode, 1: 204C mode).
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* \param enUcpLog(0: disable configture Log, 1: enable configture Log).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_RFIC_CellInit(uint64_t sampleRate,
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uint64_t bw,
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uint16_t antNumb,
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uint16_t enFdd,
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uint16_t enOrx,
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uint16_t en204C,
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uint16_t enUcpLog);
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/**
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* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation.
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* then process Initialize transceiver
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*
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* \param txLo is Transmit local frequency (Unit hz).
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* \param rxLo is Receive local frequency (Unit hz).
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* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20).
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* \param initGain is Initialize rx Gain index (Unit db, range 183 ~ 255).
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* \param auxLo is orx local frequency (Unit hz).
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* \param calPara is paras for RX QEC、TX att cal and so on
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* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt,
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uint16_t initGain, uint64_t auxLo, uint16_t enOrx,
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ucp_rfic_calPara_t calPara);
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/**
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* \brief delete cell.
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*
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* \param void.
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*
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* \retval void.
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*/
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extern int32_t UCP_API_RFIC_CellDelete(void);
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//**********************************************************************************
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// chip option layer
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// TRANSCEIVER
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/**
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* \brief transceiver chip hardware reset.
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*
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* \param void.
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*
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* \retval void.
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*/
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extern int32_t UCP_API_TRANSCEIVER_Reset(void);
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/**
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* \brief Sets up the transceiver's MGC Mod.
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*
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* \param en, if set 1, MGC Mode; set 0, AGC Mode.
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en);
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/**
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* \brief Sets up the transceiver's rx gain at MGC mode.
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*
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* \param gain_db (Unit db, range 0~36, step 0.5db).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db);
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/**
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* \brief Get the transceiver's rx gain.
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*
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* \param gain_db (Unit db, range 0~36, step 0.5db).
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*
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* \retval gain_db (Unit db, range 0~36, step 0.5db).
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*/
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extern double UCP_API_TRANSCEIVER_Gain_Get(void);
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/**
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* \brief Set up the transceiver's tx attenuation.
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*
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* \param att_db (Unit db, range 0~20).
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*
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* \retval 0.
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*/
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extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db);
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/**
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* \brief Get the transceiver's tx attenuation.
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*
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* \retval att_db (Unit db, range 0~20).
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*/
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extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void);
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//**********************************************************************************
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// CLOCKGEN
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/**
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* \brief clockGen chip hardware reset.
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*
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* \param void.
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*
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* \retval void.
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*/
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extern void UCP_API_CLOCKGEN_Reset(void);
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/**
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* \brief clockGen chip init function.
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*
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* \param void.
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*
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* \retval void.
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*/
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extern int32_t UCP_API_CLOCKGEN_Init(void);
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/**
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* \brief Get the status of clockGen chip's pll.
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*
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* \param void.
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*
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* \retval lock code.
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*/
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extern uint8_t UCP_API_CLOCKGEN_LockStatus(void);
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/**
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* \brief gpio of rf controlling
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*
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* \param setting
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*
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* \retval none.
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*/
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extern void UCP_API_GPIO_Tx (void);
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extern void UCP_API_GPIO_Rx (void);
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extern void UCP_API_GPIO_Off (void);
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extern void UCP_API_GPIO_OrxOn (void);
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extern void UCP_API_GPIO_OrxOff (void);
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extern void UCP_API_GPIO_TrigOn (void);
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extern void UCP_API_GPIO_TrigOff (void);
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/**
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* \brief Get board's indx
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*
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* \param void
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*
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* \retval
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HW_UNKNOW = 0
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HW_EVMT = 1
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HW_EVMF = 2
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HW_EVB = 3
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HW_EVMY = 4
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HW_OTHER = 254
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HW_MAX = 255
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*/
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extern uint8_t UCP_API_RFIC_GetBoardInfo (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* #ifndef UCP_API_RFIC_H_ */
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