207 lines
6.4 KiB
C
207 lines
6.4 KiB
C
//******************** (C) COPYRIGHT 2022 SmartLogic*******************************
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// FileName : ucp_api_jesd.h
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// Author : Boheng Lin bhlin919@126.com
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// Date First Issued : 2023-03-04 14:37:50 PM
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// Last Modified :
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef UCP_API_JESD_H_
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#define UCP_API_JESD_H_
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \brief the max channels of trx
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*/
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#define MAX_UCP_JESD_TRX_CH (4)
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/**
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* \brief Data structure to hold UCP API State
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*/
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typedef enum ucp_jesd_States
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{
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UCP_JESD_STATE_POWERONRESET = 0x00,
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UCP_JESD_STATE_JSCTRLOK = 0x01,
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UCP_JESD_STATE_CRGOK = 0x02,
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UCP_JESD_STATE_SUBCTRLOK = 0x04,
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UCP_JESD_STATE_204COREOK = 0x08,
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UCP_JESD_STATE_PMAOK = 0x10,
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UCP_JESD_STATE_TIMEROK = 0x20,
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UCP_JESD_STATE_RUN = 0x40
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} ucp_jesd_States_e;
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/**
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* \brief Data structure to ape working step
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*/
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typedef enum ucp_jesd_ApeWorkStep
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{
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UCP_JESD_APE_POWERONRESET = 0x00,
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UCP_JESD_APE_CLOCKGENRUN = 0x01,
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UCP_JESD_APE_CELLRUN = 0x02,
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} ucp_jesd_ApeWorkStep_e;
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/**
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* \brief Data structure to the level status of trx's control pins.
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*/
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typedef enum ucp_jesd_gpioEnableLevel
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{
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UCP_JESD_TRX_GPIO_DISABLE = 0x00,
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UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01,
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UCP_JESD_TRX_GPIO_VALID_LOW = 0x02,
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} ucp_jesd_gpioEnableLevel_e;
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/**
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* \brief Data structure to contrl pins of rf's trx
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*/
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typedef struct ucp_jesd_gpio {
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uint8_t port;
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uint8_t pin;
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uint8_t enableLevel;
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} ucp_jesd_gpio_t;
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typedef struct ucp_jesd_TrxGpio {
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ucp_jesd_gpio_t tx;
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ucp_jesd_gpio_t rx;
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ucp_jesd_gpio_t orx;
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} ucp_jesd_TrxGpio_t;
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/**
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* \brief Data structure to configure of trx's contrl pins
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*/
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typedef struct ucp_jesd_TrxGpioCfg {
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uint8_t maxCh;
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int32_t uldelay;
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int32_t dldelay;
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ucp_jesd_gpio_t triger;
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ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH];
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} ucp_jesd_TrxGpioCfg_t;
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/**
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* \brief Data structure to hold digital clock settings
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*/
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typedef struct ucp_jesd_CommonSettings
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{
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uint32_t devClock_kHz; /*!< Device clock frequency in kHz */
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uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */
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uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */
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uint8_t jesdSubClass;
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} ucp_jesd_CommonSettings_t;
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/**
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* \brief Data structure to hold UCP JESD204b Framer configuration settings
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*/
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typedef struct ucp_jesd_FrmCfg
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{
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uint8_t enable;
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uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */
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uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */
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uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */
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uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */
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uint8_t jesd204E; /*!< JESD204C E parameter */
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uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */
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uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
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uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */
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} ucp_jesd_FrmCfg_t;
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/**
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* \brief Data structure to hold the settings for the deframer configuration
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*/
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typedef struct ucp_jesd_DfrmCfg
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{
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uint8_t enable;
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uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */
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uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */
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uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */
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uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */
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uint8_t jesd204E; /*!< JESD204C E parameter */
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uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */
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uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
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uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */
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} ucp_jesd_DfrmCfg_t;
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/**
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* \brief Data structure to hold ucp JESD Framer and Deframer configuration information
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*/
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typedef struct ucp_jesd_Init
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{
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ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */
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ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */
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ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */
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} ucp_jesd_Init_t;
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/**
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* \brief get jesd module's version
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*
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* \param void
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*
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* \retval version.
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*/
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extern uint32_t UCP_API_JESD_Version(void);
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/**
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* \brief Sets up the ape work step
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*
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* \param step
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* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value
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* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value
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* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value
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*
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* \retval none.
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*/
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extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step);
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/**
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* \brief Sets up the gpios of tx and rx
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*
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* \param setting
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*
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* \retval none.
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*/
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extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile);
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/**
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* \brief Sets up the ucp4008 jesd's para setting
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*
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* \param setting
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*
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* \retval none.
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*/
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extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting);
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/**
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* \brief Sets up the ucp4008 jesd's para setting
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*
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* \param setting
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*
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* \retval none.
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*/
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extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting);
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/**
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* \brief Sets up the ucp4008 jesd's para setting
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*
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* \param setting
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*
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* \retval none.
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*/
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extern void UCP_API_JESD_CellDelete (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* #ifndef UCP_API_JESD_H_ */
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