155 lines
8.2 KiB
C
155 lines
8.2 KiB
C
//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
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// FileName : dw_apb_gpio.h
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// Author : lijian, jian.li@smartlogictech.com
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// Date First Issued : 2019-03-29 03:39:50 PM
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// Last Modified : 2020-05-13 10:20:01 AM
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// Description :
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// ------------------------------------------------------------
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// Modification History:
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// Version Date Author Modification Description
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//
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//**********************************************************************************
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#define DW_APB_GPIO0_BASE 0x04450000
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#define DW_APB_GPIO1_BASE 0x04d10000
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#define GPIO_SWPORTA_DR_OFFSET 0x00
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#define GPIO_SWPORTA_DDR_OFFSET 0x04
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#define GPIO_SWPORTA_CTL_OFFSET 0x08
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#define GPIO_SWPORTB_DR_OFFSET 0x0C
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#define GPIO_SWPORTB_DDR_OFFSET 0x10
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#define GPIO_SWPORTB_CTL_OFFSET 0x14
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#define GPIO_SWPORTC_DR_OFFSET 0x18
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#define GPIO_SWPORTC_DDR_OFFSET 0x1C
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#define GPIO_SWPORTC_CTL_OFFSET 0x20
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#define GPIO_SWPORTD_DR_OFFSET 0x24
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#define GPIO_SWPORTD_DDR_OFFSET 0x28
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#define GPIO_SWPORTD_CTL_OFFSET 0x2C
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#define GPIO_INTEN_OFFSET 0x30
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#define GPIO_INTMASK_OFFSET 0x34
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#define GPIO_INTTYPE_LEVEL_OFFSET 0x38
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#define GPIO_INT_POLARITY_OFFSET 0x3C
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#define GPIO_INTSTATUS_OFFSET 0x40
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#define GPIO_RAW_INTSTATUS_OFFSET 0x44
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#define GPIO_DEBOUNCE_OFFSET 0x48
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#define GPIO_PORTA_EOI_OFFSET 0x4C
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#define GPIO_EXT_PORTA_OFFSET 0x50
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#define GPIO_EXT_PORTB_OFFSET 0x54
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#define GPIO_EXT_PORTC_OFFSET 0x58
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#define GPIO_EXT_PORTD_OFFSET 0x5C
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#define GPIO_LS_SYNC_OFFSET 0x60
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#define GPIO_ID_CODE_OFFSET 0x64
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#define GPIO_VER_ID_CODE_OFFSET 0x6C
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#define GPIO_CONFIGID_REG2_OFFSET 0x70
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#define GPIO_CONFIGID_REG1_OFFSET 0x74
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#define GPIO0_SWPORTA_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTA_DR_OFFSET)
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#define GPIO0_SWPORTA_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTA_DDR_OFFSET)
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#define GPIO0_SWPORTA_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTA_CTL_OFFSET)
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#define GPIO0_SWPORTB_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTB_DR_OFFSET)
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#define GPIO0_SWPORTB_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTB_DDR_OFFSET)
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#define GPIO0_SWPORTB_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTB_CTL_OFFSET)
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#define GPIO0_SWPORTC_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTC_DR_OFFSET)
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#define GPIO0_SWPORTC_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTC_DDR_OFFSET)
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#define GPIO0_SWPORTC_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTC_CTL_OFFSET)
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#define GPIO0_SWPORTD_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTD_DR_OFFSET)
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#define GPIO0_SWPORTD_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTD_DDR_OFFSET)
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#define GPIO0_SWPORTD_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTD_CTL_OFFSET)
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#define GPIO0_INTEN (DW_APB_GPIO0_BASE + GPIO_INTEN_OFFSET)
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#define GPIO0_INTMASK (DW_APB_GPIO0_BASE + GPIO_INTMASK_OFFSET)
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#define GPIO0_INTTYPE_LEVEL (DW_APB_GPIO0_BASE + GPIO_INTTYPE_LEVEL_OFFSET)
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#define GPIO0_INT_POLARITY (DW_APB_GPIO0_BASE + GPIO_INT_POLARITY_OFFSET)
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#define GPIO0_INTSTATUS (DW_APB_GPIO0_BASE + GPIO_INTSTATUS_OFFSET)
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#define GPIO0_RAW_INTSTATUS (DW_APB_GPIO0_BASE + GPIO_RAW_INTSTATUS_OFFSET)
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#define GPIO0_DEBOUNCE (DW_APB_GPIO0_BASE + GPIO_DEBOUNCE_OFFSET)
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#define GPIO0_PORTA_EOI (DW_APB_GPIO0_BASE + GPIO_PORTA_EOI_OFFSET)
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#define GPIO0_EXT_PORTA (DW_APB_GPIO0_BASE + GPIO_EXT_PORTA_OFFSET)
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#define GPIO0_EXT_PORTB (DW_APB_GPIO0_BASE + GPIO_EXT_PORTB_OFFSET)
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#define GPIO0_EXT_PORTC (DW_APB_GPIO0_BASE + GPIO_EXT_PORTC_OFFSET)
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#define GPIO0_EXT_PORTD (DW_APB_GPIO0_BASE + GPIO_EXT_PORTD_OFFSET)
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#define GPIO0_LS_SYNC (DW_APB_GPIO0_BASE + GPIO_LS_SYNC_OFFSET)
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#define GPIO0_ID_CODE (DW_APB_GPIO0_BASE + GPIO_ID_CODE_OFFSET)
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#define GPIO0_VER_ID_CODE (DW_APB_GPIO0_BASE + GPIO_VER_ID_CODE_OFFSET)
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#define GPIO0_CONFIGID_REG2 (DW_APB_GPIO0_BASE + GPIO_CONFIGID_REG2_OFFSET)
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#define GPIO0_CONFIGID_REG1 (DW_APB_GPIO0_BASE + GPIO_CONFIGID_REG1_OFFSET)
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#define GPIO0PING_1BIT_WR (GPIO0_SWPORTA_DR)
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#define GPIO1_SWPORTA_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTA_DR_OFFSET)
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#define GPIO1_SWPORTA_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTA_DDR_OFFSET)
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#define GPIO1_SWPORTA_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTA_CTL_OFFSET)
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#define GPIO1_SWPORTB_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTB_DR_OFFSET)
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#define GPIO1_SWPORTB_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTB_DDR_OFFSET)
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#define GPIO1_SWPORTB_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTB_CTL_OFFSET)
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#define GPIO1_SWPORTC_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTC_DR_OFFSET)
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#define GPIO1_SWPORTC_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTC_DDR_OFFSET)
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#define GPIO1_SWPORTC_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTC_CTL_OFFSET)
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#define GPIO1_SWPORTD_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTD_DR_OFFSET)
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#define GPIO1_SWPORTD_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTD_DDR_OFFSET)
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#define GPIO1_SWPORTD_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTD_CTL_OFFSET)
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#define GPIO1_INTEN (DW_APB_GPIO1_BASE + GPIO_INTEN_OFFSET)
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#define GPIO1_INTMASK (DW_APB_GPIO1_BASE + GPIO_INTMASK_OFFSET)
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#define GPIO1_INTTYPE_LEVEL (DW_APB_GPIO1_BASE + GPIO_INTTYPE_LEVEL_OFFSET)
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#define GPIO1_INT_POLARITY (DW_APB_GPIO1_BASE + GPIO_INT_POLARITY_OFFSET)
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#define GPIO1_INTSTATUS (DW_APB_GPIO1_BASE + GPIO_INTSTATUS_OFFSET)
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#define GPIO1_RAW_INTSTATUS (DW_APB_GPIO1_BASE + GPIO_RAW_INTSTATUS_OFFSET)
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#define GPIO1_DEBOUNCE (DW_APB_GPIO1_BASE + GPIO_DEBOUNCE_OFFSET)
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#define GPIO1_PORTA_EOI (DW_APB_GPIO1_BASE + GPIO_PORTA_EOI_OFFSET)
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#define GPIO1_EXT_PORTA (DW_APB_GPIO1_BASE + GPIO_EXT_PORTA_OFFSET)
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#define GPIO1_EXT_PORTB (DW_APB_GPIO1_BASE + GPIO_EXT_PORTB_OFFSET)
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#define GPIO1_EXT_PORTC (DW_APB_GPIO1_BASE + GPIO_EXT_PORTC_OFFSET)
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#define GPIO1_EXT_PORTD (DW_APB_GPIO1_BASE + GPIO_EXT_PORTD_OFFSET)
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#define GPIO1_LS_SYNC (DW_APB_GPIO1_BASE + GPIO_LS_SYNC_OFFSET)
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#define GPIO1_ID_CODE (DW_APB_GPIO1_BASE + GPIO_ID_CODE_OFFSET)
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#define GPIO1_VER_ID_CODE (DW_APB_GPIO1_BASE + GPIO_VER_ID_CODE_OFFSET)
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#define GPIO1_CONFIGID_REG2 (DW_APB_GPIO1_BASE + GPIO_CONFIGID_REG2_OFFSET)
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#define GPIO1_CONFIGID_REG1 (DW_APB_GPIO1_BASE + GPIO_CONFIGID_REG1_OFFSET)
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#define GPIO1PING_1BIT_WR (GPIO1_SWPORTA_DR)
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#define CC_GPIO_ADD_ENCODED_PARAM 0x1
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#define CC_GPIO_APB_DATA_WIDTH 32
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#define CC_GPIO_NUM_PORTS 4
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#define CC_GPIO_ID 0
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#define CC_GPIO_DEBOUNCE 0
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#define CC_GPIO_ID_WIDTH 32
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#define CC_GPIO_ID_NUM 0x0
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#define CC_GPIO_REV_ID 0
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#define CC_GPIO_REV_ID_WIDTH 32
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#define CC_GPIO_REV_ID_NUM 0x0
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#define CC_GPIO_PWIDTH_A 8
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#define CC_GPIO_PORTA_SINGLE_CTL 1
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#define CC_GPIO_SWPORTA_RESET 0x0
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#define CC_GPIO_HW_PORTA 1
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#define CC_GPIO_DFLT_DIR_A 0
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#define CC_GPIO_DFLT_SRC_A 0
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#define CC_GPIO_PORTA_INTR 1
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#define CC_GPIO_INT_POL 0
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#define CC_GPIO_INTR_IO 0
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#define CC_GPIO_PA_SYNC_EXT_DATA 1
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#define CC_GPIO_PA_SYNC_INTERRUPTS 1
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#define CC_GPIO_PWIDTH_B 32
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#define CC_GPIO_PORTB_SINGLE_CTL 1
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#define CC_GPIO_SWPORTB_RESET 0x0
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#define CC_GPIO_HW_PORTB 0
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#define CC_GPIO_DFLT_DIR_B 0
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#define CC_GPIO_DFLT_SRC_B 0
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#define CC_GPIO_PB_SYNC_EXT_DATA 1
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#define CC_GPIO_PWIDTH_C 32
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#define CC_GPIO_PORTC_SINGLE_CTL 1
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#define CC_GPIO_SWPORTC_RESET 0x0
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#define CC_GPIO_HW_PORTC 0
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#define CC_GPIO_DFLT_DIR_C 1
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#define CC_GPIO_DFLT_SRC_C 0
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#define CC_GPIO_PC_SYNC_EXT_DATA 0
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#define CC_GPIO_PWIDTH_D 8
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#define CC_GPIO_PORTD_SINGLE_CTL 1
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#define CC_GPIO_SWPORTD_RESET 0x0
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#define CC_GPIO_HW_PORTD 1
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#define CC_GPIO_DFLT_DIR_D 1
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#define CC_GPIO_DFLT_SRC_D 1
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#define CC_GPIO_PD_SYNC_EXT_DATA 1
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#endif
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