90 lines
5.0 KiB
C
90 lines
5.0 KiB
C
/*********************************************************************
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*
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* Filename: ucp_js_ctrl.h
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*
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* Created: 2021-11-08 10:54:34 AM
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* Last Modified: 2022-06-08 05:32:38 PM
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* Author: LiPin , lip2014@ia.ac.cn
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* Organization: Beijing Smart Logic Technology Co., Ltd.
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*
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* Description:
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*
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*
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********************************************************************/
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#ifndef __JS_CTRL__
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#define __JS_CTRL__
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//The JESD And SRIO SubCtrl Base Addr
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#define JS_CTRL_BASE 0x05f50000
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//The JESD ECPRI CPRI SRIO SubCtrl Base Addr
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#define JECS_CTRL_BASE 0x08460000
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//------------------------------------JS SYSTEM--------------------------------//
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//JESD And SRIO SubCtrl Reg Addr
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#define JS_CTRL_CLK_SEL (JS_CTRL_BASE + 4*18) //RW
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#define JS_CTRL_TX_TMR_EN_CTRL (JS_CTRL_BASE + 4*19) //RW
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#define JS_PHY_BS_CTRL (JS_CTRL_BASE + 4*20)
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#define JS_CTRL_PHY_MISC_SEL_0 (JS_CTRL_BASE + 4*22) //RW
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#define JS_CTRL_PHY_INT_CLK_SEL_SUB0 (JS_CTRL_BASE + 4*23) //RW
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#define JS_CTRL_PHY_OUT_TEST_CLK_SEL_SUB0 (JS_CTRL_BASE + 4*24) //RW
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#define JS_CTRL_PHY_MISC_SEL_1 (JS_CTRL_BASE + 4*53) //RW
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#define JS_CTRL_SRIO0_AWADDR_H (JS_CTRL_BASE + 4*54) //RW
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#define JS_CTRL_SRIO0_ARADDR_H (JS_CTRL_BASE + 4*55) //RW
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#define JS_CTRL_JESD204_QOS (JS_CTRL_BASE + 4*56) //RW
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#define JS_CTRL_RFC_QOS (JS_CTRL_BASE + 4*57) //RW
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#define JS_CTRL_JESD204_MODE_SEL (JS_CTRL_BASE + 4*58) //RW
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#define JS_SERDES_CLK_EN (JS_CTRL_BASE + 4*59) //RW
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//------------------------------------ES SYSTEM--------------------------------//
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//JESD ECPRI CPRI SRIO SubCtrl Reg Addr
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#define JECS_CTRL_RFM_USER0 (JECS_CTRL_BASE + 4*0) //RW
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#define JECS_CTRL_RFM_USER1 (JECS_CTRL_BASE + 4*1) //RW
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#define JECS_CTRL_RFM_USER2 (JECS_CTRL_BASE + 4*2) //RW
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#define JECS_CTRL_RFM_USER3 (JECS_CTRL_BASE + 4*3) //RW
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#define JECS_CTRL_RFM_USER4 (JECS_CTRL_BASE + 4*4) //RW
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#define JECS_CTRL_RFM_USER5 (JECS_CTRL_BASE + 4*5) //RW
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#define JECS_CTRL_RFM_ADDR_CTRL (JECS_CTRL_BASE + 4*6) //RW
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#define JECS_CTRL_QOS_M3_SRIO_AXIM (JECS_CTRL_BASE + 4*7) //RW
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#define JECS_CTRL_PHY_CLK_SEL (JECS_CTRL_BASE + 4*8) //RW
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#define JECS_CTRL_PROTOCOL_SEL (JECS_CTRL_BASE + 4*9) //RW
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#define JECS_CTRL_RFM_INT_MASK0 (JECS_CTRL_BASE + 10*4)
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#define JECS_CTRL_RFM_INT_MASK1 (JECS_CTRL_BASE + 11*4)
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#define JECS_CTRL_RFM_INT_MASK2 (JECS_CTRL_BASE + 12*4)
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#define JECS_CTRL_RFM_INT_MASK3 (JECS_CTRL_BASE + 13*4)
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#define JECS_CTRL_RFM_INT_MASK4 (JECS_CTRL_BASE + 14*4)
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#define JECS_CTRL_RFM_INT_MASK5 (JECS_CTRL_BASE + 15*4)
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#define JECS_CTRL_RFM_INT_MASK6 (JECS_CTRL_BASE + 16*4)
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#define JECS_CTRL_RFM_INT_MASK7 (JECS_CTRL_BASE + 17*4)
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#define JECS_CTRL_RFM_INT_MASK8 (JECS_CTRL_BASE + 18*4)
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#define JECS_CTRL_RFM_INT_MASK9 (JECS_CTRL_BASE + 19*4)
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#define JECS_CTRL_RFM_INT_MASK10 (JECS_CTRL_BASE + 20*4)
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#define JECS_CTRL_RFM_INT_MASK11 (JECS_CTRL_BASE + 21*4)
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#define JECS_CTRL_RFM_INT_MASK12 (JECS_CTRL_BASE + 22*4)
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#define JECS_CTRL_RFM_INT_MASK13 (JECS_CTRL_BASE + 23*4)
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#define JECS_CTRL_RFM_INT_MASK14 (JECS_CTRL_BASE + 24*4)
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#define JECS_CTRL_RFM_INT_MASK15 (JECS_CTRL_BASE + 25*4)
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#define JECS_CTRL_CTC_INT0 (JECS_CTRL_BASE + 26*4)
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#define JECS_CTRL_CTC_INT1 (JECS_CTRL_BASE + 27*4)
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#define JECS_CTRL_CTC_INT2 (JECS_CTRL_BASE + 28*4)
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#define JECS_CTRL_CTC_INT3 (JECS_CTRL_BASE + 29*4)
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#define JECS_CTRL_CTC_INT4 (JECS_CTRL_BASE + 30*4)
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#define JECS_CTRL_CTC_INT5 (JECS_CTRL_BASE + 31*4)
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#define JECS_CTRL_CTC_INT6 (JECS_CTRL_BASE + 32*4)
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#define JECS_CTRL_CPRI_GMAC_PHY_INT (JECS_CTRL_BASE + 33*4)
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#define JECS_PHY_BS_CTRL (JECS_CTRL_BASE + 34*4)
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#define JECS_CTRL_ECPRI_QOSH (JECS_CTRL_BASE + 35*4)
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#define JECS_CTRL_ECPRI_QOSL (JECS_CTRL_BASE + 36*4)
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#define JECS_CTRL_CSU_BUS_CTRL (JECS_CTRL_BASE + 37*4)
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#define JECS_CTRL_CPRI_PAD_CTRL (JECS_CTRL_BASE + 38*4)
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#define JECS_CLK_GATE_CTRL (JECS_CTRL_BASE + 39*4)
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#define JECS_PMA_TIMER_CTRL (JECS_CTRL_BASE + 41*4)
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#endif
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